2 * MPC8323E EMDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
13 model = "MPC8323EMDS";
14 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
33 d-cache-line-size = <20>; // 32 bytes
34 i-cache-line-size = <20>; // 32 bytes
35 d-cache-size = <4000>; // L1, 16K
36 i-cache-size = <4000>; // L1, 16K
37 timebase-frequency = <0>;
39 clock-frequency = <0>;
44 device_type = "memory";
45 reg = <00000000 08000000>;
49 device_type = "board-control";
50 reg = <f8000000 8000>;
57 ranges = <0 e0000000 00100000>;
58 reg = <e0000000 00000200>;
59 bus-frequency = <7DE2900>;
62 device_type = "watchdog";
63 compatible = "mpc83xx_wdt";
71 compatible = "fsl-i2c";
74 interrupt-parent = < &ipic >;
78 compatible = "dallas,ds1374";
83 serial0: serial@4500 {
85 device_type = "serial";
86 compatible = "ns16550";
88 clock-frequency = <0>;
90 interrupt-parent = < &ipic >;
93 serial1: serial@4600 {
95 device_type = "serial";
96 compatible = "ns16550";
98 clock-frequency = <0>;
100 interrupt-parent = < &ipic >;
104 device_type = "crypto";
106 compatible = "talitos";
109 interrupt-parent = < &ipic >;
112 channel-fifo-len = <18>;
113 exec-units-mask = <0000004c>;
114 descriptor-types-mask = <0122003f>;
118 interrupt-controller;
119 #address-cells = <0>;
120 #interrupt-cells = <2>;
122 device_type = "ipic";
127 device_type = "par_io";
132 /* port pin dir open_drain assignment has_irq */
133 3 4 3 0 2 0 /* MDIO */
134 3 5 1 0 2 0 /* MDC */
135 0 d 2 0 1 0 /* RX_CLK (CLK9) */
136 3 18 2 0 1 0 /* TX_CLK (CLK10) */
137 1 0 1 0 1 0 /* TxD0 */
138 1 1 1 0 1 0 /* TxD1 */
139 1 2 1 0 1 0 /* TxD2 */
140 1 3 1 0 1 0 /* TxD3 */
141 1 4 2 0 1 0 /* RxD0 */
142 1 5 2 0 1 0 /* RxD1 */
143 1 6 2 0 1 0 /* RxD2 */
144 1 7 2 0 1 0 /* RxD3 */
145 1 8 2 0 1 0 /* RX_ER */
146 1 9 1 0 1 0 /* TX_ER */
147 1 a 2 0 1 0 /* RX_DV */
148 1 b 2 0 1 0 /* COL */
149 1 c 1 0 1 0 /* TX_EN */
150 1 d 2 0 1 0>;/* CRS */
154 /* port pin dir open_drain assignment has_irq */
155 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
156 3 6 2 0 1 0 /* TX_CLK (CLK8) */
157 1 12 1 0 1 0 /* TxD0 */
158 1 13 1 0 1 0 /* TxD1 */
159 1 14 1 0 1 0 /* TxD2 */
160 1 15 1 0 1 0 /* TxD3 */
161 1 16 2 0 1 0 /* RxD0 */
162 1 17 2 0 1 0 /* RxD1 */
163 1 18 2 0 1 0 /* RxD2 */
164 1 19 2 0 1 0 /* RxD3 */
165 1 1a 2 0 1 0 /* RX_ER */
166 1 1b 1 0 1 0 /* TX_ER */
167 1 1c 2 0 1 0 /* RX_DV */
168 1 1d 2 0 1 0 /* COL */
169 1 1e 1 0 1 0 /* TX_EN */
170 1 1f 2 0 1 0>;/* CRS */
176 #address-cells = <1>;
180 ranges = <0 e0100000 00100000>;
181 reg = <e0100000 480>;
183 bus-frequency = <BCD3D80>;
186 device_type = "muram";
187 ranges = <0 00010000 00004000>;
196 compatible = "fsl_spi";
199 interrupt-parent = < &qeic >;
205 compatible = "fsl_spi";
208 interrupt-parent = < &qeic >;
214 compatible = "qe_udc";
215 reg = <6c0 40 8B00 100>;
217 interrupt-parent = < &qeic >;
222 device_type = "network";
223 compatible = "ucc_geth";
229 interrupt-parent = < &qeic >;
230 local-mac-address = [ 00 00 00 00 00 00 ];
231 rx-clock-name = "clk9";
232 tx-clock-name = "clk10";
233 phy-handle = < &phy3 >;
234 pio-handle = < &pio3 >;
238 device_type = "network";
239 compatible = "ucc_geth";
245 interrupt-parent = < &qeic >;
246 local-mac-address = [ 00 00 00 00 00 00 ];
247 rx-clock-name = "clk7";
248 tx-clock-name = "clk8";
249 phy-handle = < &phy4 >;
250 pio-handle = < &pio4 >;
254 #address-cells = <1>;
257 device_type = "mdio";
258 compatible = "ucc_geth_phy";
260 phy3: ethernet-phy@03 {
261 interrupt-parent = < &ipic >;
264 device_type = "ethernet-phy";
266 phy4: ethernet-phy@04 {
267 interrupt-parent = < &ipic >;
270 device_type = "ethernet-phy";
275 interrupt-controller;
276 device_type = "qeic";
277 #address-cells = <0>;
278 #interrupt-cells = <1>;
281 interrupts = <20 8 21 8>; //high:32 low:33
282 interrupt-parent = < &ipic >;
288 interrupt-map-mask = <f800 0 0 7>;
290 /* IDSEL 0x11 AD17 */
291 8800 0 0 1 &ipic 14 8
292 8800 0 0 2 &ipic 15 8
293 8800 0 0 3 &ipic 16 8
294 8800 0 0 4 &ipic 17 8
296 /* IDSEL 0x12 AD18 */
297 9000 0 0 1 &ipic 16 8
298 9000 0 0 2 &ipic 17 8
299 9000 0 0 3 &ipic 14 8
300 9000 0 0 4 &ipic 15 8
302 /* IDSEL 0x13 AD19 */
303 9800 0 0 1 &ipic 17 8
304 9800 0 0 2 &ipic 14 8
305 9800 0 0 3 &ipic 15 8
306 9800 0 0 4 &ipic 16 8
309 a800 0 0 1 &ipic 14 8
310 a800 0 0 2 &ipic 15 8
311 a800 0 0 3 &ipic 16 8
312 a800 0 0 4 &ipic 17 8
315 b000 0 0 1 &ipic 17 8
316 b000 0 0 2 &ipic 14 8
317 b000 0 0 3 &ipic 15 8
318 b000 0 0 4 &ipic 16 8
321 b800 0 0 1 &ipic 16 8
322 b800 0 0 2 &ipic 17 8
323 b800 0 0 3 &ipic 14 8
324 b800 0 0 4 &ipic 15 8
327 c000 0 0 1 &ipic 15 8
328 c000 0 0 2 &ipic 16 8
329 c000 0 0 3 &ipic 17 8
330 c000 0 0 4 &ipic 14 8>;
331 interrupt-parent = < &ipic >;
334 ranges = <02000000 0 90000000 90000000 0 10000000
335 42000000 0 80000000 80000000 0 10000000
336 01000000 0 00000000 d0000000 0 00100000>;
337 clock-frequency = <0>;
338 #interrupt-cells = <1>;
340 #address-cells = <3>;
341 reg = <e0008500 100>;
342 compatible = "fsl,mpc8349-pci";