2 * Toshiba rbtx4927 specific setup
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
20 * Copyright (C) 2000-2001 Toshiba Corporation
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/clk.h>
53 #include <linux/delay.h>
55 #include <asm/bootinfo.h>
57 #include <asm/processor.h>
58 #include <asm/reboot.h>
60 #include <asm/txx9tmr.h>
61 #include <asm/txx9/generic.h>
62 #include <asm/txx9/pci.h>
63 #include <asm/txx9/rbtx4927.h>
64 #include <asm/txx9/tx4938.h> /* for TX4937 */
65 #ifdef CONFIG_SERIAL_TXX9
66 #include <linux/serial_core.h>
69 /* These functions are used for rebooting or halting the machine*/
70 extern void toshiba_rbtx4927_restart(char *command);
71 extern void toshiba_rbtx4927_halt(void);
72 extern void toshiba_rbtx4927_power_off(void);
73 extern void toshiba_rbtx4927_irq_setup(void);
75 char *prom_getcmdline(void);
77 static int tx4927_ccfg_toeon = 1;
79 char *toshiba_name = "";
82 static void __init tx4927_pci_setup(void)
84 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
85 struct pci_controller *c = &txx9_primary_pcic;
87 register_pci_controller(c);
89 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
91 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
92 TXX9_PCI_OPT_CLK_66; /* already configured */
95 writeb(1, rbtx4927_pcireset_addr);
97 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
98 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
100 tx4927_pciclk66_setup();
102 /* clear PCIC reset */
103 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
104 writeb(0, rbtx4927_pcireset_addr);
107 tx4927_report_pciclk();
108 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
109 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
110 TXX9_PCI_OPT_CLK_AUTO &&
111 txx9_pci66_check(c, 0, 0)) {
113 writeb(1, rbtx4927_pcireset_addr);
115 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
116 tx4927_pciclk66_setup();
118 /* clear PCIC reset */
119 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
120 writeb(0, rbtx4927_pcireset_addr);
122 /* Reinitialize PCIC */
123 tx4927_report_pciclk();
124 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
128 static void __init tx4937_pci_setup(void)
130 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
131 struct pci_controller *c = &txx9_primary_pcic;
133 register_pci_controller(c);
135 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
137 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
138 TXX9_PCI_OPT_CLK_66; /* already configured */
141 writeb(1, rbtx4927_pcireset_addr);
143 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
144 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
146 tx4938_pciclk66_setup();
148 /* clear PCIC reset */
149 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
150 writeb(0, rbtx4927_pcireset_addr);
153 tx4938_report_pciclk();
154 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
155 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
156 TXX9_PCI_OPT_CLK_AUTO &&
157 txx9_pci66_check(c, 0, 0)) {
159 writeb(1, rbtx4927_pcireset_addr);
161 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
162 tx4938_pciclk66_setup();
164 /* clear PCIC reset */
165 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
166 writeb(0, rbtx4927_pcireset_addr);
168 /* Reinitialize PCIC */
169 tx4938_report_pciclk();
170 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
174 static int __init rbtx4927_arch_init(void)
176 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
182 arch_initcall(rbtx4927_arch_init);
183 #endif /* CONFIG_PCI */
185 static void __noreturn wait_forever(void)
192 void toshiba_rbtx4927_restart(char *command)
194 printk(KERN_NOTICE "System Rebooting...\n");
196 /* enable the s/w reset register */
197 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
199 /* wait for enable to be seen */
200 while ((readb(RBTX4927_SW_RESET_ENABLE) &
201 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
204 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
206 /* do something passive while waiting for reset */
212 void toshiba_rbtx4927_halt(void)
214 printk(KERN_NOTICE "System Halted\n");
220 void toshiba_rbtx4927_power_off(void)
222 toshiba_rbtx4927_halt();
226 void __init plat_mem_setup(void)
232 printk("CPU is %s\n", toshiba_name);
234 /* f/w leaves this on at startup */
235 clear_c0_status(ST0_ERL);
237 /* enable caches -- HCP5 does this, pmon does not */
238 cp0_config = read_c0_config();
239 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
240 write_c0_config(cp0_config);
242 ioport_resource.end = 0xffffffff;
243 iomem_resource.end = 0xffffffff;
245 _machine_restart = toshiba_rbtx4927_restart;
246 _machine_halt = toshiba_rbtx4927_halt;
247 pm_power_off = toshiba_rbtx4927_power_off;
249 for (i = 0; i < TX4927_NR_TMR; i++)
250 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
253 txx9_alloc_pci_controller(&txx9_primary_pcic,
254 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
255 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
257 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
261 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
264 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
265 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
266 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
267 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
268 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
269 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
272 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
273 * PCIDIVMODE[10] is 0.
274 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
275 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
276 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
277 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
278 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
279 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
282 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
283 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
284 TX4938_CCFG_PCIDIVMODE_MASK) {
285 case TX4938_CCFG_PCIDIVMODE_8:
286 case TX4938_CCFG_PCIDIVMODE_4:
287 txx9_cpu_clock = 266666666; /* 266MHz */
289 case TX4938_CCFG_PCIDIVMODE_9:
290 case TX4938_CCFG_PCIDIVMODE_4_5:
291 txx9_cpu_clock = 300000000; /* 300MHz */
294 txx9_cpu_clock = 333333333; /* 333MHz */
297 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
298 TX4927_CCFG_PCIDIVMODE_MASK) {
299 case TX4927_CCFG_PCIDIVMODE_2_5:
300 case TX4927_CCFG_PCIDIVMODE_5:
301 txx9_cpu_clock = 166666666; /* 166MHz */
304 txx9_cpu_clock = 200000000; /* 200MHz */
306 /* change default value to udelay/mdelay take reasonable time */
307 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
310 /* do reset on watchdog */
311 tx4927_ccfg_set(TX4927_CCFG_WR);
312 /* enable Timeout BusError */
313 if (tx4927_ccfg_toeon)
314 tx4927_ccfg_set(TX4927_CCFG_TOE);
316 #ifdef CONFIG_SERIAL_TXX9
318 extern int early_serial_txx9_setup(struct uart_port *port);
319 struct uart_port req;
320 for(i = 0; i < 2; i++) {
321 memset(&req, 0, sizeof(req));
323 req.iotype = UPIO_MEM;
324 req.membase = (char *)(0xff1ff300 + i * 0x100);
325 req.mapbase = 0xff1ff300 + i * 0x100;
326 req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
327 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
328 req.uartclk = 50000000;
329 early_serial_txx9_setup(&req);
332 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
333 argptr = prom_getcmdline();
334 if (strstr(argptr, "console=") == NULL) {
335 strcat(argptr, " console=ttyS0,38400");
340 #ifdef CONFIG_ROOT_NFS
341 argptr = prom_getcmdline();
342 if (strstr(argptr, "root=") == NULL) {
343 strcat(argptr, " root=/dev/nfs rw");
348 argptr = prom_getcmdline();
349 if (strstr(argptr, "ip=") == NULL) {
350 strcat(argptr, " ip=any");
355 void __init plat_time_init(void)
357 mips_hpt_frequency = txx9_cpu_clock / 2;
358 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
359 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
364 static int __init toshiba_rbtx4927_rtc_init(void)
366 static struct resource __initdata res = {
368 .end = 0x1c010000 + 0x800 - 1,
369 .flags = IORESOURCE_MEM,
371 struct platform_device *dev =
372 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
373 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
375 device_initcall(toshiba_rbtx4927_rtc_init);
377 static int __init rbtx4927_ne_init(void)
379 static struct resource __initdata res[] = {
381 .start = RBTX4927_RTL_8019_BASE,
382 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
383 .flags = IORESOURCE_IO,
385 .start = RBTX4927_RTL_8019_IRQ,
386 .flags = IORESOURCE_IRQ,
389 struct platform_device *dev =
390 platform_device_register_simple("ne", -1,
391 res, ARRAY_SIZE(res));
392 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
394 device_initcall(rbtx4927_ne_init);
396 /* Watchdog support */
398 static int __init txx9_wdt_init(unsigned long base)
400 struct resource res = {
402 .end = base + 0x100 - 1,
403 .flags = IORESOURCE_MEM,
405 struct platform_device *dev =
406 platform_device_register_simple("txx9wdt", -1, &res, 1);
407 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
410 static int __init rbtx4927_wdt_init(void)
412 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
414 device_initcall(rbtx4927_wdt_init);
416 /* Minimum CLK support */
418 struct clk *clk_get(struct device *dev, const char *id)
420 if (!strcmp(id, "imbus_clk"))
421 return (struct clk *)50000000;
422 return ERR_PTR(-ENOENT);
424 EXPORT_SYMBOL(clk_get);
426 int clk_enable(struct clk *clk)
430 EXPORT_SYMBOL(clk_enable);
432 void clk_disable(struct clk *clk)
435 EXPORT_SYMBOL(clk_disable);
437 unsigned long clk_get_rate(struct clk *clk)
439 return (unsigned long)clk;
441 EXPORT_SYMBOL(clk_get_rate);
443 void clk_put(struct clk *clk)
446 EXPORT_SYMBOL(clk_put);