2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
4 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 * Copyright (C) 1999 - 2001 Kanoj Sarcar
8 #include <linux/config.h>
9 #include <linux/init.h>
10 #include <linux/irq.h>
11 #include <linux/errno.h>
12 #include <linux/signal.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/timex.h>
19 #include <linux/slab.h>
20 #include <linux/random.h>
21 #include <linux/smp_lock.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/delay.h>
24 #include <linux/bitops.h>
26 #include <asm/bootinfo.h>
28 #include <asm/mipsregs.h>
29 #include <asm/system.h>
31 #include <asm/ptrace.h>
32 #include <asm/processor.h>
33 #include <asm/pci/bridge.h>
34 #include <asm/sn/addrs.h>
35 #include <asm/sn/agent.h>
36 #include <asm/sn/arch.h>
37 #include <asm/sn/hub.h>
38 #include <asm/sn/intr.h>
42 #define DBG(x...) printk(x)
48 * Linux has a controller-independent x86 interrupt architecture.
49 * every controller has a 'controller-template', that is used
50 * by the main code to do the right thing. Each driver-visible
51 * interrupt source is transparently wired to the apropriate
52 * controller. Thus drivers need not be aware of the
53 * interrupt-controller.
55 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
56 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
57 * (IO-APICs assumed to be messaging to Pentium local-APICs)
59 * the code is designed to be easily extended with new/different
60 * interrupt controllers, without having to do assembly magic.
63 extern asmlinkage void ip27_irq(void);
65 extern struct bridge_controller *irq_to_bridge[];
66 extern int irq_to_slot[];
69 * use these macros to get the encoded nasid and widget id
72 #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
73 #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
75 static inline int alloc_level(int cpu, int irq)
77 struct hub_data *hub = hub_data(cpu_to_node(cpu));
78 struct slice_data *si = cpu_data[cpu].data;
81 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
82 if (level >= LEVELS_PER_SLICE)
83 panic("Cpu %d flooded with devices\n", cpu);
85 __set_bit(level, hub->irq_alloc_mask);
86 si->level_to_irq[level] = irq;
91 static inline int find_level(cpuid_t *cpunum, int irq)
95 for (cpu = 0; cpu <= NR_CPUS; cpu++) {
96 struct slice_data *si = cpu_data[cpu].data;
101 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
102 if (si->level_to_irq[i] == irq) {
109 panic("Could not identify cpu/level for irq %d\n", irq);
115 static int ms1bit(unsigned long x)
119 s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
120 s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s;
121 s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s;
122 s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s;
123 s = 1; if (x >> 1 == 0) s = 0; b += s;
129 * This code is unnecessarily complex, because we do SA_INTERRUPT
130 * intr enabling. Basically, once we grab the set of intrs we need
131 * to service, we must mask _all_ these interrupts; firstly, to make
132 * sure the same intr does not intr again, causing recursion that
133 * can lead to stack overflow. Secondly, we can not just mask the
134 * one intr we are do_IRQing, because the non-masked intrs in the
135 * first set might intr again, causing multiple servicings of the
136 * same intr. This effect is mostly seen for intercpu intrs.
140 void ip27_do_irq_mask0(struct pt_regs *regs)
143 hubreg_t pend0, mask0;
144 cpuid_t cpu = smp_processor_id();
146 (cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B;
148 /* copied from Irix intpend0() */
149 pend0 = LOCAL_HUB_L(PI_INT_PEND0);
150 mask0 = LOCAL_HUB_L(pi_int_mask0);
152 pend0 &= mask0; /* Pick intrs we should look at */
156 swlevel = ms1bit(pend0);
158 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
159 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
160 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
161 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
162 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
163 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
164 smp_call_function_interrupt();
165 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
166 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
167 smp_call_function_interrupt();
171 /* "map" swlevel to irq */
172 struct slice_data *si = cpu_data[cpu].data;
174 irq = si->level_to_irq[swlevel];
178 LOCAL_HUB_L(PI_INT_PEND0);
181 void ip27_do_irq_mask1(struct pt_regs *regs)
184 hubreg_t pend1, mask1;
185 cpuid_t cpu = smp_processor_id();
186 int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B;
187 struct slice_data *si = cpu_data[cpu].data;
189 /* copied from Irix intpend0() */
190 pend1 = LOCAL_HUB_L(PI_INT_PEND1);
191 mask1 = LOCAL_HUB_L(pi_int_mask1);
193 pend1 &= mask1; /* Pick intrs we should look at */
197 swlevel = ms1bit(pend1);
198 /* "map" swlevel to irq */
199 irq = si->level_to_irq[swlevel];
200 LOCAL_HUB_CLR_INTR(swlevel);
203 LOCAL_HUB_L(PI_INT_PEND1);
206 void ip27_prof_timer(struct pt_regs *regs)
208 panic("CPU %d got a profiling interrupt", smp_processor_id());
211 void ip27_hub_error(struct pt_regs *regs)
213 panic("CPU %d got a hub error interrupt", smp_processor_id());
216 static int intr_connect_level(int cpu, int bit)
218 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
219 struct slice_data *si = cpu_data[cpu].data;
222 set_bit(bit, si->irq_enable_mask);
224 local_irq_save(flags);
225 if (!cputoslice(cpu)) {
226 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
227 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
229 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
230 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
232 local_irq_restore(flags);
237 static int intr_disconnect_level(int cpu, int bit)
239 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
240 struct slice_data *si = cpu_data[cpu].data;
242 clear_bit(bit, si->irq_enable_mask);
244 if (!cputoslice(cpu)) {
245 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
246 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
248 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
249 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
255 /* Startup one of the (PCI ...) IRQs routes over a bridge. */
256 static unsigned int startup_bridge_irq(unsigned int irq)
258 struct bridge_controller *bc;
264 pin = SLOT_FROM_PCI_IRQ(irq);
265 bc = IRQ_TO_BRIDGE(irq);
268 DBG("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin);
270 * "map" irq to a swlevel greater than 6 since the first 6 bits
271 * of INT_PEND0 are taken
273 swlevel = find_level(&cpu, irq);
274 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
275 bridge->b_int_enable |= (1 << pin);
276 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
279 * Enable sending of an interrupt clear packt to the hub on a high to
280 * low transition of the interrupt pin.
282 * IRIX sets additional bits in the address which are documented as
283 * reserved in the bridge docs.
285 bridge->b_int_mode |= (1UL << pin);
288 * We assume the bridge to have a 1:1 mapping between devices
289 * (slots) and intr pins.
291 device = bridge->b_int_device;
292 device &= ~(7 << (pin*3));
293 device |= (pin << (pin*3));
294 bridge->b_int_device = device;
296 bridge->b_wid_tflush;
298 return 0; /* Never anything pending. */
301 /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
302 static void shutdown_bridge_irq(unsigned int irq)
304 struct bridge_controller *bc = IRQ_TO_BRIDGE(irq);
305 struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu));
306 bridge_t *bridge = bc->base;
307 struct slice_data *si = cpu_data[bc->irq_cpu].data;
311 DBG("bridge_shutdown: irq 0x%x\n", irq);
312 pin = SLOT_FROM_PCI_IRQ(irq);
315 * map irq to a swlevel greater than 6 since the first 6 bits
316 * of INT_PEND0 are taken
318 swlevel = find_level(&cpu, irq);
319 intr_disconnect_level(cpu, swlevel);
321 __clear_bit(swlevel, hub->irq_alloc_mask);
322 si->level_to_irq[swlevel] = -1;
324 bridge->b_int_enable &= ~(1 << pin);
325 bridge->b_wid_tflush;
328 static inline void enable_bridge_irq(unsigned int irq)
333 swlevel = find_level(&cpu, irq); /* Criminal offence */
334 intr_connect_level(cpu, swlevel);
337 static inline void disable_bridge_irq(unsigned int irq)
342 swlevel = find_level(&cpu, irq); /* Criminal offence */
343 intr_disconnect_level(cpu, swlevel);
346 static void mask_and_ack_bridge_irq(unsigned int irq)
348 disable_bridge_irq(irq);
351 static void end_bridge_irq(unsigned int irq)
353 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
354 irq_desc[irq].action)
355 enable_bridge_irq(irq);
358 static struct hw_interrupt_type bridge_irq_type = {
359 .typename = "bridge",
360 .startup = startup_bridge_irq,
361 .shutdown = shutdown_bridge_irq,
362 .enable = enable_bridge_irq,
363 .disable = disable_bridge_irq,
364 .ack = mask_and_ack_bridge_irq,
365 .end = end_bridge_irq,
368 static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
370 static int allocate_irqno(void)
375 irq = find_first_zero_bit(irq_map, NR_IRQS);
380 if (test_and_set_bit(irq, irq_map))
386 void free_irqno(unsigned int irq)
388 clear_bit(irq, irq_map);
391 void __devinit register_bridge_irq(unsigned int irq)
393 irq_desc[irq].status = IRQ_DISABLED;
394 irq_desc[irq].action = 0;
395 irq_desc[irq].depth = 1;
396 irq_desc[irq].handler = &bridge_irq_type;
399 int __devinit request_bridge_irq(struct bridge_controller *bc)
401 int irq = allocate_irqno();
409 * "map" irq to a swlevel greater than 6 since the first 6 bits
410 * of INT_PEND0 are taken
413 swlevel = alloc_level(cpu, irq);
414 if (unlikely(swlevel < 0)) {
420 /* Make sure it's not already pending when we connect it. */
421 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
422 REMOTE_HUB_CLR_INTR(nasid, swlevel);
424 intr_connect_level(cpu, swlevel);
426 register_bridge_irq(irq);
431 void __init arch_init_irq(void)
433 set_except_vector(0, ip27_irq);
436 void install_ipi(void)
438 int slice = LOCAL_HUB_L(PI_CPU_NUM);
439 int cpu = smp_processor_id();
440 struct slice_data *si = cpu_data[cpu].data;
441 struct hub_data *hub = hub_data(cpu_to_node(cpu));
444 resched = CPU_RESCHED_A_IRQ + slice;
445 __set_bit(resched, hub->irq_alloc_mask);
446 __set_bit(resched, si->irq_enable_mask);
447 LOCAL_HUB_CLR_INTR(resched);
449 call = CPU_CALL_A_IRQ + slice;
450 __set_bit(call, hub->irq_alloc_mask);
451 __set_bit(call, si->irq_enable_mask);
452 LOCAL_HUB_CLR_INTR(call);
455 LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
456 LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
458 LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
459 LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);