2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 * http://www.algor.co.uk
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * A complete emulator for MIPS coprocessor 1 instructions. This is
25 * required for #float(switch) or #float(trap), where it catches all
26 * COP1 instructions via the "CoProcessor Unusable" exception.
28 * More surprisingly it is also required for #float(ieee), to help out
29 * the hardware fpu at the boundaries of the IEEE-754 representation
30 * (denormalised values, infinities, underflow, etc). It is made
31 * quite nasty because emulation of some non-COP1 instructions is
32 * required, e.g. in branch delay slots.
34 * Note if you know that you won't have an fpu, then you'll get much
35 * better performance by compiling with -msoft-float!
37 #include <linux/sched.h>
38 #include <linux/debugfs.h>
41 #include <asm/bootinfo.h>
42 #include <asm/processor.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/mipsregs.h>
46 #include <asm/fpu_emulator.h>
47 #include <asm/uaccess.h>
48 #include <asm/branch.h>
53 /* Strap kernel emulator for full MIPS IV emulation */
60 /* Function which emulates a floating point instruction. */
62 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
65 #if __mips >= 4 && __mips != 32
66 static int fpux_emu(struct pt_regs *,
67 struct mips_fpu_struct *, mips_instruction);
70 /* Further private data for which no space exists in mips_fpu_struct */
72 struct mips_fpu_emulator_stats fpuemustats;
74 /* Control registers */
76 #define FPCREG_RID 0 /* $0 = revision id */
77 #define FPCREG_CSR 31 /* $31 = csr */
79 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
80 static const unsigned char ieee_rm[4] = {
81 [FPU_CSR_RN] = IEEE754_RN,
82 [FPU_CSR_RZ] = IEEE754_RZ,
83 [FPU_CSR_RU] = IEEE754_RU,
84 [FPU_CSR_RD] = IEEE754_RD,
86 /* Convert IEEE library modes to Mips rounding mode (0..3). */
87 static const unsigned char mips_rm[4] = {
88 [IEEE754_RN] = FPU_CSR_RN,
89 [IEEE754_RZ] = FPU_CSR_RZ,
90 [IEEE754_RD] = FPU_CSR_RD,
91 [IEEE754_RU] = FPU_CSR_RU,
95 /* convert condition code register number to csr bit */
96 static const unsigned int fpucondbit[8] = {
110 * Redundant with logic already in kernel/branch.c,
111 * embedded in compute_return_epc. At some point,
112 * a single subroutine should be used across both
115 static int isBranchInstr(mips_instruction * i)
117 switch (MIPSInst_OPCODE(*i)) {
119 switch (MIPSInst_FUNC(*i)) {
127 switch (MIPSInst_RT(*i)) {
157 if (MIPSInst_RS(*i) == bc_op)
166 * In the Linux kernel, we support selection of FPR format on the
167 * basis of the Status.FR bit. This does imply that, if a full 32
168 * FPRs are desired, there needs to be a flip-flop that can be written
169 * to one at that bit position. In any case, O32 MIPS ABI uses
170 * only the even FPRs (Status.FR = 0).
173 #define CP0_STATUS_FR_SUPPORT
175 #ifdef CP0_STATUS_FR_SUPPORT
176 #define FR_BIT ST0_FR
181 #define SIFROMREG(si,x) ((si) = \
182 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
184 (int)(ctx->fpr[x & ~1] >> 32 ))
185 #define SITOREG(si,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
186 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
187 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
188 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
190 #define DIFROMREG(di,x) ((di) = \
191 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)])
192 #define DITOREG(di,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
195 #define SPFROMREG(sp,x) SIFROMREG((sp).bits,x)
196 #define SPTOREG(sp,x) SITOREG((sp).bits,x)
197 #define DPFROMREG(dp,x) DIFROMREG((dp).bits,x)
198 #define DPTOREG(dp,x) DITOREG((dp).bits,x)
201 * Emulate the single floating point instruction pointed at by EPC.
202 * Two instructions if the instruction is in a branch delay slot.
205 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
208 void * emulpc, *contpc;
211 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
212 fpuemustats.errors++;
216 /* XXX NEC Vr54xx bug workaround */
217 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
218 xcp->cp0_cause &= ~CAUSEF_BD;
220 if (xcp->cp0_cause & CAUSEF_BD) {
222 * The instruction to be emulated is in a branch delay slot
223 * which means that we have to emulate the branch instruction
224 * BEFORE we do the cop1 instruction.
226 * This branch could be a COP1 branch, but in that case we
227 * would have had a trap for that instruction, and would not
228 * come through this route.
230 * Linux MIPS branch emulator operates on context, updating the
233 emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
235 if (__compute_return_epc(xcp)) {
237 printk("failed to emulate branch at %p\n",
238 (void *) (xcp->cp0_epc));
242 if (get_user(ir, (mips_instruction __user *) emulpc)) {
243 fpuemustats.errors++;
246 /* __compute_return_epc() will have updated cp0_epc */
247 contpc = (void *) xcp->cp0_epc;
248 /* In order not to confuse ptrace() et al, tweak context */
249 xcp->cp0_epc = (unsigned long) emulpc - 4;
251 emulpc = (void *) xcp->cp0_epc;
252 contpc = (void *) (xcp->cp0_epc + 4);
256 fpuemustats.emulated++;
257 switch (MIPSInst_OPCODE(ir)) {
259 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
264 if (get_user(val, va)) {
265 fpuemustats.errors++;
268 DITOREG(val, MIPSInst_RT(ir));
273 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
277 fpuemustats.stores++;
278 DIFROMREG(val, MIPSInst_RT(ir));
279 if (put_user(val, va)) {
280 fpuemustats.errors++;
287 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
292 if (get_user(val, va)) {
293 fpuemustats.errors++;
296 SITOREG(val, MIPSInst_RT(ir));
301 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
305 fpuemustats.stores++;
306 SIFROMREG(val, MIPSInst_RT(ir));
307 if (put_user(val, va)) {
308 fpuemustats.errors++;
315 switch (MIPSInst_RS(ir)) {
317 #if defined(__mips64)
319 /* copregister fs -> gpr[rt] */
320 if (MIPSInst_RT(ir) != 0) {
321 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
327 /* copregister fs <- rt */
328 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
333 /* copregister rd -> gpr[rt] */
334 if (MIPSInst_RT(ir) != 0) {
335 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
341 /* copregister rd <- rt */
342 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
346 /* cop control register rd -> gpr[rt] */
349 if (ir == CP1UNDEF) {
350 return do_dsemulret(xcp);
352 if (MIPSInst_RD(ir) == FPCREG_CSR) {
354 value = (value & ~0x3) | mips_rm[value & 0x3];
356 printk("%p gpr[%d]<-csr=%08x\n",
357 (void *) (xcp->cp0_epc),
358 MIPSInst_RT(ir), value);
361 else if (MIPSInst_RD(ir) == FPCREG_RID)
366 xcp->regs[MIPSInst_RT(ir)] = value;
371 /* copregister rd <- rt */
374 if (MIPSInst_RT(ir) == 0)
377 value = xcp->regs[MIPSInst_RT(ir)];
379 /* we only have one writable control reg
381 if (MIPSInst_RD(ir) == FPCREG_CSR) {
383 printk("%p gpr[%d]->csr=%08x\n",
384 (void *) (xcp->cp0_epc),
385 MIPSInst_RT(ir), value);
387 value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
388 ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
389 /* convert to ieee library modes */
390 ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
392 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
401 if (xcp->cp0_cause & CAUSEF_BD)
405 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
407 cond = ctx->fcr31 & FPU_CSR_COND;
409 switch (MIPSInst_RT(ir) & 3) {
420 /* thats an illegal instruction */
424 xcp->cp0_cause |= CAUSEF_BD;
426 /* branch taken: emulate dslot
432 (MIPSInst_SIMM(ir) << 2));
435 (mips_instruction __user *) xcp->cp0_epc)) {
436 fpuemustats.errors++;
440 switch (MIPSInst_OPCODE(ir)) {
443 #if (__mips >= 2 || defined(__mips64))
448 #if __mips >= 4 && __mips != 32
451 /* its one of ours */
455 if (MIPSInst_FUNC(ir) == movc_op)
462 * Single step the non-cp1
463 * instruction in the dslot
465 return mips_dsemul(xcp, ir, (unsigned long) contpc);
468 /* branch not taken */
471 * branch likely nullifies
477 * else continue & execute
478 * dslot as normal insn
486 if (!(MIPSInst_RS(ir) & 0x10))
491 /* a real fpu computation instruction */
492 if ((sig = fpu_emu(xcp, ctx, ir)))
498 #if __mips >= 4 && __mips != 32
502 if ((sig = fpux_emu(xcp, ctx, ir)))
510 if (MIPSInst_FUNC(ir) != movc_op)
512 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
513 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
514 xcp->regs[MIPSInst_RD(ir)] =
515 xcp->regs[MIPSInst_RS(ir)];
524 xcp->cp0_epc = (unsigned long) contpc;
525 xcp->cp0_cause &= ~CAUSEF_BD;
531 * Conversion table from MIPS compare ops 48-63
532 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
534 static const unsigned char cmptab[8] = {
535 0, /* cmp_0 (sig) cmp_sf */
536 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
537 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
538 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
539 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
540 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
541 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
542 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
546 #if __mips >= 4 && __mips != 32
549 * Additional MIPS4 instructions
552 #define DEF3OP(name, p, f1, f2, f3) \
553 static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
556 struct _ieee754_csr ieee754_csr_save; \
558 ieee754_csr_save = ieee754_csr; \
560 ieee754_csr_save.cx |= ieee754_csr.cx; \
561 ieee754_csr_save.sx |= ieee754_csr.sx; \
563 ieee754_csr.cx |= ieee754_csr_save.cx; \
564 ieee754_csr.sx |= ieee754_csr_save.sx; \
568 static ieee754dp fpemu_dp_recip(ieee754dp d)
570 return ieee754dp_div(ieee754dp_one(0), d);
573 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
575 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
578 static ieee754sp fpemu_sp_recip(ieee754sp s)
580 return ieee754sp_div(ieee754sp_one(0), s);
583 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
585 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
588 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,);
589 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,);
590 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
591 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
592 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,);
593 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,);
594 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
595 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
597 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
600 unsigned rcsr = 0; /* resulting csr */
602 fpuemustats.cp1xops++;
604 switch (MIPSInst_FMA_FFMT(ir)) {
607 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
608 ieee754sp fd, fr, fs, ft;
612 switch (MIPSInst_FUNC(ir)) {
614 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
615 xcp->regs[MIPSInst_FT(ir)]);
618 if (get_user(val, va)) {
619 fpuemustats.errors++;
622 SITOREG(val, MIPSInst_FD(ir));
626 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
627 xcp->regs[MIPSInst_FT(ir)]);
629 fpuemustats.stores++;
631 SIFROMREG(val, MIPSInst_FS(ir));
632 if (put_user(val, va)) {
633 fpuemustats.errors++;
639 handler = fpemu_sp_madd;
642 handler = fpemu_sp_msub;
645 handler = fpemu_sp_nmadd;
648 handler = fpemu_sp_nmsub;
652 SPFROMREG(fr, MIPSInst_FR(ir));
653 SPFROMREG(fs, MIPSInst_FS(ir));
654 SPFROMREG(ft, MIPSInst_FT(ir));
655 fd = (*handler) (fr, fs, ft);
656 SPTOREG(fd, MIPSInst_FD(ir));
659 if (ieee754_cxtest(IEEE754_INEXACT))
660 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
661 if (ieee754_cxtest(IEEE754_UNDERFLOW))
662 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
663 if (ieee754_cxtest(IEEE754_OVERFLOW))
664 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
665 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
666 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
668 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
669 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
670 /*printk ("SIGFPE: fpu csr = %08x\n",
684 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
685 ieee754dp fd, fr, fs, ft;
689 switch (MIPSInst_FUNC(ir)) {
691 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
692 xcp->regs[MIPSInst_FT(ir)]);
695 if (get_user(val, va)) {
696 fpuemustats.errors++;
699 DITOREG(val, MIPSInst_FD(ir));
703 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
704 xcp->regs[MIPSInst_FT(ir)]);
706 fpuemustats.stores++;
707 DIFROMREG(val, MIPSInst_FS(ir));
708 if (put_user(val, va)) {
709 fpuemustats.errors++;
715 handler = fpemu_dp_madd;
718 handler = fpemu_dp_msub;
721 handler = fpemu_dp_nmadd;
724 handler = fpemu_dp_nmsub;
728 DPFROMREG(fr, MIPSInst_FR(ir));
729 DPFROMREG(fs, MIPSInst_FS(ir));
730 DPFROMREG(ft, MIPSInst_FT(ir));
731 fd = (*handler) (fr, fs, ft);
732 DPTOREG(fd, MIPSInst_FD(ir));
742 if (MIPSInst_FUNC(ir) != pfetch_op) {
745 /* ignore prefx operation */
759 * Emulate a single COP1 arithmetic instruction.
761 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
764 int rfmt; /* resulting format */
765 unsigned rcsr = 0; /* resulting csr */
774 } rv; /* resulting value */
776 fpuemustats.cp1ops++;
777 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
780 ieee754sp(*b) (ieee754sp, ieee754sp);
781 ieee754sp(*u) (ieee754sp);
784 switch (MIPSInst_FUNC(ir)) {
787 handler.b = ieee754sp_add;
790 handler.b = ieee754sp_sub;
793 handler.b = ieee754sp_mul;
796 handler.b = ieee754sp_div;
800 #if __mips >= 2 || defined(__mips64)
802 handler.u = ieee754sp_sqrt;
805 #if __mips >= 4 && __mips != 32
807 handler.u = fpemu_sp_rsqrt;
810 handler.u = fpemu_sp_recip;
815 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
816 if (((ctx->fcr31 & cond) != 0) !=
817 ((MIPSInst_FT(ir) & 1) != 0))
819 SPFROMREG(rv.s, MIPSInst_FS(ir));
822 if (xcp->regs[MIPSInst_FT(ir)] != 0)
824 SPFROMREG(rv.s, MIPSInst_FS(ir));
827 if (xcp->regs[MIPSInst_FT(ir)] == 0)
829 SPFROMREG(rv.s, MIPSInst_FS(ir));
833 handler.u = ieee754sp_abs;
836 handler.u = ieee754sp_neg;
840 SPFROMREG(rv.s, MIPSInst_FS(ir));
843 /* binary op on handler */
848 SPFROMREG(fs, MIPSInst_FS(ir));
849 SPFROMREG(ft, MIPSInst_FT(ir));
851 rv.s = (*handler.b) (fs, ft);
858 SPFROMREG(fs, MIPSInst_FS(ir));
859 rv.s = (*handler.u) (fs);
863 if (ieee754_cxtest(IEEE754_INEXACT))
864 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
865 if (ieee754_cxtest(IEEE754_UNDERFLOW))
866 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
867 if (ieee754_cxtest(IEEE754_OVERFLOW))
868 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
869 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
870 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
871 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
872 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
877 return SIGILL; /* not defined */
881 SPFROMREG(fs, MIPSInst_FS(ir));
882 rv.d = ieee754dp_fsp(fs);
889 SPFROMREG(fs, MIPSInst_FS(ir));
890 rv.w = ieee754sp_tint(fs);
895 #if __mips >= 2 || defined(__mips64)
900 unsigned int oldrm = ieee754_csr.rm;
903 SPFROMREG(fs, MIPSInst_FS(ir));
904 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
905 rv.w = ieee754sp_tint(fs);
906 ieee754_csr.rm = oldrm;
910 #endif /* __mips >= 2 */
912 #if defined(__mips64)
916 SPFROMREG(fs, MIPSInst_FS(ir));
917 rv.l = ieee754sp_tlong(fs);
926 unsigned int oldrm = ieee754_csr.rm;
929 SPFROMREG(fs, MIPSInst_FS(ir));
930 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
931 rv.l = ieee754sp_tlong(fs);
932 ieee754_csr.rm = oldrm;
936 #endif /* defined(__mips64) */
939 if (MIPSInst_FUNC(ir) >= fcmp_op) {
940 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
943 SPFROMREG(fs, MIPSInst_FS(ir));
944 SPFROMREG(ft, MIPSInst_FT(ir));
945 rv.w = ieee754sp_cmp(fs, ft,
946 cmptab[cmpop & 0x7], cmpop & 0x8);
948 if ((cmpop & 0x8) && ieee754_cxtest
949 (IEEE754_INVALID_OPERATION))
950 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
965 ieee754dp(*b) (ieee754dp, ieee754dp);
966 ieee754dp(*u) (ieee754dp);
969 switch (MIPSInst_FUNC(ir)) {
972 handler.b = ieee754dp_add;
975 handler.b = ieee754dp_sub;
978 handler.b = ieee754dp_mul;
981 handler.b = ieee754dp_div;
985 #if __mips >= 2 || defined(__mips64)
987 handler.u = ieee754dp_sqrt;
990 #if __mips >= 4 && __mips != 32
992 handler.u = fpemu_dp_rsqrt;
995 handler.u = fpemu_dp_recip;
1000 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1001 if (((ctx->fcr31 & cond) != 0) !=
1002 ((MIPSInst_FT(ir) & 1) != 0))
1004 DPFROMREG(rv.d, MIPSInst_FS(ir));
1007 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1009 DPFROMREG(rv.d, MIPSInst_FS(ir));
1012 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1014 DPFROMREG(rv.d, MIPSInst_FS(ir));
1018 handler.u = ieee754dp_abs;
1022 handler.u = ieee754dp_neg;
1027 DPFROMREG(rv.d, MIPSInst_FS(ir));
1030 /* binary op on handler */
1034 DPFROMREG(fs, MIPSInst_FS(ir));
1035 DPFROMREG(ft, MIPSInst_FT(ir));
1037 rv.d = (*handler.b) (fs, ft);
1043 DPFROMREG(fs, MIPSInst_FS(ir));
1044 rv.d = (*handler.u) (fs);
1048 /* unary conv ops */
1052 DPFROMREG(fs, MIPSInst_FS(ir));
1053 rv.s = ieee754sp_fdp(fs);
1058 return SIGILL; /* not defined */
1063 DPFROMREG(fs, MIPSInst_FS(ir));
1064 rv.w = ieee754dp_tint(fs); /* wrong */
1069 #if __mips >= 2 || defined(__mips64)
1074 unsigned int oldrm = ieee754_csr.rm;
1077 DPFROMREG(fs, MIPSInst_FS(ir));
1078 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1079 rv.w = ieee754dp_tint(fs);
1080 ieee754_csr.rm = oldrm;
1086 #if defined(__mips64)
1090 DPFROMREG(fs, MIPSInst_FS(ir));
1091 rv.l = ieee754dp_tlong(fs);
1100 unsigned int oldrm = ieee754_csr.rm;
1103 DPFROMREG(fs, MIPSInst_FS(ir));
1104 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1105 rv.l = ieee754dp_tlong(fs);
1106 ieee754_csr.rm = oldrm;
1110 #endif /* __mips >= 3 */
1113 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1114 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1117 DPFROMREG(fs, MIPSInst_FS(ir));
1118 DPFROMREG(ft, MIPSInst_FT(ir));
1119 rv.w = ieee754dp_cmp(fs, ft,
1120 cmptab[cmpop & 0x7], cmpop & 0x8);
1125 (IEEE754_INVALID_OPERATION))
1126 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1142 switch (MIPSInst_FUNC(ir)) {
1144 /* convert word to single precision real */
1145 SPFROMREG(fs, MIPSInst_FS(ir));
1146 rv.s = ieee754sp_fint(fs.bits);
1150 /* convert word to double precision real */
1151 SPFROMREG(fs, MIPSInst_FS(ir));
1152 rv.d = ieee754dp_fint(fs.bits);
1161 #if defined(__mips64)
1163 switch (MIPSInst_FUNC(ir)) {
1165 /* convert long to single precision real */
1166 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1170 /* convert long to double precision real */
1171 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1186 * Update the fpu CSR register for this operation.
1187 * If an exception is required, generate a tidy SIGFPE exception,
1188 * without updating the result register.
1189 * Note: cause exception bits do not accumulate, they are rewritten
1190 * for each op; only the flag/sticky bits accumulate.
1192 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1193 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1194 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1199 * Now we can safely write the result back to the register file.
1204 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1206 cond = FPU_CSR_COND;
1211 ctx->fcr31 &= ~cond;
1215 DPTOREG(rv.d, MIPSInst_FD(ir));
1218 SPTOREG(rv.s, MIPSInst_FD(ir));
1221 SITOREG(rv.w, MIPSInst_FD(ir));
1223 #if defined(__mips64)
1225 DITOREG(rv.l, MIPSInst_FD(ir));
1235 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1238 unsigned long oldepc, prevepc;
1239 mips_instruction insn;
1242 oldepc = xcp->cp0_epc;
1244 prevepc = xcp->cp0_epc;
1246 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1247 fpuemustats.errors++;
1251 xcp->cp0_epc += 4; /* skip nops */
1254 * The 'ieee754_csr' is an alias of
1255 * ctx->fcr31. No need to copy ctx->fcr31 to
1256 * ieee754_csr. But ieee754_csr.rm is ieee
1257 * library modes. (not mips rounding mode)
1259 /* convert to ieee library modes */
1260 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1261 sig = cop1Emulate(xcp, ctx);
1262 /* revert to mips rounding mode */
1263 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1272 } while (xcp->cp0_epc > prevepc);
1274 /* SIGILL indicates a non-fpu instruction */
1275 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1276 /* but if epc has advanced, then ignore it */
1282 #ifdef CONFIG_DEBUG_FS
1283 extern struct dentry *mips_debugfs_dir;
1284 static int __init debugfs_fpuemu(void)
1286 struct dentry *d, *dir;
1291 } vars[] __initdata = {
1292 { "emulated", &fpuemustats.emulated },
1293 { "loads", &fpuemustats.loads },
1294 { "stores", &fpuemustats.stores },
1295 { "cp1ops", &fpuemustats.cp1ops },
1296 { "cp1xops", &fpuemustats.cp1xops },
1297 { "errors", &fpuemustats.errors },
1300 if (!mips_debugfs_dir)
1302 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1304 return PTR_ERR(dir);
1305 for (i = 0; i < ARRAY_SIZE(vars); i++) {
1306 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
1312 __initcall(debugfs_fpuemu);