2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
45 extern asmlinkage void handle_int(void);
46 extern asmlinkage void handle_tlbm(void);
47 extern asmlinkage void handle_tlbl(void);
48 extern asmlinkage void handle_tlbs(void);
49 extern asmlinkage void handle_adel(void);
50 extern asmlinkage void handle_ades(void);
51 extern asmlinkage void handle_ibe(void);
52 extern asmlinkage void handle_dbe(void);
53 extern asmlinkage void handle_sys(void);
54 extern asmlinkage void handle_bp(void);
55 extern asmlinkage void handle_ri(void);
56 extern asmlinkage void handle_cpu(void);
57 extern asmlinkage void handle_ov(void);
58 extern asmlinkage void handle_tr(void);
59 extern asmlinkage void handle_fpe(void);
60 extern asmlinkage void handle_mdmx(void);
61 extern asmlinkage void handle_watch(void);
62 extern asmlinkage void handle_mt(void);
63 extern asmlinkage void handle_dsp(void);
64 extern asmlinkage void handle_mcheck(void);
65 extern asmlinkage void handle_reserved(void);
67 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
68 struct mips_fpu_struct *ctx);
70 void (*board_be_init)(void);
71 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
72 void (*board_nmi_handler_setup)(void);
73 void (*board_ejtag_handler_setup)(void);
74 void (*board_bind_eic_interrupt)(int irq, int regset);
77 * These constant is for searching for possible module text segments.
78 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
80 #define MODULE_RANGE (8*1024*1024)
82 static void show_trace(unsigned long *stack)
84 const int field = 2 * sizeof(unsigned long);
87 printk("Call Trace:");
88 #ifdef CONFIG_KALLSYMS
91 while (!kstack_end(stack)) {
93 if (__kernel_text_address(addr)) {
94 printk(" [<%0*lx>] ", field, addr);
95 print_symbol("%s\n", addr);
101 #ifdef CONFIG_KALLSYMS
102 static int raw_show_trace;
103 static int __init set_raw_show_trace(char *str)
108 __setup("raw_show_trace", set_raw_show_trace);
110 extern unsigned long unwind_stack(struct task_struct *task,
111 unsigned long **sp, unsigned long pc);
112 static void show_frametrace(struct task_struct *task, struct pt_regs *regs)
114 const int field = 2 * sizeof(unsigned long);
115 unsigned long *stack = (long *)regs->regs[29];
116 unsigned long pc = regs->cp0_epc;
119 if (raw_show_trace || !__kernel_text_address(pc)) {
123 printk("Call Trace:\n");
124 while (__kernel_text_address(pc)) {
125 printk(" [<%0*lx>] ", field, pc);
126 print_symbol("%s\n", pc);
127 pc = unwind_stack(task, &stack, pc);
129 pc = regs->regs[31]; /* leaf? */
135 #define show_frametrace(task, r) show_trace((long *)(r)->regs[29]);
139 * This routine abuses get_user()/put_user() to reference pointers
140 * with at least a bit of error checking ...
142 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
144 const int field = 2 * sizeof(unsigned long);
147 unsigned long *sp = (unsigned long *)regs->regs[29];
151 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
152 if (i && ((i % (64 / field)) == 0))
159 if (__get_user(stackdata, sp++)) {
160 printk(" (Bad stack address)");
164 printk(" %0*lx", field, stackdata);
168 show_frametrace(task, regs);
171 static noinline void prepare_frametrace(struct pt_regs *regs)
173 __asm__ __volatile__(
184 : "=m" (regs->cp0_epc),
185 "=m" (regs->regs[29]), "=m" (regs->regs[31])
189 void show_stack(struct task_struct *task, unsigned long *sp)
193 regs.regs[29] = (unsigned long)sp;
197 if (task && task != current) {
198 regs.regs[29] = task->thread.reg29;
200 regs.cp0_epc = task->thread.reg31;
202 prepare_frametrace(®s);
205 show_stacktrace(task, ®s);
209 * The architecture-independent dump_stack generator
211 void dump_stack(void)
215 #ifdef CONFIG_KALLSYMS
216 if (!raw_show_trace) {
218 prepare_frametrace(®s);
219 show_frametrace(current, ®s);
226 EXPORT_SYMBOL(dump_stack);
228 void show_code(unsigned int *pc)
234 for(i = -3 ; i < 6 ; i++) {
236 if (__get_user(insn, pc + i)) {
237 printk(" (Bad address in epc)\n");
240 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
244 void show_regs(struct pt_regs *regs)
246 const int field = 2 * sizeof(unsigned long);
247 unsigned int cause = regs->cp0_cause;
250 printk("Cpu %d\n", smp_processor_id());
253 * Saved main processor registers
255 for (i = 0; i < 32; ) {
259 printk(" %0*lx", field, 0UL);
260 else if (i == 26 || i == 27)
261 printk(" %*s", field, "");
263 printk(" %0*lx", field, regs->regs[i]);
270 printk("Hi : %0*lx\n", field, regs->hi);
271 printk("Lo : %0*lx\n", field, regs->lo);
274 * Saved cp0 registers
276 printk("epc : %0*lx ", field, regs->cp0_epc);
277 print_symbol("%s ", regs->cp0_epc);
278 printk(" %s\n", print_tainted());
279 printk("ra : %0*lx ", field, regs->regs[31]);
280 print_symbol("%s\n", regs->regs[31]);
282 printk("Status: %08x ", (uint32_t) regs->cp0_status);
284 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
285 if (regs->cp0_status & ST0_KUO)
287 if (regs->cp0_status & ST0_IEO)
289 if (regs->cp0_status & ST0_KUP)
291 if (regs->cp0_status & ST0_IEP)
293 if (regs->cp0_status & ST0_KUC)
295 if (regs->cp0_status & ST0_IEC)
298 if (regs->cp0_status & ST0_KX)
300 if (regs->cp0_status & ST0_SX)
302 if (regs->cp0_status & ST0_UX)
304 switch (regs->cp0_status & ST0_KSU) {
309 printk("SUPERVISOR ");
318 if (regs->cp0_status & ST0_ERL)
320 if (regs->cp0_status & ST0_EXL)
322 if (regs->cp0_status & ST0_IE)
327 printk("Cause : %08x\n", cause);
329 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
330 if (1 <= cause && cause <= 5)
331 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
333 printk("PrId : %08x\n", read_c0_prid());
336 void show_registers(struct pt_regs *regs)
340 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
341 current->comm, current->pid, current_thread_info(), current);
342 show_stacktrace(current, regs);
343 show_code((unsigned int *) regs->cp0_epc);
347 static DEFINE_SPINLOCK(die_lock);
349 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
351 static int die_counter;
352 #ifdef CONFIG_MIPS_MT_SMTC
353 unsigned long dvpret = dvpe();
354 #endif /* CONFIG_MIPS_MT_SMTC */
357 spin_lock_irq(&die_lock);
359 #ifdef CONFIG_MIPS_MT_SMTC
360 mips_mt_regdump(dvpret);
361 #endif /* CONFIG_MIPS_MT_SMTC */
362 printk("%s[#%d]:\n", str, ++die_counter);
363 show_registers(regs);
364 spin_unlock_irq(&die_lock);
367 panic("Fatal exception in interrupt");
370 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
372 panic("Fatal exception");
378 extern const struct exception_table_entry __start___dbe_table[];
379 extern const struct exception_table_entry __stop___dbe_table[];
381 void __declare_dbe_table(void)
383 __asm__ __volatile__(
384 ".section\t__dbe_table,\"a\"\n\t"
389 /* Given an address, look for it in the exception tables. */
390 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
392 const struct exception_table_entry *e;
394 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
396 e = search_module_dbetables(addr);
400 asmlinkage void do_be(struct pt_regs *regs)
402 const int field = 2 * sizeof(unsigned long);
403 const struct exception_table_entry *fixup = NULL;
404 int data = regs->cp0_cause & 4;
405 int action = MIPS_BE_FATAL;
407 /* XXX For now. Fixme, this searches the wrong table ... */
408 if (data && !user_mode(regs))
409 fixup = search_dbe_tables(exception_epc(regs));
412 action = MIPS_BE_FIXUP;
414 if (board_be_handler)
415 action = board_be_handler(regs, fixup != 0);
418 case MIPS_BE_DISCARD:
422 regs->cp0_epc = fixup->nextinsn;
431 * Assume it would be too dangerous to continue ...
433 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
434 data ? "Data" : "Instruction",
435 field, regs->cp0_epc, field, regs->regs[31]);
436 die_if_kernel("Oops", regs);
437 force_sig(SIGBUS, current);
440 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
442 unsigned int __user *epc;
444 epc = (unsigned int __user *) regs->cp0_epc +
445 ((regs->cp0_cause & CAUSEF_BD) != 0);
446 if (!get_user(*opcode, epc))
449 force_sig(SIGSEGV, current);
457 #define OPCODE 0xfc000000
458 #define BASE 0x03e00000
459 #define RT 0x001f0000
460 #define OFFSET 0x0000ffff
461 #define LL 0xc0000000
462 #define SC 0xe0000000
463 #define SPEC3 0x7c000000
464 #define RD 0x0000f800
465 #define FUNC 0x0000003f
466 #define RDHWR 0x0000003b
469 * The ll_bit is cleared by r*_switch.S
472 unsigned long ll_bit;
474 static struct task_struct *ll_task = NULL;
476 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
478 unsigned long value, __user *vaddr;
483 * analyse the ll instruction that just caused a ri exception
484 * and put the referenced address to addr.
487 /* sign extend offset */
488 offset = opcode & OFFSET;
492 vaddr = (unsigned long __user *)
493 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
495 if ((unsigned long)vaddr & 3) {
499 if (get_user(value, vaddr)) {
506 if (ll_task == NULL || ll_task == current) {
515 compute_return_epc(regs);
517 regs->regs[(opcode & RT) >> 16] = value;
522 force_sig(signal, current);
525 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
527 unsigned long __user *vaddr;
533 * analyse the sc instruction that just caused a ri exception
534 * and put the referenced address to addr.
537 /* sign extend offset */
538 offset = opcode & OFFSET;
542 vaddr = (unsigned long __user *)
543 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
544 reg = (opcode & RT) >> 16;
546 if ((unsigned long)vaddr & 3) {
553 if (ll_bit == 0 || ll_task != current) {
554 compute_return_epc(regs);
562 if (put_user(regs->regs[reg], vaddr)) {
567 compute_return_epc(regs);
573 force_sig(signal, current);
577 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
578 * opcodes are supposed to result in coprocessor unusable exceptions if
579 * executed on ll/sc-less processors. That's the theory. In practice a
580 * few processors such as NEC's VR4100 throw reserved instruction exceptions
581 * instead, so we're doing the emulation thing in both exception handlers.
583 static inline int simulate_llsc(struct pt_regs *regs)
587 if (unlikely(get_insn_opcode(regs, &opcode)))
590 if ((opcode & OPCODE) == LL) {
591 simulate_ll(regs, opcode);
594 if ((opcode & OPCODE) == SC) {
595 simulate_sc(regs, opcode);
599 return -EFAULT; /* Strange things going on ... */
603 * Simulate trapping 'rdhwr' instructions to provide user accessible
604 * registers not implemented in hardware. The only current use of this
605 * is the thread area pointer.
607 static inline int simulate_rdhwr(struct pt_regs *regs)
609 struct thread_info *ti = task_thread_info(current);
612 if (unlikely(get_insn_opcode(regs, &opcode)))
615 if (unlikely(compute_return_epc(regs)))
618 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
619 int rd = (opcode & RD) >> 11;
620 int rt = (opcode & RT) >> 16;
623 regs->regs[rt] = ti->tp_value;
634 asmlinkage void do_ov(struct pt_regs *regs)
638 die_if_kernel("Integer overflow", regs);
640 info.si_code = FPE_INTOVF;
641 info.si_signo = SIGFPE;
643 info.si_addr = (void __user *) regs->cp0_epc;
644 force_sig_info(SIGFPE, &info, current);
648 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
650 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
652 die_if_kernel("FP exception in kernel code", regs);
654 if (fcr31 & FPU_CSR_UNI_X) {
659 #ifdef CONFIG_PREEMPT
660 if (!is_fpu_owner()) {
661 /* We might lose fpu before disabling preempt... */
663 BUG_ON(!used_math());
668 * Unimplemented operation exception. If we've got the full
669 * software emulator on-board, let's use it...
671 * Force FPU to dump state into task/thread context. We're
672 * moving a lot of data here for what is probably a single
673 * instruction, but the alternative is to pre-decode the FP
674 * register operands before invoking the emulator, which seems
675 * a bit extreme for what should be an infrequent event.
678 /* Ensure 'resume' not overwrite saved fp context again. */
683 /* Run the emulator */
684 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu);
688 own_fpu(); /* Using the FPU again. */
690 * We can't allow the emulated instruction to leave any of
691 * the cause bit set in $fcr31.
693 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
695 /* Restore the hardware register state */
700 /* If something went wrong, signal */
702 force_sig(sig, current);
707 force_sig(SIGFPE, current);
710 asmlinkage void do_bp(struct pt_regs *regs)
712 unsigned int opcode, bcode;
715 die_if_kernel("Break instruction in kernel code", regs);
717 if (get_insn_opcode(regs, &opcode))
721 * There is the ancient bug in the MIPS assemblers that the break
722 * code starts left to bit 16 instead to bit 6 in the opcode.
723 * Gas is bug-compatible, but not always, grrr...
724 * We handle both cases with a simple heuristics. --macro
726 bcode = ((opcode >> 6) & ((1 << 20) - 1));
727 if (bcode < (1 << 10))
731 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
732 * insns, even for break codes that indicate arithmetic failures.
734 * But should we continue the brokenness??? --macro
737 case BRK_OVERFLOW << 10:
738 case BRK_DIVZERO << 10:
739 if (bcode == (BRK_DIVZERO << 10))
740 info.si_code = FPE_INTDIV;
742 info.si_code = FPE_INTOVF;
743 info.si_signo = SIGFPE;
745 info.si_addr = (void __user *) regs->cp0_epc;
746 force_sig_info(SIGFPE, &info, current);
749 force_sig(SIGTRAP, current);
753 asmlinkage void do_tr(struct pt_regs *regs)
755 unsigned int opcode, tcode = 0;
758 die_if_kernel("Trap instruction in kernel code", regs);
760 if (get_insn_opcode(regs, &opcode))
763 /* Immediate versions don't provide a code. */
764 if (!(opcode & OPCODE))
765 tcode = ((opcode >> 6) & ((1 << 10) - 1));
768 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
769 * insns, even for trap codes that indicate arithmetic failures.
771 * But should we continue the brokenness??? --macro
776 if (tcode == BRK_DIVZERO)
777 info.si_code = FPE_INTDIV;
779 info.si_code = FPE_INTOVF;
780 info.si_signo = SIGFPE;
782 info.si_addr = (void __user *) regs->cp0_epc;
783 force_sig_info(SIGFPE, &info, current);
786 force_sig(SIGTRAP, current);
790 asmlinkage void do_ri(struct pt_regs *regs)
792 die_if_kernel("Reserved instruction in kernel code", regs);
795 if (!simulate_llsc(regs))
798 if (!simulate_rdhwr(regs))
801 force_sig(SIGILL, current);
804 asmlinkage void do_cpu(struct pt_regs *regs)
808 die_if_kernel("do_cpu invoked from kernel context!", regs);
810 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
815 if (!simulate_llsc(regs))
818 if (!simulate_rdhwr(regs))
827 if (used_math()) { /* Using the FPU again. */
829 } else { /* First time FPU user. */
837 int sig = fpu_emulator_cop1Handler(regs,
838 ¤t->thread.fpu);
840 force_sig(sig, current);
841 #ifdef CONFIG_MIPS_MT_FPAFF
844 * MIPS MT processors may have fewer FPU contexts
845 * than CPU threads. If we've emulated more than
846 * some threshold number of instructions, force
847 * migration to a "CPU" that has FP support.
849 if(mt_fpemul_threshold > 0
850 && ((current->thread.emulated_fp++
851 > mt_fpemul_threshold))) {
853 * If there's no FPU present, or if the
854 * application has already restricted
855 * the allowed set to exclude any CPUs
856 * with FPUs, we'll skip the procedure.
858 if (cpus_intersects(current->cpus_allowed,
863 current->thread.user_cpus_allowed,
865 set_cpus_allowed(current, tmask);
866 current->thread.mflags |= MF_FPUBOUND;
870 #endif /* CONFIG_MIPS_MT_FPAFF */
877 die_if_kernel("do_cpu invoked from kernel context!", regs);
881 force_sig(SIGILL, current);
884 asmlinkage void do_mdmx(struct pt_regs *regs)
886 force_sig(SIGILL, current);
889 asmlinkage void do_watch(struct pt_regs *regs)
892 * We use the watch exception where available to detect stack
897 panic("Caught WATCH exception - probably caused by stack overflow.");
900 asmlinkage void do_mcheck(struct pt_regs *regs)
902 const int field = 2 * sizeof(unsigned long);
903 int multi_match = regs->cp0_status & ST0_TS;
908 printk("Index : %0x\n", read_c0_index());
909 printk("Pagemask: %0x\n", read_c0_pagemask());
910 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
911 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
912 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
917 show_code((unsigned int *) regs->cp0_epc);
920 * Some chips may have other causes of machine check (e.g. SB1
923 panic("Caught Machine Check exception - %scaused by multiple "
924 "matching entries in the TLB.",
925 (multi_match) ? "" : "not ");
928 asmlinkage void do_mt(struct pt_regs *regs)
932 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
933 >> VPECONTROL_EXCPT_SHIFT;
936 printk(KERN_DEBUG "Thread Underflow\n");
939 printk(KERN_DEBUG "Thread Overflow\n");
942 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
945 printk(KERN_DEBUG "Gating Storage Exception\n");
948 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
951 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
954 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
958 die_if_kernel("MIPS MT Thread exception in kernel", regs);
960 force_sig(SIGILL, current);
964 asmlinkage void do_dsp(struct pt_regs *regs)
967 panic("Unexpected DSP exception\n");
969 force_sig(SIGILL, current);
972 asmlinkage void do_reserved(struct pt_regs *regs)
975 * Game over - no way to handle this if it ever occurs. Most probably
976 * caused by a new unknown cpu type or after another deadly
977 * hard/software error.
980 panic("Caught reserved exception %ld - should not happen.",
981 (regs->cp0_cause & 0x7f) >> 2);
984 asmlinkage void do_default_vi(struct pt_regs *regs)
987 panic("Caught unexpected vectored interrupt.");
991 * Some MIPS CPUs can enable/disable for cache parity detection, but do
994 static inline void parity_protection_init(void)
996 switch (current_cpu_data.cputype) {
1000 write_c0_ecc(0x80000000);
1001 back_to_back_c0_hazard();
1002 /* Set the PE bit (bit 31) in the c0_errctl register. */
1003 printk(KERN_INFO "Cache parity protection %sabled\n",
1004 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1008 /* Clear the DE bit (bit 16) in the c0_status register. */
1009 printk(KERN_INFO "Enable cache parity protection for "
1010 "MIPS 20KC/25KF CPUs.\n");
1011 clear_c0_status(ST0_DE);
1018 asmlinkage void cache_parity_error(void)
1020 const int field = 2 * sizeof(unsigned long);
1021 unsigned int reg_val;
1023 /* For the moment, report the problem and hang. */
1024 printk("Cache error exception:\n");
1025 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1026 reg_val = read_c0_cacheerr();
1027 printk("c0_cacheerr == %08x\n", reg_val);
1029 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1030 reg_val & (1<<30) ? "secondary" : "primary",
1031 reg_val & (1<<31) ? "data" : "insn");
1032 printk("Error bits: %s%s%s%s%s%s%s\n",
1033 reg_val & (1<<29) ? "ED " : "",
1034 reg_val & (1<<28) ? "ET " : "",
1035 reg_val & (1<<26) ? "EE " : "",
1036 reg_val & (1<<25) ? "EB " : "",
1037 reg_val & (1<<24) ? "EI " : "",
1038 reg_val & (1<<23) ? "E1 " : "",
1039 reg_val & (1<<22) ? "E0 " : "");
1040 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1042 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1043 if (reg_val & (1<<22))
1044 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1046 if (reg_val & (1<<23))
1047 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1050 panic("Can't handle the cache error!");
1054 * SDBBP EJTAG debug exception handler.
1055 * We skip the instruction and return to the next instruction.
1057 void ejtag_exception_handler(struct pt_regs *regs)
1059 const int field = 2 * sizeof(unsigned long);
1060 unsigned long depc, old_epc;
1063 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1064 depc = read_c0_depc();
1065 debug = read_c0_debug();
1066 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1067 if (debug & 0x80000000) {
1069 * In branch delay slot.
1070 * We cheat a little bit here and use EPC to calculate the
1071 * debug return address (DEPC). EPC is restored after the
1074 old_epc = regs->cp0_epc;
1075 regs->cp0_epc = depc;
1076 __compute_return_epc(regs);
1077 depc = regs->cp0_epc;
1078 regs->cp0_epc = old_epc;
1081 write_c0_depc(depc);
1084 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1085 write_c0_debug(debug | 0x100);
1090 * NMI exception handler.
1092 void nmi_exception_handler(struct pt_regs *regs)
1094 #ifdef CONFIG_MIPS_MT_SMTC
1095 unsigned long dvpret = dvpe();
1097 printk("NMI taken!!!!\n");
1098 mips_mt_regdump(dvpret);
1101 printk("NMI taken!!!!\n");
1102 #endif /* CONFIG_MIPS_MT_SMTC */
1107 #define VECTORSPACING 0x100 /* for EI/VI mode */
1109 unsigned long ebase;
1110 unsigned long exception_handlers[32];
1111 unsigned long vi_handlers[64];
1114 * As a side effect of the way this is implemented we're limited
1115 * to interrupt handlers in the address range from
1116 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1118 void *set_except_vector(int n, void *addr)
1120 unsigned long handler = (unsigned long) addr;
1121 unsigned long old_handler = exception_handlers[n];
1123 exception_handlers[n] = handler;
1124 if (n == 0 && cpu_has_divec) {
1125 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1126 (0x03ffffff & (handler >> 2));
1127 flush_icache_range(ebase + 0x200, ebase + 0x204);
1129 return (void *)old_handler;
1132 #ifdef CONFIG_CPU_MIPSR2_SRS
1134 * MIPSR2 shadow register set allocation
1138 static struct shadow_registers {
1140 * Number of shadow register sets supported
1142 unsigned long sr_supported;
1144 * Bitmap of allocated shadow registers
1146 unsigned long sr_allocated;
1149 static void mips_srs_init(void)
1151 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1152 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1153 shadow_registers.sr_supported);
1154 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1157 int mips_srs_max(void)
1159 return shadow_registers.sr_supported;
1162 int mips_srs_alloc(void)
1164 struct shadow_registers *sr = &shadow_registers;
1168 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1169 if (set >= sr->sr_supported)
1172 if (test_and_set_bit(set, &sr->sr_allocated))
1178 void mips_srs_free(int set)
1180 struct shadow_registers *sr = &shadow_registers;
1182 clear_bit(set, &sr->sr_allocated);
1185 static void *set_vi_srs_handler(int n, void *addr, int srs)
1187 unsigned long handler;
1188 unsigned long old_handler = vi_handlers[n];
1192 if (!cpu_has_veic && !cpu_has_vint)
1196 handler = (unsigned long) do_default_vi;
1199 handler = (unsigned long) addr;
1200 vi_handlers[n] = (unsigned long) addr;
1202 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1204 if (srs >= mips_srs_max())
1205 panic("Shadow register set %d not supported", srs);
1208 if (board_bind_eic_interrupt)
1209 board_bind_eic_interrupt (n, srs);
1210 } else if (cpu_has_vint) {
1211 /* SRSMap is only defined if shadow sets are implemented */
1212 if (mips_srs_max() > 1)
1213 change_c0_srsmap (0xf << n*4, srs << n*4);
1218 * If no shadow set is selected then use the default handler
1219 * that does normal register saving and a standard interrupt exit
1222 extern char except_vec_vi, except_vec_vi_lui;
1223 extern char except_vec_vi_ori, except_vec_vi_end;
1224 #ifdef CONFIG_MIPS_MT_SMTC
1226 * We need to provide the SMTC vectored interrupt handler
1227 * not only with the address of the handler, but with the
1228 * Status.IM bit to be masked before going there.
1230 extern char except_vec_vi_mori;
1231 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1232 #endif /* CONFIG_MIPS_MT_SMTC */
1233 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1234 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1235 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1237 if (handler_len > VECTORSPACING) {
1239 * Sigh... panicing won't help as the console
1240 * is probably not configured :(
1242 panic ("VECTORSPACING too small");
1245 memcpy (b, &except_vec_vi, handler_len);
1246 #ifdef CONFIG_MIPS_MT_SMTC
1248 printk("Vector index %d exceeds SMTC maximum\n", n);
1249 w = (u32 *)(b + mori_offset);
1250 *w = (*w & 0xffff0000) | (0x100 << n);
1251 #endif /* CONFIG_MIPS_MT_SMTC */
1252 w = (u32 *)(b + lui_offset);
1253 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1254 w = (u32 *)(b + ori_offset);
1255 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1256 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1260 * In other cases jump directly to the interrupt handler
1262 * It is the handlers responsibility to save registers if required
1263 * (eg hi/lo) and return from the exception using "eret"
1266 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1268 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1271 return (void *)old_handler;
1274 void *set_vi_handler(int n, void *addr)
1276 return set_vi_srs_handler(n, addr, 0);
1281 static inline void mips_srs_init(void)
1285 #endif /* CONFIG_CPU_MIPSR2_SRS */
1288 * This is used by native signal handling
1290 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1291 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1293 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1294 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1296 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1297 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1300 static int smp_save_fp_context(struct sigcontext *sc)
1303 ? _save_fp_context(sc)
1304 : fpu_emulator_save_context(sc);
1307 static int smp_restore_fp_context(struct sigcontext *sc)
1310 ? _restore_fp_context(sc)
1311 : fpu_emulator_restore_context(sc);
1315 static inline void signal_init(void)
1318 /* For now just do the cpu_has_fpu check when the functions are invoked */
1319 save_fp_context = smp_save_fp_context;
1320 restore_fp_context = smp_restore_fp_context;
1323 save_fp_context = _save_fp_context;
1324 restore_fp_context = _restore_fp_context;
1326 save_fp_context = fpu_emulator_save_context;
1327 restore_fp_context = fpu_emulator_restore_context;
1332 #ifdef CONFIG_MIPS32_COMPAT
1335 * This is used by 32-bit signal stuff on the 64-bit kernel
1337 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1338 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1340 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1341 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1343 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1344 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1346 static inline void signal32_init(void)
1349 save_fp_context32 = _save_fp_context32;
1350 restore_fp_context32 = _restore_fp_context32;
1352 save_fp_context32 = fpu_emulator_save_context32;
1353 restore_fp_context32 = fpu_emulator_restore_context32;
1358 extern void cpu_cache_init(void);
1359 extern void tlb_init(void);
1360 extern void flush_tlb_handlers(void);
1362 void __init per_cpu_trap_init(void)
1364 unsigned int cpu = smp_processor_id();
1365 unsigned int status_set = ST0_CU0;
1366 #ifdef CONFIG_MIPS_MT_SMTC
1367 int secondaryTC = 0;
1368 int bootTC = (cpu == 0);
1371 * Only do per_cpu_trap_init() for first TC of Each VPE.
1372 * Note that this hack assumes that the SMTC init code
1373 * assigns TCs consecutively and in ascending order.
1376 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1377 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1379 #endif /* CONFIG_MIPS_MT_SMTC */
1382 * Disable coprocessors and select 32-bit or 64-bit addressing
1383 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1384 * flag that some firmware may have left set and the TS bit (for
1385 * IP27). Set XX for ISA IV code to work.
1388 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1390 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1391 status_set |= ST0_XX;
1392 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1396 set_c0_status(ST0_MX);
1398 #ifdef CONFIG_CPU_MIPSR2
1399 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1402 #ifdef CONFIG_MIPS_MT_SMTC
1404 #endif /* CONFIG_MIPS_MT_SMTC */
1407 * Interrupt handling.
1409 if (cpu_has_veic || cpu_has_vint) {
1410 write_c0_ebase (ebase);
1411 /* Setting vector spacing enables EI/VI mode */
1412 change_c0_intctl (0x3e0, VECTORSPACING);
1414 if (cpu_has_divec) {
1415 if (cpu_has_mipsmt) {
1416 unsigned int vpflags = dvpe();
1417 set_c0_cause(CAUSEF_IV);
1420 set_c0_cause(CAUSEF_IV);
1422 #ifdef CONFIG_MIPS_MT_SMTC
1424 #endif /* CONFIG_MIPS_MT_SMTC */
1426 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1427 TLBMISS_HANDLER_SETUP();
1429 atomic_inc(&init_mm.mm_count);
1430 current->active_mm = &init_mm;
1431 BUG_ON(current->mm);
1432 enter_lazy_tlb(&init_mm, current);
1434 #ifdef CONFIG_MIPS_MT_SMTC
1436 #endif /* CONFIG_MIPS_MT_SMTC */
1439 #ifdef CONFIG_MIPS_MT_SMTC
1441 #endif /* CONFIG_MIPS_MT_SMTC */
1444 /* Install CPU exception handler */
1445 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1447 memcpy((void *)(ebase + offset), addr, size);
1448 flush_icache_range(ebase + offset, ebase + offset + size);
1451 /* Install uncached CPU exception handler */
1452 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1455 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1458 unsigned long uncached_ebase = TO_UNCAC(ebase);
1461 memcpy((void *)(uncached_ebase + offset), addr, size);
1464 void __init trap_init(void)
1466 extern char except_vec3_generic, except_vec3_r4000;
1467 extern char except_vec4;
1470 if (cpu_has_veic || cpu_has_vint)
1471 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1477 per_cpu_trap_init();
1480 * Copy the generic exception handlers to their final destination.
1481 * This will be overriden later as suitable for a particular
1484 set_handler(0x180, &except_vec3_generic, 0x80);
1487 * Setup default vectors
1489 for (i = 0; i <= 31; i++)
1490 set_except_vector(i, handle_reserved);
1493 * Copy the EJTAG debug exception vector handler code to it's final
1496 if (cpu_has_ejtag && board_ejtag_handler_setup)
1497 board_ejtag_handler_setup ();
1500 * Only some CPUs have the watch exceptions.
1503 set_except_vector(23, handle_watch);
1506 * Initialise interrupt handlers
1508 if (cpu_has_veic || cpu_has_vint) {
1509 int nvec = cpu_has_veic ? 64 : 8;
1510 for (i = 0; i < nvec; i++)
1511 set_vi_handler(i, NULL);
1513 else if (cpu_has_divec)
1514 set_handler(0x200, &except_vec4, 0x8);
1517 * Some CPUs can enable/disable for cache parity detection, but does
1518 * it different ways.
1520 parity_protection_init();
1523 * The Data Bus Errors / Instruction Bus Errors are signaled
1524 * by external hardware. Therefore these two exceptions
1525 * may have board specific handlers.
1530 set_except_vector(0, handle_int);
1531 set_except_vector(1, handle_tlbm);
1532 set_except_vector(2, handle_tlbl);
1533 set_except_vector(3, handle_tlbs);
1535 set_except_vector(4, handle_adel);
1536 set_except_vector(5, handle_ades);
1538 set_except_vector(6, handle_ibe);
1539 set_except_vector(7, handle_dbe);
1541 set_except_vector(8, handle_sys);
1542 set_except_vector(9, handle_bp);
1543 set_except_vector(10, handle_ri);
1544 set_except_vector(11, handle_cpu);
1545 set_except_vector(12, handle_ov);
1546 set_except_vector(13, handle_tr);
1548 if (current_cpu_data.cputype == CPU_R6000 ||
1549 current_cpu_data.cputype == CPU_R6000A) {
1551 * The R6000 is the only R-series CPU that features a machine
1552 * check exception (similar to the R4000 cache error) and
1553 * unaligned ldc1/sdc1 exception. The handlers have not been
1554 * written yet. Well, anyway there is no R6000 machine on the
1555 * current list of targets for Linux/MIPS.
1556 * (Duh, crap, there is someone with a triple R6k machine)
1558 //set_except_vector(14, handle_mc);
1559 //set_except_vector(15, handle_ndc);
1563 if (board_nmi_handler_setup)
1564 board_nmi_handler_setup();
1566 if (cpu_has_fpu && !cpu_has_nofpuex)
1567 set_except_vector(15, handle_fpe);
1569 set_except_vector(22, handle_mdmx);
1572 set_except_vector(24, handle_mcheck);
1575 set_except_vector(25, handle_mt);
1578 set_except_vector(26, handle_dsp);
1581 /* Special exception: R4[04]00 uses also the divec space. */
1582 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1583 else if (cpu_has_4kex)
1584 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1586 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1589 #ifdef CONFIG_MIPS32_COMPAT
1593 flush_icache_range(ebase, ebase + 0x400);
1594 flush_tlb_handlers();