1 /* Copyright (C) 2004 Mips Technologies, Inc */
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/cpumask.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel_stat.h>
8 #include <linux/module.h>
11 #include <asm/processor.h>
12 #include <asm/atomic.h>
13 #include <asm/system.h>
14 #include <asm/hardirq.h>
15 #include <asm/hazards.h>
17 #include <asm/mmu_context.h>
19 #include <asm/mipsregs.h>
20 #include <asm/cacheflush.h>
22 #include <asm/addrspace.h>
24 #include <asm/smtc_ipi.h>
25 #include <asm/smtc_proc.h>
28 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
29 * in do_IRQ. These are passed in setup_irq_smtc() and stored
32 unsigned long irq_hwmask[NR_IRQS];
34 #define LOCK_MT_PRA() \
35 local_irq_save(flags); \
38 #define UNLOCK_MT_PRA() \
40 local_irq_restore(flags)
42 #define LOCK_CORE_PRA() \
43 local_irq_save(flags); \
46 #define UNLOCK_CORE_PRA() \
48 local_irq_restore(flags)
51 * Data structures purely associated with SMTC parallelism
56 * Table for tracking ASIDs whose lifetime is prolonged.
59 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
62 * Clock interrupt "latch" buffers, per "CPU"
65 unsigned int ipi_timer_latch[NR_CPUS];
68 * Number of InterProcessor Interupt (IPI) message buffers to allocate
71 #define IPIBUF_PER_CPU 4
73 static struct smtc_ipi_q IPIQ[NR_CPUS];
74 static struct smtc_ipi_q freeIPIq;
77 /* Forward declarations */
79 void ipi_decode(struct smtc_ipi *);
80 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
81 static void setup_cross_vpe_interrupts(unsigned int nvpe);
82 void init_smtc_stats(void);
84 /* Global SMTC Status */
86 unsigned int smtc_status = 0;
88 /* Boot command line configuration overrides */
90 static int ipibuffers = 0;
91 static int nostlb = 0;
92 static int asidmask = 0;
93 unsigned long smtc_asid_mask = 0xff;
95 static int __init ipibufs(char *str)
97 get_option(&str, &ipibuffers);
101 static int __init stlb_disable(char *s)
107 static int __init asidmask_set(char *str)
109 get_option(&str, &asidmask);
119 smtc_asid_mask = (unsigned long)asidmask;
122 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask);
127 __setup("ipibufs=", ipibufs);
128 __setup("nostlb", stlb_disable);
129 __setup("asidmask=", asidmask_set);
131 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
133 static int hang_trig = 0;
135 static int __init hangtrig_enable(char *s)
142 __setup("hangtrig", hangtrig_enable);
144 #define DEFAULT_BLOCKED_IPI_LIMIT 32
146 static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT;
148 static int __init tintq(char *str)
150 get_option(&str, &timerq_limit);
154 __setup("tintq=", tintq);
156 static int imstuckcount[2][8];
157 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
158 static int vpemask[2][8] = {
159 {0, 0, 1, 0, 0, 0, 0, 1},
160 {0, 0, 0, 0, 0, 0, 0, 1}
162 int tcnoprog[NR_CPUS];
163 static atomic_t idle_hook_initialized = {0};
164 static int clock_hang_reported[NR_CPUS];
166 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
168 /* Initialize shared TLB - the should probably migrate to smtc_setup_cpus() */
170 void __init sanitize_tlb_entries(void)
172 printk("Deprecated sanitize_tlb_entries() invoked\n");
177 * Configure shared TLB - VPC configuration bit must be set by caller
180 static void smtc_configure_tlb(void)
183 unsigned long mvpconf0;
184 unsigned long config1val;
186 /* Set up ASID preservation table */
187 for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) {
188 for(i = 0; i < MAX_SMTC_ASIDS; i++) {
189 smtc_live_asid[vpes][i] = 0;
192 mvpconf0 = read_c0_mvpconf0();
194 if ((vpes = ((mvpconf0 & MVPCONF0_PVPE)
195 >> MVPCONF0_PVPE_SHIFT) + 1) > 1) {
196 /* If we have multiple VPEs, try to share the TLB */
197 if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) {
199 * If TLB sizing is programmable, shared TLB
200 * size is the total available complement.
201 * Otherwise, we have to take the sum of all
202 * static VPE TLB entries.
204 if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE)
205 >> MVPCONF0_PTLBE_SHIFT)) == 0) {
207 * If there's more than one VPE, there had better
208 * be more than one TC, because we need one to bind
209 * to each VPE in turn to be able to read
210 * its configuration state!
213 /* Stop the TC from doing anything foolish */
214 write_tc_c0_tchalt(TCHALT_H);
216 /* No need to un-Halt - that happens later anyway */
217 for (i=0; i < vpes; i++) {
218 write_tc_c0_tcbind(i);
220 * To be 100% sure we're really getting the right
221 * information, we exit the configuration state
222 * and do an IHB after each rebinding.
225 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
228 * Only count if the MMU Type indicated is TLB
230 if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
231 config1val = read_vpe_c0_config1();
232 tlbsiz += ((config1val >> 25) & 0x3f) + 1;
235 /* Put core back in configuration state */
237 read_c0_mvpcontrol() | MVPCONTROL_VPC );
241 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
245 * Setup kernel data structures to use software total,
246 * rather than read the per-VPE Config1 value. The values
247 * for "CPU 0" gets copied to all the other CPUs as part
248 * of their initialization in smtc_cpu_setup().
251 /* MIPS32 limits TLB indices to 64 */
254 cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
255 smtc_status |= SMTC_TLB_SHARED;
256 local_flush_tlb_all();
258 printk("TLB of %d entry pairs shared by %d VPEs\n",
261 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
268 * Incrementally build the CPU map out of constituent MIPS MT cores,
269 * using the specified available VPEs and TCs. Plaform code needs
270 * to ensure that each MIPS MT core invokes this routine on reset,
273 * This version of the build_cpu_map and prepare_cpus routines assumes
274 * that *all* TCs of a MIPS MT core will be used for Linux, and that
275 * they will be spread across *all* available VPEs (to minimise the
276 * loss of efficiency due to exception service serialization).
277 * An improved version would pick up configuration information and
278 * possibly leave some TCs/VPEs as "slave" processors.
280 * Use c0_MVPConf0 to find out how many TCs are available, setting up
281 * phys_cpu_present_map and the logical/physical mappings.
284 int __init mipsmt_build_cpu_map(int start_cpu_slot)
289 * The CPU map isn't actually used for anything at this point,
290 * so it's not clear what else we should do apart from set
291 * everything up so that "logical" = "physical".
293 ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
294 for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) {
295 cpu_set(i, phys_cpu_present_map);
296 __cpu_number_map[i] = i;
297 __cpu_logical_map[i] = i;
299 /* Initialize map of CPUs with FPUs */
300 cpus_clear(mt_fpu_cpumask);
302 /* One of those TC's is the one booting, and not a secondary... */
303 printk("%i available secondary CPU TC(s)\n", i - 1);
309 * Common setup before any secondaries are started
310 * Make sure all CPU's are in a sensible state before we boot any of the
313 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
314 * as possible across the available VPEs.
317 static void smtc_tc_setup(int vpe, int tc, int cpu)
320 write_tc_c0_tchalt(TCHALT_H);
322 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
323 & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
325 write_tc_c0_tccontext(0);
327 write_tc_c0_tcbind(vpe);
328 /* In general, all TCs should have the same cpu_data indications */
329 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
330 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
331 if (cpu_data[0].cputype == CPU_34K)
332 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
333 cpu_data[cpu].vpe_id = vpe;
334 cpu_data[cpu].tc_id = tc;
338 void mipsmt_prepare_cpus(void)
340 int i, vpe, tc, ntc, nvpe, tcpervpe, slop, cpu;
344 struct smtc_ipi *pipi;
346 /* disable interrupts so we can disable MT */
347 local_irq_save(flags);
348 /* disable MT so we can configure */
352 spin_lock_init(&freeIPIq.lock);
355 * We probably don't have as many VPEs as we do SMP "CPUs",
356 * but it's possible - and in any case we'll never use more!
358 for (i=0; i<NR_CPUS; i++) {
359 IPIQ[i].head = IPIQ[i].tail = NULL;
360 spin_lock_init(&IPIQ[i].lock);
362 ipi_timer_latch[i] = 0;
365 /* cpu_data index starts at zero */
367 cpu_data[cpu].vpe_id = 0;
368 cpu_data[cpu].tc_id = 0;
371 /* Report on boot-time options */
372 mips_mt_set_cpuoptions ();
374 printk("Limit of %d VPEs set\n", vpelimit);
376 printk("Limit of %d TCs set\n", tclimit);
378 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
381 printk("ASID mask value override to 0x%x\n", asidmask);
384 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
386 printk("Logic Analyser Trigger on suspected TC hang\n");
387 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
389 /* Put MVPE's into 'configuration state' */
390 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC );
392 val = read_c0_mvpconf0();
393 nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
394 if (vpelimit > 0 && nvpe > vpelimit)
396 ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
399 if (tclimit > 0 && ntc > tclimit)
401 tcpervpe = ntc / nvpe;
402 slop = ntc % nvpe; /* Residual TCs, < NVPE */
404 /* Set up shared TLB */
405 smtc_configure_tlb();
407 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
412 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP);
415 printk("VPE %d: TC", vpe);
416 for (i = 0; i < tcpervpe; i++) {
418 * TC 0 is bound to VPE 0 at reset,
419 * and is presumably executing this
420 * code. Leave it alone!
423 smtc_tc_setup(vpe,tc, cpu);
431 smtc_tc_setup(vpe,tc, cpu);
440 * Clear any stale software interrupts from VPE's Cause
442 write_vpe_c0_cause(0);
445 * Clear ERL/EXL of VPEs other than 0
446 * and set restricted interrupt enable/mask.
448 write_vpe_c0_status((read_vpe_c0_status()
449 & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM))
450 | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7
453 * set config to be the same as vpe0,
454 * particularly kseg0 coherency alg
456 write_vpe_c0_config(read_c0_config());
457 /* Clear any pending timer interrupt */
458 write_vpe_c0_compare(0);
459 /* Propagate Config7 */
460 write_vpe_c0_config7(read_c0_config7());
461 write_vpe_c0_count(read_c0_count());
463 /* enable multi-threading within VPE */
464 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
466 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
470 * Pull any physically present but unused TCs out of circulation.
472 while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) {
473 cpu_clear(tc, phys_cpu_present_map);
474 cpu_clear(tc, cpu_present_map);
478 /* release config state */
479 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
483 /* Set up coprocessor affinity CPU mask(s) */
485 for (tc = 0; tc < ntc; tc++) {
486 if (cpu_data[tc].options & MIPS_CPU_FPU)
487 cpu_set(tc, mt_fpu_cpumask);
490 /* set up ipi interrupts... */
492 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
494 setup_cross_vpe_interrupts(nvpe);
496 /* Set up queue of free IPI "messages". */
497 nipi = NR_CPUS * IPIBUF_PER_CPU;
501 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
503 panic("kmalloc of IPI message buffers failed\n");
505 printk("IPI buffer pool of %d buffers\n", nipi);
506 for (i = 0; i < nipi; i++) {
507 smtc_ipi_nq(&freeIPIq, pipi);
511 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
514 local_irq_restore(flags);
515 /* Initialize SMTC /proc statistics/diagnostics */
521 * Setup the PC, SP, and GP of a secondary processor and start it
523 * smp_bootstrap is the place to resume from
524 * __KSTK_TOS(idle) is apparently the stack pointer
525 * (unsigned long)idle->thread_info the gp
528 void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
530 extern u32 kernelsp[NR_CPUS];
535 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
538 settc(cpu_data[cpu].tc_id);
541 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
544 kernelsp[cpu] = __KSTK_TOS(idle);
545 write_tc_gpr_sp(__KSTK_TOS(idle));
548 write_tc_gpr_gp((unsigned long)task_thread_info(idle));
550 smtc_status |= SMTC_MTC_ACTIVE;
551 write_tc_c0_tchalt(0);
552 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
558 void smtc_init_secondary(void)
561 * Start timer on secondary VPEs if necessary.
562 * plat_timer_setup has already have been invoked by init/main
563 * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that
564 * SMTC init code assigns TCs consdecutively and in ascending order
565 * to across available VPEs.
567 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
568 ((read_c0_tcbind() & TCBIND_CURVPE)
569 != cpu_data[smp_processor_id() - 1].vpe_id)){
570 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
576 void smtc_smp_finish(void)
578 printk("TC %d going on-line as CPU %d\n",
579 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
582 void smtc_cpus_done(void)
587 * Support for SMTC-optimized driver IRQ registration
591 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
592 * in do_IRQ. These are passed in setup_irq_smtc() and stored
596 int setup_irq_smtc(unsigned int irq, struct irqaction * new,
597 unsigned long hwmask)
599 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
600 unsigned int vpe = current_cpu_data.vpe_id;
602 vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
604 irq_hwmask[irq] = hwmask;
606 return setup_irq(irq, new);
609 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
611 * Support for IRQ affinity to TCs
614 void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
617 * If a "fast path" cache of quickly decodable affinity state
618 * is maintained, this is where it gets done, on a call up
619 * from the platform affinity code.
623 void smtc_forward_irq(unsigned int irq)
628 * OK wise guy, now figure out how to get the IRQ
629 * to be serviced on an authorized "CPU".
631 * Ideally, to handle the situation where an IRQ has multiple
632 * eligible CPUS, we would maintain state per IRQ that would
633 * allow a fair distribution of service requests. Since the
634 * expected use model is any-or-only-one, for simplicity
635 * and efficiency, we just pick the easiest one to find.
638 target = first_cpu(irq_desc[irq].affinity);
641 * We depend on the platform code to have correctly processed
642 * IRQ affinity change requests to ensure that the IRQ affinity
643 * mask has been purged of bits corresponding to nonexistent and
644 * offline "CPUs", and to TCs bound to VPEs other than the VPE
645 * connected to the physical interrupt input for the interrupt
646 * in question. Otherwise we have a nasty problem with interrupt
647 * mask management. This is best handled in non-performance-critical
648 * platform IRQ affinity setting code, to minimize interrupt-time
652 /* If no one is eligible, service locally */
653 if (target >= NR_CPUS) {
654 do_IRQ_no_affinity(irq);
658 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
661 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
664 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
665 * Within a VPE one TC can interrupt another by different approaches.
666 * The easiest to get right would probably be to make all TCs except
667 * the target IXMT and set a software interrupt, but an IXMT-based
668 * scheme requires that a handler must run before a new IPI could
669 * be sent, which would break the "broadcast" loops in MIPS MT.
670 * A more gonzo approach within a VPE is to halt the TC, extract
671 * its Restart, Status, and a couple of GPRs, and program the Restart
672 * address to emulate an interrupt.
674 * Within a VPE, one can be confident that the target TC isn't in
675 * a critical EXL state when halted, since the write to the Halt
676 * register could not have issued on the writing thread if the
677 * halting thread had EXL set. So k0 and k1 of the target TC
678 * can be used by the injection code. Across VPEs, one can't
679 * be certain that the target TC isn't in a critical exception
680 * state. So we try a two-step process of sending a software
681 * interrupt to the target VPE, which either handles the event
682 * itself (if it was the target) or injects the event within
686 static void smtc_ipi_qdump(void)
690 for (i = 0; i < NR_CPUS ;i++) {
691 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
692 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
698 * The standard atomic.h primitives don't quite do what we want
699 * here: We need an atomic add-and-return-previous-value (which
700 * could be done with atomic_add_return and a decrement) and an
701 * atomic set/zero-and-return-previous-value (which can't really
702 * be done with the atomic.h primitives). And since this is
703 * MIPS MT, we can assume that we have LL/SC.
705 static __inline__ int atomic_postincrement(unsigned int *pv)
707 unsigned long result;
711 __asm__ __volatile__(
717 : "=&r" (result), "=&r" (temp), "=m" (*pv)
724 void smtc_send_ipi(int cpu, int type, unsigned int action)
727 struct smtc_ipi *pipi;
731 if (cpu == smp_processor_id()) {
732 printk("Cannot Send IPI to self!\n");
735 /* Set up a descriptor, to be delivered either promptly or queued */
736 pipi = smtc_ipi_dq(&freeIPIq);
739 mips_mt_regdump(dvpe());
740 panic("IPI Msg. Buffers Depleted\n");
743 pipi->arg = (void *)action;
745 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
746 /* If not on same VPE, enqueue and send cross-VPE interupt */
747 smtc_ipi_nq(&IPIQ[cpu], pipi);
749 settc(cpu_data[cpu].tc_id);
750 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1);
754 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
755 * since ASID shootdown on the other VPE may
756 * collide with this operation.
759 settc(cpu_data[cpu].tc_id);
760 /* Halt the targeted TC */
761 write_tc_c0_tchalt(TCHALT_H);
765 * Inspect TCStatus - if IXMT is set, we have to queue
766 * a message. Otherwise, we set up the "interrupt"
769 tcstatus = read_tc_c0_tcstatus();
771 if ((tcstatus & TCSTATUS_IXMT) != 0) {
773 * Spin-waiting here can deadlock,
774 * so we queue the message for the target TC.
776 write_tc_c0_tchalt(0);
778 /* Try to reduce redundant timer interrupt messages */
779 if (type == SMTC_CLOCK_TICK) {
780 if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){
781 smtc_ipi_nq(&freeIPIq, pipi);
785 smtc_ipi_nq(&IPIQ[cpu], pipi);
787 post_direct_ipi(cpu, pipi);
788 write_tc_c0_tchalt(0);
795 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
797 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
799 struct pt_regs *kstack;
800 unsigned long tcstatus;
801 unsigned long tcrestart;
802 extern u32 kernelsp[NR_CPUS];
803 extern void __smtc_ipi_vector(void);
805 /* Extract Status, EPC from halted TC */
806 tcstatus = read_tc_c0_tcstatus();
807 tcrestart = read_tc_c0_tcrestart();
808 /* If TCRestart indicates a WAIT instruction, advance the PC */
809 if ((tcrestart & 0x80000000)
810 && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) {
814 * Save on TC's future kernel stack
816 * CU bit of Status is indicator that TC was
817 * already running on a kernel stack...
819 if (tcstatus & ST0_CU0) {
820 /* Note that this "- 1" is pointer arithmetic */
821 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
823 kstack = ((struct pt_regs *)kernelsp[cpu]) - 1;
826 kstack->cp0_epc = (long)tcrestart;
828 kstack->cp0_tcstatus = tcstatus;
829 /* Pass token of operation to be performed kernel stack pad area */
830 kstack->pad0[4] = (unsigned long)pipi;
831 /* Pass address of function to be called likewise */
832 kstack->pad0[5] = (unsigned long)&ipi_decode;
833 /* Set interrupt exempt and kernel mode */
834 tcstatus |= TCSTATUS_IXMT;
835 tcstatus &= ~TCSTATUS_TKSU;
836 write_tc_c0_tcstatus(tcstatus);
838 /* Set TC Restart address to be SMTC IPI vector */
839 write_tc_c0_tcrestart(__smtc_ipi_vector);
842 static void ipi_resched_interrupt(void)
844 /* Return from interrupt should be enough to cause scheduler check */
848 static void ipi_call_interrupt(void)
850 /* Invoke generic function invocation code in smp.c */
851 smp_call_function_interrupt();
854 void ipi_decode(struct smtc_ipi *pipi)
856 void *arg_copy = pipi->arg;
857 int type_copy = pipi->type;
858 int dest_copy = pipi->dest;
860 smtc_ipi_nq(&freeIPIq, pipi);
862 case SMTC_CLOCK_TICK:
864 kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_compare_irq]++;
865 /* Invoke Clock "Interrupt" */
866 ipi_timer_latch[dest_copy] = 0;
867 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
868 clock_hang_reported[dest_copy] = 0;
869 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
870 local_timer_interrupt(0, NULL);
874 switch ((int)arg_copy) {
875 case SMP_RESCHEDULE_YOURSELF:
876 ipi_resched_interrupt();
878 case SMP_CALL_FUNCTION:
879 ipi_call_interrupt();
882 printk("Impossible SMTC IPI Argument 0x%x\n",
887 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
888 case IRQ_AFFINITY_IPI:
890 * Accept a "forwarded" interrupt that was initially
891 * taken by a TC who doesn't have affinity for the IRQ.
893 do_IRQ_no_affinity((int)arg_copy);
895 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
897 printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
902 void deferred_smtc_ipi(void)
904 struct smtc_ipi *pipi;
907 int q = smp_processor_id();
910 * Test is not atomic, but much faster than a dequeue,
911 * and the vast majority of invocations will have a null queue.
913 if (IPIQ[q].head != NULL) {
914 while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
915 /* ipi_decode() should be called with interrupts off */
916 local_irq_save(flags);
918 local_irq_restore(flags);
924 * Send clock tick to all TCs except the one executing the funtion
927 void smtc_timer_broadcast(void)
930 int myTC = cpu_data[smp_processor_id()].tc_id;
931 int myVPE = cpu_data[smp_processor_id()].vpe_id;
933 smtc_cpu_stats[smp_processor_id()].timerints++;
935 for_each_online_cpu(cpu) {
936 if (cpu_data[cpu].vpe_id == myVPE &&
937 cpu_data[cpu].tc_id != myTC)
938 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
943 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
944 * set via cross-VPE MTTR manipulation of the Cause register. It would be
945 * in some regards preferable to have external logic for "doorbell" hardware
949 static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
951 static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
953 int my_vpe = cpu_data[smp_processor_id()].vpe_id;
954 int my_tc = cpu_data[smp_processor_id()].tc_id;
956 struct smtc_ipi *pipi;
957 unsigned long tcstatus;
960 unsigned int mtflags;
961 unsigned int vpflags;
964 * So long as cross-VPE interrupts are done via
965 * MFTR/MTTR read-modify-writes of Cause, we need
966 * to stop other VPEs whenever the local VPE does
969 local_irq_save(flags);
971 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ);
972 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ);
975 local_irq_restore(flags);
978 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
979 * queued for TCs on this VPE other than the current one.
980 * Return-from-interrupt should cause us to drain the queue
981 * for the current TC, so we ought not to have to do it explicitly here.
984 for_each_online_cpu(cpu) {
985 if (cpu_data[cpu].vpe_id != my_vpe)
988 pipi = smtc_ipi_dq(&IPIQ[cpu]);
990 if (cpu_data[cpu].tc_id != my_tc) {
993 settc(cpu_data[cpu].tc_id);
994 write_tc_c0_tchalt(TCHALT_H);
996 tcstatus = read_tc_c0_tcstatus();
997 if ((tcstatus & TCSTATUS_IXMT) == 0) {
998 post_direct_ipi(cpu, pipi);
1001 write_tc_c0_tchalt(0);
1004 smtc_ipi_req(&IPIQ[cpu], pipi);
1008 * ipi_decode() should be called
1009 * with interrupts off
1011 local_irq_save(flags);
1013 local_irq_restore(flags);
1021 static void ipi_irq_dispatch(void)
1023 do_IRQ(cpu_ipi_irq);
1026 static struct irqaction irq_ipi = {
1027 .handler = ipi_interrupt,
1028 .flags = IRQF_DISABLED,
1030 .flags = IRQF_PERCPU
1033 static void setup_cross_vpe_interrupts(unsigned int nvpe)
1039 panic("SMTC Kernel requires Vectored Interupt support");
1041 set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
1043 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1045 set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
1049 * SMTC-specific hacks invoked from elsewhere in the kernel.
1051 * smtc_ipi_replay is called from raw_local_irq_restore which is only ever
1052 * called with interrupts disabled. We do rely on interrupts being disabled
1053 * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would
1054 * result in a recursive call to raw_local_irq_restore().
1057 static void __smtc_ipi_replay(void)
1059 unsigned int cpu = smp_processor_id();
1062 * To the extent that we've ever turned interrupts off,
1063 * we may have accumulated deferred IPIs. This is subtle.
1064 * If we use the smtc_ipi_qdepth() macro, we'll get an
1065 * exact number - but we'll also disable interrupts
1066 * and create a window of failure where a new IPI gets
1067 * queued after we test the depth but before we re-enable
1068 * interrupts. So long as IXMT never gets set, however,
1069 * we should be OK: If we pick up something and dispatch
1070 * it here, that's great. If we see nothing, but concurrent
1071 * with this operation, another TC sends us an IPI, IXMT
1072 * is clear, and we'll handle it as a real pseudo-interrupt
1073 * and not a pseudo-pseudo interrupt.
1075 if (IPIQ[cpu].depth > 0) {
1077 struct smtc_ipi_q *q = &IPIQ[cpu];
1078 struct smtc_ipi *pipi;
1079 extern void self_ipi(struct smtc_ipi *);
1081 spin_lock(&q->lock);
1082 pipi = __smtc_ipi_dq(q);
1083 spin_unlock(&q->lock);
1088 smtc_cpu_stats[cpu].selfipis++;
1093 void smtc_ipi_replay(void)
1095 raw_local_irq_disable();
1096 __smtc_ipi_replay();
1099 EXPORT_SYMBOL(smtc_ipi_replay);
1101 void smtc_idle_loop_hook(void)
1103 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1112 * printk within DMT-protected regions can deadlock,
1113 * so buffer diagnostic messages for later output.
1116 char id_ho_db_msg[768]; /* worst-case use should be less than 700 */
1118 if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */
1119 if (atomic_add_return(1, &idle_hook_initialized) == 1) {
1121 /* Tedious stuff to just do once */
1122 mvpconf0 = read_c0_mvpconf0();
1123 hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
1124 if (hook_ntcs > NR_CPUS)
1125 hook_ntcs = NR_CPUS;
1126 for (tc = 0; tc < hook_ntcs; tc++) {
1128 clock_hang_reported[tc] = 0;
1130 for (vpe = 0; vpe < 2; vpe++)
1131 for (im = 0; im < 8; im++)
1132 imstuckcount[vpe][im] = 0;
1133 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs);
1134 atomic_set(&idle_hook_initialized, 1000);
1136 /* Someone else is initializing in parallel - let 'em finish */
1137 while (atomic_read(&idle_hook_initialized) < 1000)
1142 /* Have we stupidly left IXMT set somewhere? */
1143 if (read_c0_tcstatus() & 0x400) {
1144 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1146 printk("Dangling IXMT in cpu_idle()\n");
1149 /* Have we stupidly left an IM bit turned off? */
1150 #define IM_LIMIT 2000
1151 local_irq_save(flags);
1153 pdb_msg = &id_ho_db_msg[0];
1154 im = read_c0_status();
1155 vpe = current_cpu_data.vpe_id;
1156 for (bit = 0; bit < 8; bit++) {
1158 * In current prototype, I/O interrupts
1159 * are masked for VPE > 0
1161 if (vpemask[vpe][bit]) {
1162 if (!(im & (0x100 << bit)))
1163 imstuckcount[vpe][bit]++;
1165 imstuckcount[vpe][bit] = 0;
1166 if (imstuckcount[vpe][bit] > IM_LIMIT) {
1167 set_c0_status(0x100 << bit);
1169 imstuckcount[vpe][bit] = 0;
1170 pdb_msg += sprintf(pdb_msg,
1171 "Dangling IM %d fixed for VPE %d\n", bit,
1178 * Now that we limit outstanding timer IPIs, check for hung TC
1180 for (tc = 0; tc < NR_CPUS; tc++) {
1181 /* Don't check ourself - we'll dequeue IPIs just below */
1182 if ((tc != smp_processor_id()) &&
1183 ipi_timer_latch[tc] > timerq_limit) {
1184 if (clock_hang_reported[tc] == 0) {
1185 pdb_msg += sprintf(pdb_msg,
1186 "TC %d looks hung with timer latch at %d\n",
1187 tc, ipi_timer_latch[tc]);
1188 clock_hang_reported[tc]++;
1193 local_irq_restore(flags);
1194 if (pdb_msg != &id_ho_db_msg[0])
1195 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
1196 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1199 * Replay any accumulated deferred IPIs. If "Instant Replay"
1200 * is in use, there should never be any.
1202 #ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
1204 unsigned long flags;
1206 local_irq_save(flags);
1207 __smtc_ipi_replay();
1208 local_irq_restore(flags);
1210 #endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
1213 void smtc_soft_dump(void)
1217 printk("Counter Interrupts taken per CPU (TC)\n");
1218 for (i=0; i < NR_CPUS; i++) {
1219 printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints);
1221 printk("Self-IPI invocations:\n");
1222 for (i=0; i < NR_CPUS; i++) {
1223 printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
1226 printk("Timer IPI Backlogs:\n");
1227 for (i=0; i < NR_CPUS; i++) {
1228 printk("%d: %d\n", i, ipi_timer_latch[i]);
1230 printk("%d Recoveries of \"stolen\" FPU\n",
1231 atomic_read(&smtc_fpu_recoveries));
1236 * TLB management routines special to SMTC
1239 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1241 unsigned long flags, mtflags, tcstat, prevhalt, asid;
1245 * It would be nice to be able to use a spinlock here,
1246 * but this is invoked from within TLB flush routines
1247 * that protect themselves with DVPE, so if a lock is
1248 * held by another TC, it'll never be freed.
1250 * DVPE/DMT must not be done with interrupts enabled,
1251 * so even so most callers will already have disabled
1252 * them, let's be really careful...
1255 local_irq_save(flags);
1256 if (smtc_status & SMTC_TLB_SHARED) {
1261 tlb = cpu_data[cpu].vpe_id;
1263 asid = asid_cache(cpu);
1266 if (!((asid += ASID_INC) & ASID_MASK) ) {
1267 if (cpu_has_vtag_icache)
1269 /* Traverse all online CPUs (hack requires contigous range) */
1270 for (i = 0; i < num_online_cpus(); i++) {
1272 * We don't need to worry about our own CPU, nor those of
1273 * CPUs who don't share our TLB.
1275 if ((i != smp_processor_id()) &&
1276 ((smtc_status & SMTC_TLB_SHARED) ||
1277 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) {
1278 settc(cpu_data[i].tc_id);
1279 prevhalt = read_tc_c0_tchalt() & TCHALT_H;
1281 write_tc_c0_tchalt(TCHALT_H);
1284 tcstat = read_tc_c0_tcstatus();
1285 smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
1287 write_tc_c0_tchalt(0);
1290 if (!asid) /* fix version if needed */
1291 asid = ASID_FIRST_VERSION;
1292 local_flush_tlb_all(); /* start new asid cycle */
1294 } while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
1297 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1299 for (i = 0; i < num_online_cpus(); i++) {
1300 if ((smtc_status & SMTC_TLB_SHARED) ||
1301 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1302 cpu_context(i, mm) = asid_cache(i) = asid;
1305 if (smtc_status & SMTC_TLB_SHARED)
1309 local_irq_restore(flags);
1313 * Invoked from macros defined in mmu_context.h
1314 * which must already have disabled interrupts
1315 * and done a DVPE or DMT as appropriate.
1318 void smtc_flush_tlb_asid(unsigned long asid)
1323 entry = read_c0_wired();
1325 /* Traverse all non-wired entries */
1326 while (entry < current_cpu_data.tlbsize) {
1327 write_c0_index(entry);
1331 ehi = read_c0_entryhi();
1332 if ((ehi & ASID_MASK) == asid) {
1334 * Invalidate only entries with specified ASID,
1335 * makiing sure all entries differ.
1337 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
1338 write_c0_entrylo0(0);
1339 write_c0_entrylo1(0);
1341 tlb_write_indexed();
1345 write_c0_index(PARKED_INDEX);
1350 * Support for single-threading cache flush operations.
1353 static int halt_state_save[NR_CPUS];
1356 * To really, really be sure that nothing is being done
1357 * by other TCs, halt them all. This code assumes that
1358 * a DVPE has already been done, so while their Halted
1359 * state is theoretically architecturally unstable, in
1360 * practice, it's not going to change while we're looking
1364 void smtc_cflush_lockdown(void)
1368 for_each_online_cpu(cpu) {
1369 if (cpu != smp_processor_id()) {
1370 settc(cpu_data[cpu].tc_id);
1371 halt_state_save[cpu] = read_tc_c0_tchalt();
1372 write_tc_c0_tchalt(TCHALT_H);
1378 /* It would be cheating to change the cpu_online states during a flush! */
1380 void smtc_cflush_release(void)
1385 * Start with a hazard barrier to ensure
1386 * that all CACHE ops have played through.
1390 for_each_online_cpu(cpu) {
1391 if (cpu != smp_processor_id()) {
1392 settc(cpu_data[cpu].tc_id);
1393 write_tc_c0_tchalt(halt_state_save[cpu]);