2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/mv643xx.h>
16 #include <linux/sched.h>
20 #include <asm/marvell.h>
22 static unsigned int irq_base;
24 static inline int ls1bit32(unsigned int x)
28 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
29 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
30 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
31 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
32 s = 1; if (x << 1 == 0) s = 0; b -= s;
37 /* mask off an interrupt -- 1 is enable, 0 is disable */
38 static inline void mask_mv64340_irq(unsigned int irq)
42 if (irq < (irq_base + 32)) {
43 value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
44 value &= ~(1 << (irq - irq_base));
45 MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
47 value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
48 value &= ~(1 << (irq - irq_base - 32));
49 MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
53 /* unmask an interrupt -- 1 is enable, 0 is disable */
54 static inline void unmask_mv64340_irq(unsigned int irq)
58 if (irq < (irq_base + 32)) {
59 value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
60 value |= 1 << (irq - irq_base);
61 MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
63 value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
64 value |= 1 << (irq - irq_base - 32);
65 MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
70 * Enables the IRQ on Marvell Chip
72 static void enable_mv64340_irq(unsigned int irq)
74 unmask_mv64340_irq(irq);
78 * Initialize the IRQ on Marvell Chip
80 static unsigned int startup_mv64340_irq(unsigned int irq)
82 unmask_mv64340_irq(irq);
87 * Disables the IRQ on Marvell Chip
89 static void disable_mv64340_irq(unsigned int irq)
91 mask_mv64340_irq(irq);
95 * Masks and ACKs an IRQ
97 static void mask_and_ack_mv64340_irq(unsigned int irq)
99 mask_mv64340_irq(irq);
105 static void end_mv64340_irq(unsigned int irq)
107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
108 unmask_mv64340_irq(irq);
112 * Interrupt handler for interrupts coming from the Marvell chip.
113 * It could be built in ethernet ports etc...
115 void ll_mv64340_irq(void)
117 unsigned int irq_src_low, irq_src_high;
118 unsigned int irq_mask_low, irq_mask_high;
120 /* read the interrupt status registers */
121 irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
122 irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
123 irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW);
124 irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH);
126 /* mask for just the interrupts we want */
127 irq_src_low &= irq_mask_low;
128 irq_src_high &= irq_mask_high;
131 do_IRQ(ls1bit32(irq_src_low) + irq_base);
133 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
136 #define shutdown_mv64340_irq disable_mv64340_irq
138 struct irq_chip mv64340_irq_type = {
139 .typename = "MV-64340",
140 .startup = startup_mv64340_irq,
141 .shutdown = shutdown_mv64340_irq,
142 .enable = enable_mv64340_irq,
143 .disable = disable_mv64340_irq,
144 .ack = mask_and_ack_mv64340_irq,
145 .end = end_mv64340_irq,
148 void __init mv64340_irq_init(unsigned int base)
152 /* Reset irq handlers pointers to NULL */
153 for (i = base; i < base + 64; i++) {
154 irq_desc[i].status = IRQ_DISABLED;
155 irq_desc[i].action = 0;
156 irq_desc[i].depth = 2;
157 irq_desc[i].chip = &mv64340_irq_type;