2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com
10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
19 #include <asm/msc01_ic.h>
21 static unsigned long _icctrl_msc;
22 #define MSC01_IC_REG_BASE _icctrl_msc
24 #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
25 #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
27 static unsigned int irq_base;
29 /* mask off an interrupt */
30 static inline void mask_msc_irq(unsigned int irq)
32 if (irq < (irq_base + 32))
33 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
35 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
38 /* unmask an interrupt */
39 static inline void unmask_msc_irq(unsigned int irq)
41 if (irq < (irq_base + 32))
42 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
44 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
48 * Masks and ACKs an IRQ
50 static void level_mask_and_ack_msc_irq(unsigned int irq)
54 MSCIC_WRITE(MSC01_IC_EOI, 0);
55 #ifdef CONFIG_MIPS_MT_SMTC
56 /* This actually needs to be a call into platform code */
57 if (irq_hwmask[irq] & ST0_IM)
58 set_c0_status(irq_hwmask[irq] & ST0_IM);
59 #endif /* CONFIG_MIPS_MT_SMTC */
63 * Masks and ACKs an IRQ
65 static void edge_mask_and_ack_msc_irq(unsigned int irq)
69 MSCIC_WRITE(MSC01_IC_EOI, 0);
72 MSCIC_READ(MSC01_IC_SUP+irq*8, r);
73 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
74 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
76 #ifdef CONFIG_MIPS_MT_SMTC
77 if (irq_hwmask[irq] & ST0_IM)
78 set_c0_status(irq_hwmask[irq] & ST0_IM);
79 #endif /* CONFIG_MIPS_MT_SMTC */
85 static void end_msc_irq(unsigned int irq)
87 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
92 * Interrupt handler for interrupts coming from SOC-it.
98 /* read the interrupt vector register */
99 MSCIC_READ(MSC01_IC_VEC, irq);
101 do_IRQ(irq + irq_base);
103 /* Ignore spurious interrupt */
108 msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
110 MSCIC_WRITE(MSC01_IC_RAMW,
111 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
114 struct irq_chip msc_levelirq_type = {
115 .typename = "SOC-it-Level",
116 .ack = level_mask_and_ack_msc_irq,
117 .mask = mask_msc_irq,
118 .mask_ack = level_mask_and_ack_msc_irq,
119 .unmask = unmask_msc_irq,
123 struct irq_chip msc_edgeirq_type = {
124 .typename = "SOC-it-Edge",
125 .ack = edge_mask_and_ack_msc_irq,
126 .mask = mask_msc_irq,
127 .mask_ack = edge_mask_and_ack_msc_irq,
128 .unmask = unmask_msc_irq,
133 void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
135 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
137 _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000);
139 /* Reset interrupt controller - initialises all registers to 0 */
140 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
142 board_bind_eic_interrupt = &msc_bind_eic_interrupt;
144 for (; nirq >= 0; nirq--, imp++) {
147 switch (imp->im_type) {
149 set_irq_chip(base+n, &msc_edgeirq_type);
151 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
155 case MSC01_IRQ_LEVEL:
156 set_irq_chip(base+n, &msc_levelirq_type);
158 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
160 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
166 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */