2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Code to handle x86 style IRQs plus some generic interrupt stuff.
8 * Copyright (C) 1992 Linus Torvalds
9 * Copyright (C) 1994 - 2000 Ralf Baechle
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/spinlock.h>
17 #include <linux/sysdev.h>
19 #include <asm/i8259.h>
23 * This is the 'legacy' 8259A Programmable Interrupt Controller,
24 * present in the majority of PC/AT boxes.
25 * plus some generic x86 specific things if generic specifics makes
27 * this file should become arch/i386/kernel/irq.c when the old irq.c
28 * moves to arch independent land
31 static int i8259A_auto_eoi = -1;
32 DEFINE_SPINLOCK(i8259A_lock);
33 /* some platforms call this... */
34 void mask_and_ack_8259A(unsigned int);
36 static struct irq_chip i8259A_chip = {
38 .mask = disable_8259A_irq,
39 .disable = disable_8259A_irq,
40 .unmask = enable_8259A_irq,
41 .mask_ack = mask_and_ack_8259A,
42 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
43 .set_affinity = plat_set_irq_affinity,
44 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
48 * 8259A PIC functions to handle ISA devices:
52 * This contains the irq mask for both 8259A irq controllers,
54 static unsigned int cached_irq_mask = 0xffff;
56 #define cached_master_mask (cached_irq_mask)
57 #define cached_slave_mask (cached_irq_mask >> 8)
59 void disable_8259A_irq(unsigned int irq)
64 irq -= I8259A_IRQ_BASE;
66 spin_lock_irqsave(&i8259A_lock, flags);
67 cached_irq_mask |= mask;
69 outb(cached_slave_mask, PIC_SLAVE_IMR);
71 outb(cached_master_mask, PIC_MASTER_IMR);
72 spin_unlock_irqrestore(&i8259A_lock, flags);
75 void enable_8259A_irq(unsigned int irq)
80 irq -= I8259A_IRQ_BASE;
82 spin_lock_irqsave(&i8259A_lock, flags);
83 cached_irq_mask &= mask;
85 outb(cached_slave_mask, PIC_SLAVE_IMR);
87 outb(cached_master_mask, PIC_MASTER_IMR);
88 spin_unlock_irqrestore(&i8259A_lock, flags);
91 int i8259A_irq_pending(unsigned int irq)
97 irq -= I8259A_IRQ_BASE;
99 spin_lock_irqsave(&i8259A_lock, flags);
101 ret = inb(PIC_MASTER_CMD) & mask;
103 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
104 spin_unlock_irqrestore(&i8259A_lock, flags);
109 void make_8259A_irq(unsigned int irq)
111 disable_irq_nosync(irq);
112 set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
117 * This function assumes to be called rarely. Switching between
118 * 8259A registers is slow.
119 * This has to be protected by the irq controller spinlock
120 * before being called.
122 static inline int i8259A_irq_real(unsigned int irq)
125 int irqmask = 1 << irq;
128 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
129 value = inb(PIC_MASTER_CMD) & irqmask;
130 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
133 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
134 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
135 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
140 * Careful! The 8259A is a fragile beast, it pretty
141 * much _has_ to be done exactly like this (mask it
142 * first, _then_ send the EOI, and the order of EOI
143 * to the two 8259s is important!
145 void mask_and_ack_8259A(unsigned int irq)
147 unsigned int irqmask;
150 irq -= I8259A_IRQ_BASE;
152 spin_lock_irqsave(&i8259A_lock, flags);
154 * Lightweight spurious IRQ detection. We do not want
155 * to overdo spurious IRQ handling - it's usually a sign
156 * of hardware problems, so we only do the checks we can
157 * do without slowing down good hardware unnecessarily.
159 * Note that IRQ7 and IRQ15 (the two spurious IRQs
160 * usually resulting from the 8259A-1|2 PICs) occur
161 * even if the IRQ is masked in the 8259A. Thus we
162 * can check spurious 8259A IRQs without doing the
163 * quite slow i8259A_irq_real() call for every IRQ.
164 * This does not cover 100% of spurious interrupts,
165 * but should be enough to warn the user that there
166 * is something bad going on ...
168 if (cached_irq_mask & irqmask)
169 goto spurious_8259A_irq;
170 cached_irq_mask |= irqmask;
174 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
175 outb(cached_slave_mask, PIC_SLAVE_IMR);
176 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
177 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
179 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
180 outb(cached_master_mask, PIC_MASTER_IMR);
181 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
183 smtc_im_ack_irq(irq);
184 spin_unlock_irqrestore(&i8259A_lock, flags);
189 * this is the slow path - should happen rarely.
191 if (i8259A_irq_real(irq))
193 * oops, the IRQ _is_ in service according to the
194 * 8259A - not spurious, go handle it.
196 goto handle_real_irq;
199 static int spurious_irq_mask;
201 * At this point we can be sure the IRQ is spurious,
202 * lets ACK and report it. [once per IRQ]
204 if (!(spurious_irq_mask & irqmask)) {
205 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
206 spurious_irq_mask |= irqmask;
208 atomic_inc(&irq_err_count);
210 * Theoretically we do not have to handle this IRQ,
211 * but in Linux this does not cause problems and is
214 goto handle_real_irq;
218 static int i8259A_resume(struct sys_device *dev)
220 if (i8259A_auto_eoi >= 0)
221 init_8259A(i8259A_auto_eoi);
225 static int i8259A_shutdown(struct sys_device *dev)
227 /* Put the i8259A into a quiescent state that
228 * the kernel initialization code can get it
231 if (i8259A_auto_eoi >= 0) {
232 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
233 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
238 static struct sysdev_class i8259_sysdev_class = {
239 set_kset_name("i8259"),
240 .resume = i8259A_resume,
241 .shutdown = i8259A_shutdown,
244 static struct sys_device device_i8259A = {
246 .cls = &i8259_sysdev_class,
249 static int __init i8259A_init_sysfs(void)
251 int error = sysdev_class_register(&i8259_sysdev_class);
253 error = sysdev_register(&device_i8259A);
257 device_initcall(i8259A_init_sysfs);
259 void init_8259A(int auto_eoi)
263 i8259A_auto_eoi = auto_eoi;
265 spin_lock_irqsave(&i8259A_lock, flags);
267 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
268 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
271 * outb_p - this has to work on a wide range of PC hardware.
273 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
274 outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
275 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
276 if (auto_eoi) /* master does Auto EOI */
277 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
278 else /* master expects normal EOI */
279 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
281 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
282 outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
283 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
284 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
287 * In AEOI mode we just have to mask the interrupt
290 i8259A_chip.mask_ack = disable_8259A_irq;
292 i8259A_chip.mask_ack = mask_and_ack_8259A;
294 udelay(100); /* wait for 8259A to initialize */
296 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
297 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
299 spin_unlock_irqrestore(&i8259A_lock, flags);
303 * IRQ2 is cascade interrupt to second interrupt controller
305 static struct irqaction irq2 = {
306 .handler = no_action,
307 .mask = CPU_MASK_NONE,
311 static struct resource pic1_io_resource = {
313 .start = PIC_MASTER_CMD,
314 .end = PIC_MASTER_IMR,
315 .flags = IORESOURCE_BUSY
318 static struct resource pic2_io_resource = {
320 .start = PIC_SLAVE_CMD,
321 .end = PIC_SLAVE_IMR,
322 .flags = IORESOURCE_BUSY
326 * On systems with i8259-style interrupt controllers we assume for
327 * driver compatibility reasons interrupts 0 - 15 to be the i8259
328 * interrupts even if the hardware uses a different interrupt numbering.
330 void __init init_i8259_irqs (void)
334 insert_resource(&ioport_resource, &pic1_io_resource);
335 insert_resource(&ioport_resource, &pic2_io_resource);
339 for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++)
340 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
342 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);