err.no Git - linux-2.6/blob - arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   6  * Copyright (C) 1994 - 2003 Ralf Baechle
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/stddef.h>
  19
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | TX39_CONF_HALT);
  44 }
  45
  46 static void r4k_wait(void)
  47 {
  48         __asm__(".set\tmips3\n\t"
  49                 "wait\n\t"
  50                 ".set\tmips0");
  51 }
  52
  53 /* The Au1xxx wait is available only if using 32khz counter or
  54  * external timer source, but specifically not CP0 Counter. */
  55 int allow_au1k_wait;
  56 static void au1k_wait(void)
  57 {
  58         unsigned long addr = 0;
  59         /* using the wait instruction makes CP0 counter unusable */
  60         __asm__("la %0,au1k_wait\n\t"
  61                 ".set mips3\n\t"
  62                 "cache 0x14,0(%0)\n\t"
  63                 "cache 0x14,32(%0)\n\t"
  64                 "sync\n\t"
  65                 "nop\n\t"
  66                 "wait\n\t"
  67                 "nop\n\t"
  68                 "nop\n\t"
  69                 "nop\n\t"
  70                 "nop\n\t"
  71                 ".set mips0\n\t"
  72                 : : "r" (addr));
  73 }
  74
  75 static inline void check_wait(void)
  76 {
  77         struct cpuinfo_mips *c = &current_cpu_data;
  78
  79         printk("Checking for 'wait' instruction... ");
  80         switch (c->cputype) {
  81         case CPU_R3081:
  82         case CPU_R3081E:
  83                 cpu_wait = r3081_wait;
  84                 printk(" available.\n");
  85                 break;
  86         case CPU_TX3927:
  87                 cpu_wait = r39xx_wait;
  88                 printk(" available.\n");
  89                 break;
  90         case CPU_R4200:
  91 /*      case CPU_R4300: */
  92         case CPU_R4600:
  93         case CPU_R4640:
  94         case CPU_R4650:
  95         case CPU_R4700:
  96         case CPU_R5000:
  97         case CPU_NEVADA:
  98         case CPU_RM7000:
  99         case CPU_RM9000:
 100         case CPU_TX49XX:
 101         case CPU_4KC:
 102         case CPU_4KEC:
 103         case CPU_4KSC:
 104         case CPU_5KC:
 105 /*      case CPU_20KC:*/
 106         case CPU_24K:
 107         case CPU_25KF:
 108                 cpu_wait = r4k_wait;
 109                 printk(" available.\n");
 110                 break;
 111         case CPU_AU1000:
 112         case CPU_AU1100:
 113         case CPU_AU1500:
 114         case CPU_AU1550:
 115         case CPU_AU1200:
 116                 if (allow_au1k_wait) {
 117                         cpu_wait = au1k_wait;
 118                         printk(" available.\n");
 119                 } else
 120                         printk(" unavailable.\n");
 121                 break;
 122         default:
 123                 printk(" unavailable.\n");
 124                 break;
 125         }
 126 }
 127
 128 void __init check_bugs32(void)
 129 {
 130         check_wait();
 131 }
 132
 133 /*
 134  * Probe whether cpu has config register by trying to play with
 135  * alternate cache bit and see whether it matters.
 136  * It's used by cpu_probe to distinguish between R3000A and R3081.
 137  */
 138 static inline int cpu_has_confreg(void)
 139 {
 140 #ifdef CONFIG_CPU_R3000
 141         extern unsigned long r3k_cache_size(unsigned long);
 142         unsigned long size1, size2;
 143         unsigned long cfg = read_c0_conf();
 144
 145         size1 = r3k_cache_size(ST0_ISC);
 146         write_c0_conf(cfg ^ R30XX_CONF_AC);
 147         size2 = r3k_cache_size(ST0_ISC);
 148         write_c0_conf(cfg);
 149         return size1 != size2;
 150 #else
 151         return 0;
 152 #endif
 153 }
 154
 155 /*
 156  * Get the FPU Implementation/Revision.
 157  */
 158 static inline unsigned long cpu_get_fpu_id(void)
 159 {
 160         unsigned long tmp, fpu_id;
 161
 162         tmp = read_c0_status();
 163         __enable_fpu();
 164         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 165         write_c0_status(tmp);
 166         return fpu_id;
 167 }
 168
 169 /*
 170  * Check the CPU has an FPU the official way.
 171  */
 172 static inline int __cpu_has_fpu(void)
 173 {
 174         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 175 }
 176
 177 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
 178                 | MIPS_CPU_COUNTER)
 179
 180 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 181 {
 182         switch (c->processor_id & 0xff00) {
 183         case PRID_IMP_R2000:
 184                 c->cputype = CPU_R2000;
 185                 c->isa_level = MIPS_CPU_ISA_I;
 186                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 187                 if (__cpu_has_fpu())
 188                         c->options |= MIPS_CPU_FPU;
 189                 c->tlbsize = 64;
 190                 break;
 191         case PRID_IMP_R3000:
 192                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 193                         if (cpu_has_confreg())
 194                                 c->cputype = CPU_R3081E;
 195                         else
 196                                 c->cputype = CPU_R3000A;
 197                 else
 198                         c->cputype = CPU_R3000;
 199                 c->isa_level = MIPS_CPU_ISA_I;
 200                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 201                 if (__cpu_has_fpu())
 202                         c->options |= MIPS_CPU_FPU;
 203                 c->tlbsize = 64;
 204                 break;
 205         case PRID_IMP_R4000:
 206                 if (read_c0_config() & CONF_SC) {
 207                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 208                                 c->cputype = CPU_R4400PC;
 209                         else
 210                                 c->cputype = CPU_R4000PC;
 211                 } else {
 212                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 213                                 c->cputype = CPU_R4400SC;
 214                         else
 215                                 c->cputype = CPU_R4000SC;
 216                 }
 217
 218                 c->isa_level = MIPS_CPU_ISA_III;
 219                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 220                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 221                              MIPS_CPU_LLSC;
 222                 c->tlbsize = 48;
 223                 break;
 224         case PRID_IMP_VR41XX:
 225                 switch (c->processor_id & 0xf0) {
 226                 case PRID_REV_VR4111:
 227                         c->cputype = CPU_VR4111;
 228                         break;
 229                 case PRID_REV_VR4121:
 230                         c->cputype = CPU_VR4121;
 231                         break;
 232                 case PRID_REV_VR4122:
 233                         if ((c->processor_id & 0xf) < 0x3)
 234                                 c->cputype = CPU_VR4122;
 235                         else
 236                                 c->cputype = CPU_VR4181A;
 237                         break;
 238                 case PRID_REV_VR4130:
 239                         if ((c->processor_id & 0xf) < 0x4)
 240                                 c->cputype = CPU_VR4131;
 241                         else
 242                                 c->cputype = CPU_VR4133;
 243                         break;
 244                 default:
 245                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 246                         c->cputype = CPU_VR41XX;
 247                         break;
 248                 }
 249                 c->isa_level = MIPS_CPU_ISA_III;
 250                 c->options = R4K_OPTS;
 251                 c->tlbsize = 32;
 252                 break;
 253         case PRID_IMP_R4300:
 254                 c->cputype = CPU_R4300;
 255                 c->isa_level = MIPS_CPU_ISA_III;
 256                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 257                              MIPS_CPU_LLSC;
 258                 c->tlbsize = 32;
 259                 break;
 260         case PRID_IMP_R4600:
 261                 c->cputype = CPU_R4600;
 262                 c->isa_level = MIPS_CPU_ISA_III;
 263                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 264                 c->tlbsize = 48;
 265                 break;
 266         #if 0
 267         case PRID_IMP_R4650:
 268                 /*
 269                  * This processor doesn't have an MMU, so it's not
 270                  * "real easy" to run Linux on it. It is left purely
 271                  * for documentation.  Commented out because it shares
 272                  * it's c0_prid id number with the TX3900.
 273                  */
 274                 c->cputype = CPU_R4650;
 275                 c->isa_level = MIPS_CPU_ISA_III;
 276                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 277                 c->tlbsize = 48;
 278                 break;
 279         #endif
 280         case PRID_IMP_TX39:
 281                 c->isa_level = MIPS_CPU_ISA_I;
 282                 c->options = MIPS_CPU_TLB;
 283
 284                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 285                         c->cputype = CPU_TX3927;
 286                         c->tlbsize = 64;
 287                 } else {
 288                         switch (c->processor_id & 0xff) {
 289                         case PRID_REV_TX3912:
 290                                 c->cputype = CPU_TX3912;
 291                                 c->tlbsize = 32;
 292                                 break;
 293                         case PRID_REV_TX3922:
 294                                 c->cputype = CPU_TX3922;
 295                                 c->tlbsize = 64;
 296                                 break;
 297                         default:
 298                                 c->cputype = CPU_UNKNOWN;
 299                                 break;
 300                         }
 301                 }
 302                 break;
 303         case PRID_IMP_R4700:
 304                 c->cputype = CPU_R4700;
 305                 c->isa_level = MIPS_CPU_ISA_III;
 306                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 307                              MIPS_CPU_LLSC;
 308                 c->tlbsize = 48;
 309                 break;
 310         case PRID_IMP_TX49:
 311                 c->cputype = CPU_TX49XX;
 312                 c->isa_level = MIPS_CPU_ISA_III;
 313                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 314                 if (!(c->processor_id & 0x08))
 315                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 316                 c->tlbsize = 48;
 317                 break;
 318         case PRID_IMP_R5000:
 319                 c->cputype = CPU_R5000;
 320                 c->isa_level = MIPS_CPU_ISA_IV;
 321                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 322                              MIPS_CPU_LLSC;
 323                 c->tlbsize = 48;
 324                 break;
 325         case PRID_IMP_R5432:
 326                 c->cputype = CPU_R5432;
 327                 c->isa_level = MIPS_CPU_ISA_IV;
 328                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 329                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 330                 c->tlbsize = 48;
 331                 break;
 332         case PRID_IMP_R5500:
 333                 c->cputype = CPU_R5500;
 334                 c->isa_level = MIPS_CPU_ISA_IV;
 335                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 336                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 337                 c->tlbsize = 48;
 338                 break;
 339         case PRID_IMP_NEVADA:
 340                 c->cputype = CPU_NEVADA;
 341                 c->isa_level = MIPS_CPU_ISA_IV;
 342                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 343                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 344                 c->tlbsize = 48;
 345                 break;
 346         case PRID_IMP_R6000:
 347                 c->cputype = CPU_R6000;
 348                 c->isa_level = MIPS_CPU_ISA_II;
 349                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 350                              MIPS_CPU_LLSC;
 351                 c->tlbsize = 32;
 352                 break;
 353         case PRID_IMP_R6000A:
 354                 c->cputype = CPU_R6000A;
 355                 c->isa_level = MIPS_CPU_ISA_II;
 356                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 357                              MIPS_CPU_LLSC;
 358                 c->tlbsize = 32;
 359                 break;
 360         case PRID_IMP_RM7000:
 361                 c->cputype = CPU_RM7000;
 362                 c->isa_level = MIPS_CPU_ISA_IV;
 363                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 364                              MIPS_CPU_LLSC;
 365                 /*
 366                  * Undocumented RM7000:  Bit 29 in the info register of
 367                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 368                  * entries.
 369                  *
 370                  * 29      1 =>    64 entry JTLB
 371                  *         0 =>    48 entry JTLB
 372                  */
 373                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 374                 break;
 375         case PRID_IMP_RM9000:
 376                 c->cputype = CPU_RM9000;
 377                 c->isa_level = MIPS_CPU_ISA_IV;
 378                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 379                              MIPS_CPU_LLSC;
 380                 /*
 381                  * Bit 29 in the info register of the RM9000
 382                  * indicates if the TLB has 48 or 64 entries.
 383                  *
 384                  * 29      1 =>    64 entry JTLB
 385                  *         0 =>    48 entry JTLB
 386                  */
 387                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 388                 break;
 389         case PRID_IMP_R8000:
 390                 c->cputype = CPU_R8000;
 391                 c->isa_level = MIPS_CPU_ISA_IV;
 392                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 393                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 394                              MIPS_CPU_LLSC;
 395                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 396                 break;
 397         case PRID_IMP_R10000:
 398                 c->cputype = CPU_R10000;
 399                 c->isa_level = MIPS_CPU_ISA_IV;
 400                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 401                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 402                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 403                              MIPS_CPU_LLSC;
 404                 c->tlbsize = 64;
 405                 break;
 406         case PRID_IMP_R12000:
 407                 c->cputype = CPU_R12000;
 408                 c->isa_level = MIPS_CPU_ISA_IV;
 409                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 410                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 411                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 412                              MIPS_CPU_LLSC;
 413                 c->tlbsize = 64;
 414                 break;
 415         }
 416 }
 417
 418 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 419 {
 420         unsigned int config0;
 421         int isa;
 422
 423         config0 = read_c0_config();
 424
 425         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 426                 c->options |= MIPS_CPU_TLB;
 427         isa = (config0 & MIPS_CONF_AT) >> 13;
 428         switch (isa) {
 429         case 0:
 430                 c->isa_level = MIPS_CPU_ISA_M32;
 431                 break;
 432         case 2:
 433                 c->isa_level = MIPS_CPU_ISA_M64;
 434                 break;
 435         default:
 436                 panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
 437         }
 438
 439         return config0 & MIPS_CONF_M;
 440 }
 441
 442 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 443 {
 444         unsigned int config1;
 445
 446         config1 = read_c0_config1();
 447
 448         if (config1 & MIPS_CONF1_MD)
 449                 c->ases |= MIPS_ASE_MDMX;
 450         if (config1 & MIPS_CONF1_WR)
 451                 c->options |= MIPS_CPU_WATCH;
 452         if (config1 & MIPS_CONF1_CA)
 453                 c->ases |= MIPS_ASE_MIPS16;
 454         if (config1 & MIPS_CONF1_EP)
 455                 c->options |= MIPS_CPU_EJTAG;
 456         if (config1 & MIPS_CONF1_FP) {
 457                 c->options |= MIPS_CPU_FPU;
 458                 c->options |= MIPS_CPU_32FPR;
 459         }
 460         if (cpu_has_tlb)
 461                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 462
 463         return config1 & MIPS_CONF_M;
 464 }
 465
 466 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 467 {
 468         unsigned int config2;
 469
 470         config2 = read_c0_config2();
 471
 472         if (config2 & MIPS_CONF2_SL)
 473                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 474
 475         return config2 & MIPS_CONF_M;
 476 }
 477
 478 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 479 {
 480         unsigned int config3;
 481
 482         config3 = read_c0_config3();
 483
 484         if (config3 & MIPS_CONF3_SM)
 485                 c->ases |= MIPS_ASE_SMARTMIPS;
 486
 487         return config3 & MIPS_CONF_M;
 488 }
 489
 490 static inline void decode_configs(struct cpuinfo_mips *c)
 491 {
 492         /* MIPS32 or MIPS64 compliant CPU.  */
 493         c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 494                      MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 495
 496         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 497
 498         /* Read Config registers.  */
 499         if (!decode_config0(c))
 500                 return;                 /* actually worth a panic() */
 501         if (!decode_config1(c))
 502                 return;
 503         if (!decode_config2(c))
 504                 return;
 505         if (!decode_config3(c))
 506                 return;
 507 }
 508
 509 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 510 {
 511         decode_configs(c);
 512         if (cpu_has_tlb)
 513                 c->options |= MIPS_CPU_4KTLB;
 514         switch (c->processor_id & 0xff00) {
 515         case PRID_IMP_4KC:
 516                 c->cputype = CPU_4KC;
 517                 break;
 518         case PRID_IMP_4KEC:
 519                 c->cputype = CPU_4KEC;
 520                 break;
 521         case PRID_IMP_4KECR2:
 522                 c->cputype = CPU_4KEC;
 523                 break;
 524         case PRID_IMP_4KSC:
 525                 c->cputype = CPU_4KSC;
 526                 break;
 527         case PRID_IMP_5KC:
 528                 c->cputype = CPU_5KC;
 529                 break;
 530         case PRID_IMP_20KC:
 531                 c->cputype = CPU_20KC;
 532                 break;
 533         case PRID_IMP_24K:
 534                 c->cputype = CPU_24K;
 535                 break;
 536         case PRID_IMP_25KF:
 537                 c->cputype = CPU_25KF;
 538                 /* Probe for L2 cache */
 539                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 540                 break;
 541         }
 542 }
 543
 544 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 545 {
 546         decode_configs(c);
 547         switch (c->processor_id & 0xff00) {
 548         case PRID_IMP_AU1_REV1:
 549         case PRID_IMP_AU1_REV2:
 550                 switch ((c->processor_id >> 24) & 0xff) {
 551                 case 0:
 552                         c->cputype = CPU_AU1000;
 553                         break;
 554                 case 1:
 555                         c->cputype = CPU_AU1500;
 556                         break;
 557                 case 2:
 558                         c->cputype = CPU_AU1100;
 559                         break;
 560                 case 3:
 561                         c->cputype = CPU_AU1550;
 562                         break;
 563                 case 4:
 564                         c->cputype = CPU_AU1200;
 565                         break;
 566                 default:
 567                         panic("Unknown Au Core!");
 568                         break;
 569                 }
 570                 break;
 571         }
 572 }
 573
 574 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 575 {
 576         decode_configs(c);
 577         switch (c->processor_id & 0xff00) {
 578         case PRID_IMP_SB1:
 579                 c->cputype = CPU_SB1;
 580 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 581                 /* FPU in pass1 is known to have issues. */
 582                 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 583 #endif
 584                 break;
 585         }
 586 }
 587
 588 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 589 {
 590         decode_configs(c);
 591         if (cpu_has_tlb)
 592                 c->options |= MIPS_CPU_4KTLB;
 593         switch (c->processor_id & 0xff00) {
 594         case PRID_IMP_SR71000:
 595                 c->cputype = CPU_SR71000;
 596                 c->scache.ways = 8;
 597                 c->tlbsize = 64;
 598                 break;
 599         }
 600 }
 601
 602 __init void cpu_probe(void)
 603 {
 604         struct cpuinfo_mips *c = &current_cpu_data;
 605
 606         c->processor_id = PRID_IMP_UNKNOWN;
 607         c->fpu_id       = FPIR_IMP_NONE;
 608         c->cputype      = CPU_UNKNOWN;
 609
 610         c->processor_id = read_c0_prid();
 611         switch (c->processor_id & 0xff0000) {
 612         case PRID_COMP_LEGACY:
 613                 cpu_probe_legacy(c);
 614                 break;
 615         case PRID_COMP_MIPS:
 616                 cpu_probe_mips(c);
 617                 break;
 618         case PRID_COMP_ALCHEMY:
 619                 cpu_probe_alchemy(c);
 620                 break;
 621         case PRID_COMP_SIBYTE:
 622                 cpu_probe_sibyte(c);
 623                 break;
 624         case PRID_COMP_SANDCRAFT:
 625                 cpu_probe_sandcraft(c);
 626                 break;
 627         default:
 628                 c->cputype = CPU_UNKNOWN;
 629         }
 630         if (c->options & MIPS_CPU_FPU) {
 631                 c->fpu_id = cpu_get_fpu_id();
 632
 633                 if (c->isa_level == MIPS_CPU_ISA_M32 ||
 634                     c->isa_level == MIPS_CPU_ISA_M64) {
 635                         if (c->fpu_id & MIPS_FPIR_3D)
 636                                 c->ases |= MIPS_ASE_MIPS3D;
 637                 }
 638         }
 639 }
 640
 641 __init void cpu_report(void)
 642 {
 643         struct cpuinfo_mips *c = &current_cpu_data;
 644
 645         printk("CPU revision is: %08x\n", c->processor_id);
 646         if (c->options & MIPS_CPU_FPU)
 647                 printk("FPU revision is: %08x\n", c->fpu_id);
 648 }