2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
23 #include <asm/mipsregs.h>
24 #include <asm/system.h>
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
33 void (*cpu_wait)(void) = NULL;
35 static void r3081_wait(void)
37 unsigned long cfg = read_c0_conf();
38 write_c0_conf(cfg | R30XX_CONF_HALT);
41 static void r39xx_wait(void)
43 unsigned long cfg = read_c0_conf();
44 write_c0_conf(cfg | TX39_CONF_HALT);
47 static void r4k_wait(void)
49 __asm__(".set\tmips3\n\t"
54 /* The Au1xxx wait is available only if using 32khz counter or
55 * external timer source, but specifically not CP0 Counter. */
57 static void au1k_wait(void)
59 unsigned long addr = 0;
60 /* using the wait instruction makes CP0 counter unusable */
61 __asm__("la %0,au1k_wait\n\t"
63 "cache 0x14,0(%0)\n\t"
64 "cache 0x14,32(%0)\n\t"
76 static inline void check_wait(void)
78 struct cpuinfo_mips *c = ¤t_cpu_data;
80 printk("Checking for 'wait' instruction... ");
84 cpu_wait = r3081_wait;
85 printk(" available.\n");
88 cpu_wait = r39xx_wait;
89 printk(" available.\n");
110 printk(" available.\n");
117 if (allow_au1k_wait) {
118 cpu_wait = au1k_wait;
119 printk(" available.\n");
121 printk(" unavailable.\n");
124 printk(" unavailable.\n");
129 void __init check_bugs32(void)
135 * Probe whether cpu has config register by trying to play with
136 * alternate cache bit and see whether it matters.
137 * It's used by cpu_probe to distinguish between R3000A and R3081.
139 static inline int cpu_has_confreg(void)
141 #ifdef CONFIG_CPU_R3000
142 extern unsigned long r3k_cache_size(unsigned long);
143 unsigned long size1, size2;
144 unsigned long cfg = read_c0_conf();
146 size1 = r3k_cache_size(ST0_ISC);
147 write_c0_conf(cfg ^ R30XX_CONF_AC);
148 size2 = r3k_cache_size(ST0_ISC);
150 return size1 != size2;
157 * Get the FPU Implementation/Revision.
159 static inline unsigned long cpu_get_fpu_id(void)
161 unsigned long tmp, fpu_id;
163 tmp = read_c0_status();
165 fpu_id = read_32bit_cp1_register(CP1_REVISION);
166 write_c0_status(tmp);
171 * Check the CPU has an FPU the official way.
173 static inline int __cpu_has_fpu(void)
175 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
178 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
181 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
183 switch (c->processor_id & 0xff00) {
185 c->cputype = CPU_R2000;
186 c->isa_level = MIPS_CPU_ISA_I;
187 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
189 c->options |= MIPS_CPU_FPU;
193 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
194 if (cpu_has_confreg())
195 c->cputype = CPU_R3081E;
197 c->cputype = CPU_R3000A;
199 c->cputype = CPU_R3000;
200 c->isa_level = MIPS_CPU_ISA_I;
201 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
203 c->options |= MIPS_CPU_FPU;
207 if (read_c0_config() & CONF_SC) {
208 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
209 c->cputype = CPU_R4400PC;
211 c->cputype = CPU_R4000PC;
213 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
214 c->cputype = CPU_R4400SC;
216 c->cputype = CPU_R4000SC;
219 c->isa_level = MIPS_CPU_ISA_III;
220 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
221 MIPS_CPU_WATCH | MIPS_CPU_VCE |
225 case PRID_IMP_VR41XX:
226 switch (c->processor_id & 0xf0) {
227 case PRID_REV_VR4111:
228 c->cputype = CPU_VR4111;
230 case PRID_REV_VR4121:
231 c->cputype = CPU_VR4121;
233 case PRID_REV_VR4122:
234 if ((c->processor_id & 0xf) < 0x3)
235 c->cputype = CPU_VR4122;
237 c->cputype = CPU_VR4181A;
239 case PRID_REV_VR4130:
240 if ((c->processor_id & 0xf) < 0x4)
241 c->cputype = CPU_VR4131;
243 c->cputype = CPU_VR4133;
246 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
247 c->cputype = CPU_VR41XX;
250 c->isa_level = MIPS_CPU_ISA_III;
251 c->options = R4K_OPTS;
255 c->cputype = CPU_R4300;
256 c->isa_level = MIPS_CPU_ISA_III;
257 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
262 c->cputype = CPU_R4600;
263 c->isa_level = MIPS_CPU_ISA_III;
264 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
270 * This processor doesn't have an MMU, so it's not
271 * "real easy" to run Linux on it. It is left purely
272 * for documentation. Commented out because it shares
273 * it's c0_prid id number with the TX3900.
275 c->cputype = CPU_R4650;
276 c->isa_level = MIPS_CPU_ISA_III;
277 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
282 c->isa_level = MIPS_CPU_ISA_I;
283 c->options = MIPS_CPU_TLB;
285 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
286 c->cputype = CPU_TX3927;
289 switch (c->processor_id & 0xff) {
290 case PRID_REV_TX3912:
291 c->cputype = CPU_TX3912;
294 case PRID_REV_TX3922:
295 c->cputype = CPU_TX3922;
299 c->cputype = CPU_UNKNOWN;
305 c->cputype = CPU_R4700;
306 c->isa_level = MIPS_CPU_ISA_III;
307 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
312 c->cputype = CPU_TX49XX;
313 c->isa_level = MIPS_CPU_ISA_III;
314 c->options = R4K_OPTS | MIPS_CPU_LLSC;
315 if (!(c->processor_id & 0x08))
316 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
320 c->cputype = CPU_R5000;
321 c->isa_level = MIPS_CPU_ISA_IV;
322 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
327 c->cputype = CPU_R5432;
328 c->isa_level = MIPS_CPU_ISA_IV;
329 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
330 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
334 c->cputype = CPU_R5500;
335 c->isa_level = MIPS_CPU_ISA_IV;
336 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
337 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
340 case PRID_IMP_NEVADA:
341 c->cputype = CPU_NEVADA;
342 c->isa_level = MIPS_CPU_ISA_IV;
343 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
344 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
348 c->cputype = CPU_R6000;
349 c->isa_level = MIPS_CPU_ISA_II;
350 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
354 case PRID_IMP_R6000A:
355 c->cputype = CPU_R6000A;
356 c->isa_level = MIPS_CPU_ISA_II;
357 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
361 case PRID_IMP_RM7000:
362 c->cputype = CPU_RM7000;
363 c->isa_level = MIPS_CPU_ISA_IV;
364 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
367 * Undocumented RM7000: Bit 29 in the info register of
368 * the RM7000 v2.0 indicates if the TLB has 48 or 64
371 * 29 1 => 64 entry JTLB
374 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
376 case PRID_IMP_RM9000:
377 c->cputype = CPU_RM9000;
378 c->isa_level = MIPS_CPU_ISA_IV;
379 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
382 * Bit 29 in the info register of the RM9000
383 * indicates if the TLB has 48 or 64 entries.
385 * 29 1 => 64 entry JTLB
388 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
391 c->cputype = CPU_R8000;
392 c->isa_level = MIPS_CPU_ISA_IV;
393 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
394 MIPS_CPU_FPU | MIPS_CPU_32FPR |
396 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
398 case PRID_IMP_R10000:
399 c->cputype = CPU_R10000;
400 c->isa_level = MIPS_CPU_ISA_IV;
401 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
402 MIPS_CPU_FPU | MIPS_CPU_32FPR |
403 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
407 case PRID_IMP_R12000:
408 c->cputype = CPU_R12000;
409 c->isa_level = MIPS_CPU_ISA_IV;
410 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
411 MIPS_CPU_FPU | MIPS_CPU_32FPR |
412 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
419 static inline void decode_config1(struct cpuinfo_mips *c)
421 unsigned long config0 = read_c0_config();
422 unsigned long config1;
424 if ((config0 & (1 << 31)) == 0)
425 return; /* actually wort a panic() */
427 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
428 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
429 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
430 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
431 config1 = read_c0_config1();
432 if (config1 & (1 << 3))
433 c->options |= MIPS_CPU_WATCH;
434 if (config1 & (1 << 2))
435 c->options |= MIPS_CPU_MIPS16;
436 if (config1 & (1 << 1))
437 c->options |= MIPS_CPU_EJTAG;
439 c->options |= MIPS_CPU_FPU;
440 c->options |= MIPS_CPU_32FPR;
442 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
444 c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
447 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
450 switch (c->processor_id & 0xff00) {
452 c->cputype = CPU_4KC;
453 c->isa_level = MIPS_CPU_ISA_M32;
456 c->cputype = CPU_4KEC;
457 c->isa_level = MIPS_CPU_ISA_M32;
459 case PRID_IMP_4KECR2:
460 c->cputype = CPU_4KEC;
461 c->isa_level = MIPS_CPU_ISA_M32;
464 c->cputype = CPU_4KSC;
465 c->isa_level = MIPS_CPU_ISA_M32;
468 c->cputype = CPU_5KC;
469 c->isa_level = MIPS_CPU_ISA_M64;
472 c->cputype = CPU_20KC;
473 c->isa_level = MIPS_CPU_ISA_M64;
476 c->cputype = CPU_24K;
477 c->isa_level = MIPS_CPU_ISA_M32;
480 c->cputype = CPU_25KF;
481 c->isa_level = MIPS_CPU_ISA_M64;
482 /* Probe for L2 cache */
483 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
488 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
491 switch (c->processor_id & 0xff00) {
492 case PRID_IMP_AU1_REV1:
493 case PRID_IMP_AU1_REV2:
494 switch ((c->processor_id >> 24) & 0xff) {
496 c->cputype = CPU_AU1000;
499 c->cputype = CPU_AU1500;
502 c->cputype = CPU_AU1100;
505 c->cputype = CPU_AU1550;
508 c->cputype = CPU_AU1200;
511 panic("Unknown Au Core!");
514 c->isa_level = MIPS_CPU_ISA_M32;
519 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
522 switch (c->processor_id & 0xff00) {
524 c->cputype = CPU_SB1;
525 c->isa_level = MIPS_CPU_ISA_M64;
526 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
527 MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
528 MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
529 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
530 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
531 /* FPU in pass1 is known to have issues. */
532 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
538 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
541 switch (c->processor_id & 0xff00) {
542 case PRID_IMP_SR71000:
543 c->cputype = CPU_SR71000;
544 c->isa_level = MIPS_CPU_ISA_M64;
545 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
546 MIPS_CPU_4KTLB | MIPS_CPU_FPU |
547 MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
554 __init void cpu_probe(void)
556 struct cpuinfo_mips *c = ¤t_cpu_data;
558 c->processor_id = PRID_IMP_UNKNOWN;
559 c->fpu_id = FPIR_IMP_NONE;
560 c->cputype = CPU_UNKNOWN;
562 c->processor_id = read_c0_prid();
563 switch (c->processor_id & 0xff0000) {
564 case PRID_COMP_LEGACY:
570 case PRID_COMP_ALCHEMY:
571 cpu_probe_alchemy(c);
573 case PRID_COMP_SIBYTE:
577 case PRID_COMP_SANDCRAFT:
578 cpu_probe_sandcraft(c);
581 c->cputype = CPU_UNKNOWN;
583 if (c->options & MIPS_CPU_FPU)
584 c->fpu_id = cpu_get_fpu_id();
587 __init void cpu_report(void)
589 struct cpuinfo_mips *c = ¤t_cpu_data;
591 printk("CPU revision is: %08x\n", c->processor_id);
592 if (c->options & MIPS_CPU_FPU)
593 printk("FPU revision is: %08x\n", c->fpu_id);