1 /***********************************************************************
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
7 * Based on arch/mips/ddb5xxx/ddb5477/setup.c
9 * Setup file for JMR3927.
11 * Copyright (C) 2000-2001 Toshiba Corporation
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 ***********************************************************************
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/kdev_t.h>
39 #include <linux/types.h>
40 #include <linux/sched.h>
41 #include <linux/pci.h>
42 #include <linux/ide.h>
43 #include <linux/irq.h>
44 #include <linux/ioport.h>
45 #include <linux/param.h> /* for HZ */
46 #include <linux/delay.h>
48 #ifdef CONFIG_SERIAL_TXX9
49 #include <linux/tty.h>
50 #include <linux/serial.h>
51 #include <linux/serial_core.h>
54 #include <asm/addrspace.h>
56 #include <asm/bcache.h>
58 #include <asm/reboot.h>
59 #include <asm/gdb-stub.h>
60 #include <asm/jmr3927/jmr3927.h>
61 #include <asm/mipsregs.h>
62 #include <asm/traps.h>
64 extern void puts(unsigned char *cp);
66 /* Tick Timer divider */
67 #define JMR3927_TIMER_CCD 0 /* 1/2 */
68 #define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
70 unsigned char led_state = 0xf;
75 struct resource pcimem;
78 struct resource pciio;
79 struct resource jmy1394;
84 } jmr3927_resources = {
89 .flags = IORESOURCE_MEM
94 .flags = IORESOURCE_MEM
99 .flags = IORESOURCE_MEM
135 /* don't enable - see errata */
136 int jmr3927_ccfg_toeon = 0;
138 static inline void do_reset(void)
140 #if 1 /* Resetting PCI bus */
141 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
142 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
143 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
145 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
147 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
150 static void jmr3927_machine_restart(char *command)
153 puts("Rebooting...");
157 static void jmr3927_machine_halt(void)
159 puts("JMR-TX3927 halted.\n");
163 static void jmr3927_machine_power_off(void)
165 puts("JMR-TX3927 halted. Please turn off the power.\n");
169 static cycle_t jmr3927_hpt_read(void)
171 /* We assume this function is called xtime_lock held. */
172 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
175 #define USE_RTC_DS1742
176 #ifdef USE_RTC_DS1742
177 extern void rtc_ds1742_init(unsigned long base);
179 static void __init jmr3927_time_init(void)
181 clocksource_mips.read = jmr3927_hpt_read;
182 mips_hpt_frequency = JMR3927_TIMER_CLK;
183 #ifdef USE_RTC_DS1742
184 if (jmr3927_have_nvram()) {
185 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
190 void __init plat_timer_setup(struct irqaction *irq)
192 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
193 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
194 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
195 jmr3927_tmrptr->tcr =
196 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
198 setup_irq(JMR3927_IRQ_TICK, irq);
201 #define USECS_PER_JIFFY (1000000/HZ)
203 //#undef DO_WRITE_THROUGH
204 #define DO_WRITE_THROUGH
205 #define DO_ENABLE_CACHE
207 extern char * __init prom_getcmdline(void);
208 static void jmr3927_board_init(void);
209 extern struct resource pci_io_resource;
210 extern struct resource pci_mem_resource;
212 void __init plat_mem_setup(void)
216 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
218 board_time_init = jmr3927_time_init;
220 _machine_restart = jmr3927_machine_restart;
221 _machine_halt = jmr3927_machine_halt;
222 pm_power_off = jmr3927_machine_power_off;
227 ioport_resource.start = pci_io_resource.start;
228 ioport_resource.end = pci_io_resource.end;
229 iomem_resource.start = 0;
230 iomem_resource.end = 0xffffffff;
232 /* Reboot on panic */
237 conf = read_c0_conf();
244 #ifdef DO_ENABLE_CACHE
245 int mips_ic_disable = 0, mips_dc_disable = 0;
247 int mips_ic_disable = 1, mips_dc_disable = 1;
249 #ifdef DO_WRITE_THROUGH
250 int mips_config_cwfon = 0;
251 int mips_config_wbon = 0;
253 int mips_config_cwfon = 1;
254 int mips_config_wbon = 1;
257 conf = read_c0_conf();
258 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
259 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
260 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
261 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
262 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
269 /* initialize board */
270 jmr3927_board_init();
272 argptr = prom_getcmdline();
274 if ((argptr = strstr(argptr, "toeon")) != NULL) {
275 jmr3927_ccfg_toeon = 1;
277 argptr = prom_getcmdline();
278 if ((argptr = strstr(argptr, "ip=")) == NULL) {
279 argptr = prom_getcmdline();
280 strcat(argptr, " ip=bootp");
283 #ifdef CONFIG_SERIAL_TXX9
285 extern int early_serial_txx9_setup(struct uart_port *port);
287 struct uart_port req;
288 for(i = 0; i < 2; i++) {
289 memset(&req, 0, sizeof(req));
291 req.iotype = UPIO_MEM;
292 req.membase = (char *)TX3927_SIO_REG(i);
293 req.mapbase = TX3927_SIO_REG(i);
295 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
297 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
298 req.uartclk = JMR3927_IMCLK;
299 early_serial_txx9_setup(&req);
302 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
303 argptr = prom_getcmdline();
304 if ((argptr = strstr(argptr, "console=")) == NULL) {
305 argptr = prom_getcmdline();
306 strcat(argptr, " console=ttyS1,115200");
312 static void tx3927_setup(void);
315 unsigned long mips_pci_io_base;
316 unsigned long mips_pci_io_size;
317 unsigned long mips_pci_mem_base;
318 unsigned long mips_pci_mem_size;
319 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
320 unsigned long mips_pci_io_pciaddr = 0;
323 static void __init jmr3927_board_init(void)
328 mips_pci_io_base = JMR3927_PCIIO;
329 mips_pci_io_size = JMR3927_PCIIO_SIZE;
330 mips_pci_mem_base = JMR3927_PCIMEM;
331 mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
336 if (jmr3927_have_isac()) {
338 #ifdef CONFIG_FB_E1355
339 argptr = prom_getcmdline();
340 if ((argptr = strstr(argptr, "video=")) == NULL) {
341 argptr = prom_getcmdline();
342 strcat(argptr, " video=e1355fb:crt16h");
346 #ifdef CONFIG_BLK_DEV_IDE
347 /* overrides PCI-IDE */
352 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
357 if (jmr3927_have_isac())
358 jmr3927_io_led_set(0);
359 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
360 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
361 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
362 jmr3927_dipsw1(), jmr3927_dipsw2(),
363 jmr3927_dipsw3(), jmr3927_dipsw4());
364 if (jmr3927_have_isac())
365 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
366 jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
370 void __init tx3927_setup(void)
374 /* SDRAMC are configured by PROM */
377 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
378 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
379 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
380 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
383 /* enable Timeout BusError */
384 if (jmr3927_ccfg_toeon)
385 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
387 /* clear BusErrorOnWrite flag */
388 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
389 /* Disable PCI snoop */
390 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
392 #ifdef DO_WRITE_THROUGH
393 /* Enable PCI SNOOP - with write through only */
394 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
398 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
399 tx3927_ccfgptr->pcfg |=
400 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
401 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
403 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
404 tx3927_ccfgptr->crir,
405 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
408 /* disable interrupt control */
409 tx3927_ircptr->cer = 0;
410 /* mask all IRC interrupts */
411 tx3927_ircptr->imr = 0;
412 for (i = 0; i < TX3927_NUM_IR / 2; i++) {
413 tx3927_ircptr->ilr[i] = 0;
415 /* setup IRC interrupt mode (Low Active) */
416 for (i = 0; i < TX3927_NUM_IR / 8; i++) {
417 tx3927_ircptr->cr[i] = 0;
421 /* disable all timers */
422 for (i = 0; i < TX3927_NR_TMR; i++) {
423 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
424 tx3927_tmrptr(i)->tisr = 0;
425 tx3927_tmrptr(i)->cpra = 0xffffffff;
426 tx3927_tmrptr(i)->itmr = 0;
427 tx3927_tmrptr(i)->ccdr = 0;
428 tx3927_tmrptr(i)->pgmr = 0;
432 tx3927_dmaptr->mcr = 0;
433 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
435 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
436 tx3927_dmaptr->ch[i].ccr = 0;
440 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
442 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
447 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
448 tx3927_pcicptr->did, tx3927_pcicptr->vid,
449 tx3927_pcicptr->rid);
450 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
451 printk("External\n");
454 printk("Internal\n");
457 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
459 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
460 JMR3927_IOC_RESET_ADDR);
462 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
465 /* Disable External PCI Config. Access */
466 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
468 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
469 TX3927_PCIC_LBC_TIBSE |
470 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
472 /* LB->PCI mappings */
473 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
474 tx3927_pcicptr->ilbioma = mips_pci_io_base;
475 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
476 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
477 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
478 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
479 /* PCI->LB mappings */
480 tx3927_pcicptr->iobas = 0xffffffff;
481 tx3927_pcicptr->ioba = 0;
482 tx3927_pcicptr->tlbioma = 0;
483 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
484 tx3927_pcicptr->mba = 0;
485 tx3927_pcicptr->tlbmma = 0;
486 #ifndef JMR3927_INIT_INDIRECT_PCI
487 /* Enable Direct mapping Address Space Decoder */
488 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
491 /* Clear All Local Bus Status */
492 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
493 /* Enable All Local Bus Interrupts */
494 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
495 /* Clear All PCI Status Error */
496 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
497 /* Enable All PCI Status Error Interrupts */
498 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
500 /* PCIC Int => IRC IRQ10 */
501 tx3927_pcicptr->il = TX3927_IR_PCI;
503 /* Target Control (per errata) */
504 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
507 /* Enable Bus Arbiter */
509 tx3927_pcicptr->req_trace = 0x73737373;
511 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
513 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
518 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
520 #endif /* CONFIG_PCI */
523 /* PIO[15:12] connected to LEDs */
524 tx3927_pioptr->dir = 0x0000f000;
525 tx3927_pioptr->maskcpu = 0;
526 tx3927_pioptr->maskext = 0;
530 conf = read_c0_conf();
531 if (!(conf & TX39_CONF_ICE))
532 printk("TX3927 I-Cache disabled.\n");
533 if (!(conf & TX39_CONF_DCE))
534 printk("TX3927 D-Cache disabled.\n");
535 else if (!(conf & TX39_CONF_WBON))
536 printk("TX3927 D-Cache WriteThrough.\n");
537 else if (!(conf & TX39_CONF_CWFON))
538 printk("TX3927 D-Cache WriteBack.\n");
540 printk("TX3927 D-Cache WriteBack (CWF) .\n");