2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 * Copyright (C) 2004 Silicon Graphics, Inc.
11 * Note: Above list of copyright holders is incomplete...
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/smp_lock.h>
22 #include <linux/spinlock.h>
24 #include <asm/machvec.h>
26 #include <asm/system.h>
31 #include <asm/hw_irq.h>
34 * Low-level SAL-based PCI configuration access functions. Note that SAL
35 * calls are already serialized (via sal_lock), so we don't need another
36 * synchronization mechanism here.
39 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
40 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
42 /* SAL 3.2 adds support for extended config space. */
44 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
45 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
48 pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
49 int reg, int len, u32 *value)
54 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
57 if ((seg | reg) <= 255) {
58 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
61 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
64 result = ia64_sal_pci_config_read(addr, mode, len, &data);
73 pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
74 int reg, int len, u32 value)
79 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
82 if ((seg | reg) <= 255) {
83 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
86 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
89 result = ia64_sal_pci_config_write(addr, mode, len, value);
95 static struct pci_raw_ops pci_sal_ops = {
97 .write = pci_sal_write
100 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
103 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
105 return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
106 devfn, where, size, value);
110 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
112 return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
113 devfn, where, size, value);
116 struct pci_ops pci_root_ops = {
121 /* Called by ACPI when it finds a new root bus. */
123 static struct pci_controller * __devinit
124 alloc_pci_controller (int seg)
126 struct pci_controller *controller;
128 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
132 memset(controller, 0, sizeof(*controller));
133 controller->segment = seg;
134 controller->node = -1;
138 struct pci_root_info {
139 struct pci_controller *controller;
144 new_space (u64 phys_base, int sparse)
150 return 0; /* legacy I/O port space */
152 mmio_base = (u64) ioremap(phys_base, 0);
153 for (i = 0; i < num_io_spaces; i++)
154 if (io_space[i].mmio_base == mmio_base &&
155 io_space[i].sparse == sparse)
158 if (num_io_spaces == MAX_IO_SPACES) {
159 printk(KERN_ERR "PCI: Too many IO port spaces "
160 "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
165 io_space[i].mmio_base = mmio_base;
166 io_space[i].sparse = sparse;
172 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
174 struct resource *resource;
176 u64 base, min, max, base_port;
177 unsigned int sparse = 0, space_nr, len;
179 resource = kzalloc(sizeof(*resource), GFP_KERNEL);
181 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
186 len = strlen(info->name) + 32;
187 name = kzalloc(len, GFP_KERNEL);
189 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
195 max = min + addr->address_length - 1;
196 if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
199 space_nr = new_space(addr->translation_offset, sparse);
203 base = __pa(io_space[space_nr].mmio_base);
204 base_port = IO_SPACE_BASE(space_nr);
205 snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
206 base_port + min, base_port + max);
209 * The SDM guarantees the legacy 0-64K space is sparse, but if the
210 * mapping is done by the processor (not the bridge), ACPI may not
216 resource->name = name;
217 resource->flags = IORESOURCE_MEM;
218 resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
219 resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
220 insert_resource(&iomem_resource, resource);
232 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
233 struct acpi_resource_address64 *addr)
238 * We're only interested in _CRS descriptors that are
239 * - address space descriptors for memory or I/O space
241 * - producers, i.e., the address space is routed downstream,
242 * not consumed by the bridge itself
244 status = acpi_resource_to_address64(resource, addr);
245 if (ACPI_SUCCESS(status) &&
246 (addr->resource_type == ACPI_MEMORY_RANGE ||
247 addr->resource_type == ACPI_IO_RANGE) &&
248 addr->address_length &&
249 addr->producer_consumer == ACPI_PRODUCER)
255 static acpi_status __devinit
256 count_window (struct acpi_resource *resource, void *data)
258 unsigned int *windows = (unsigned int *) data;
259 struct acpi_resource_address64 addr;
262 status = resource_to_window(resource, &addr);
263 if (ACPI_SUCCESS(status))
269 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
271 struct pci_root_info *info = data;
272 struct pci_window *window;
273 struct acpi_resource_address64 addr;
275 unsigned long flags, offset = 0;
276 struct resource *root;
278 /* Return AE_OK for non-window resources to keep scanning for more */
279 status = resource_to_window(res, &addr);
280 if (!ACPI_SUCCESS(status))
283 if (addr.resource_type == ACPI_MEMORY_RANGE) {
284 flags = IORESOURCE_MEM;
285 root = &iomem_resource;
286 offset = addr.translation_offset;
287 } else if (addr.resource_type == ACPI_IO_RANGE) {
288 flags = IORESOURCE_IO;
289 root = &ioport_resource;
290 offset = add_io_space(info, &addr);
296 window = &info->controller->window[info->controller->windows++];
297 window->resource.name = info->name;
298 window->resource.flags = flags;
299 window->resource.start = addr.minimum + offset;
300 window->resource.end = window->resource.start + addr.address_length - 1;
301 window->resource.child = NULL;
302 window->offset = offset;
304 if (insert_resource(root, &window->resource)) {
305 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
306 window->resource.start, window->resource.end,
307 root->name, info->name);
313 static void __devinit
314 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
319 for (i = 0; i < ctrl->windows; i++) {
320 struct resource *res = &ctrl->window[i].resource;
321 /* HP's firmware has a hack to work around a Windows bug.
322 * Ignore these tiny memory ranges */
323 if ((res->flags & IORESOURCE_MEM) &&
324 (res->end - res->start < 16))
326 if (j >= PCI_BUS_NUM_RESOURCES) {
327 printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
328 res->end, res->flags);
331 bus->resource[j++] = res;
335 struct pci_bus * __devinit
336 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
338 struct pci_root_info info;
339 struct pci_controller *controller;
340 unsigned int windows = 0;
341 struct pci_bus *pbus;
345 controller = alloc_pci_controller(domain);
349 controller->acpi_handle = device->handle;
351 pxm = acpi_get_pxm(controller->acpi_handle);
354 controller->node = pxm_to_node(pxm);
357 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
359 controller->window = kmalloc_node(sizeof(*controller->window) * windows,
360 GFP_KERNEL, controller->node);
361 if (!controller->window)
364 name = kmalloc(16, GFP_KERNEL);
368 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
369 info.controller = controller;
371 acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
374 pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
376 pcibios_setup_root_windows(pbus, controller);
381 kfree(controller->window);
388 void pcibios_resource_to_bus(struct pci_dev *dev,
389 struct pci_bus_region *region, struct resource *res)
391 struct pci_controller *controller = PCI_CONTROLLER(dev);
392 unsigned long offset = 0;
395 for (i = 0; i < controller->windows; i++) {
396 struct pci_window *window = &controller->window[i];
397 if (!(window->resource.flags & res->flags))
399 if (window->resource.start > res->start)
401 if (window->resource.end < res->end)
403 offset = window->offset;
407 region->start = res->start - offset;
408 region->end = res->end - offset;
410 EXPORT_SYMBOL(pcibios_resource_to_bus);
412 void pcibios_bus_to_resource(struct pci_dev *dev,
413 struct resource *res, struct pci_bus_region *region)
415 struct pci_controller *controller = PCI_CONTROLLER(dev);
416 unsigned long offset = 0;
419 for (i = 0; i < controller->windows; i++) {
420 struct pci_window *window = &controller->window[i];
421 if (!(window->resource.flags & res->flags))
423 if (window->resource.start - window->offset > region->start)
425 if (window->resource.end - window->offset < region->end)
427 offset = window->offset;
431 res->start = region->start + offset;
432 res->end = region->end + offset;
434 EXPORT_SYMBOL(pcibios_bus_to_resource);
436 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
438 unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
439 struct resource *devr = &dev->resource[idx];
443 for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
444 struct resource *busr = dev->bus->resource[i];
446 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
448 if ((devr->start) && (devr->start >= busr->start) &&
449 (devr->end <= busr->end))
455 static void __devinit
456 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
458 struct pci_bus_region region;
461 for (i = start; i < limit; i++) {
462 if (!dev->resource[i].flags)
464 region.start = dev->resource[i].start;
465 region.end = dev->resource[i].end;
466 pcibios_bus_to_resource(dev, &dev->resource[i], ®ion);
467 if ((is_valid_resource(dev, i)))
468 pci_claim_resource(dev, i);
472 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
474 pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
477 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
479 pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
483 * Called after each bus is probed, but before its children are examined.
486 pcibios_fixup_bus (struct pci_bus *b)
491 pci_read_bridge_bases(b);
492 pcibios_fixup_bridge_resources(b->self);
494 list_for_each_entry(dev, &b->devices, bus_list)
495 pcibios_fixup_device_resources(dev);
501 pcibios_update_irq (struct pci_dev *dev, int irq)
503 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
505 /* ??? FIXME -- record old value for shutdown. */
509 pcibios_enable_resources (struct pci_dev *dev, int mask)
514 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
519 pci_read_config_word(dev, PCI_COMMAND, &cmd);
521 for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
522 /* Only set up the desired resources. */
523 if (!(mask & (1 << idx)))
526 r = &dev->resource[idx];
527 if (!(r->flags & type_mask))
529 if ((idx == PCI_ROM_RESOURCE) &&
530 (!(r->flags & IORESOURCE_ROM_ENABLE)))
532 if (!r->start && r->end) {
534 "PCI: Device %s not available because of resource collisions\n",
538 if (r->flags & IORESOURCE_IO)
539 cmd |= PCI_COMMAND_IO;
540 if (r->flags & IORESOURCE_MEM)
541 cmd |= PCI_COMMAND_MEMORY;
543 if (cmd != old_cmd) {
544 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
545 pci_write_config_word(dev, PCI_COMMAND, cmd);
551 pcibios_enable_device (struct pci_dev *dev, int mask)
555 ret = pcibios_enable_resources(dev, mask);
559 return acpi_pci_irq_enable(dev);
563 pcibios_disable_device (struct pci_dev *dev)
565 acpi_pci_irq_disable(dev);
569 pcibios_align_resource (void *data, struct resource *res,
570 resource_size_t size, resource_size_t align)
575 * PCI BIOS setup, always defaults to SAL interface
578 pcibios_setup (char *str)
584 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
585 enum pci_mmap_state mmap_state, int write_combine)
588 * I/O space cannot be accessed via normal processor loads and
589 * stores on this platform.
591 if (mmap_state == pci_mmap_io)
593 * XXX we could relax this for I/O spaces for which ACPI
594 * indicates that the space is 1-to-1 mapped. But at the
595 * moment, we don't support multiple PCI address spaces and
596 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
601 * Leave vm_pgoff as-is, the PCI space address is the physical
602 * address on this platform.
604 if (write_combine && efi_range_is_wc(vma->vm_start,
605 vma->vm_end - vma->vm_start))
606 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
608 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
610 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
611 vma->vm_end - vma->vm_start, vma->vm_page_prot))
618 * ia64_pci_get_legacy_mem - generic legacy mem routine
619 * @bus: bus to get legacy memory base address for
621 * Find the base of legacy memory for @bus. This is typically the first
622 * megabyte of bus address space for @bus or is simply 0 on platforms whose
623 * chipsets support legacy I/O and memory routing. Returns the base address
624 * or an error pointer if an error occurred.
626 * This is the ia64 generic version of this routine. Other platforms
627 * are free to override it with a machine vector.
629 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
631 return (char *)__IA64_UNCACHED_OFFSET;
635 * pci_mmap_legacy_page_range - map legacy memory space to userland
636 * @bus: bus whose legacy space we're mapping
637 * @vma: vma passed in by mmap
639 * Map legacy memory space for this device back to userspace using a machine
640 * vector to get the base address.
643 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
645 unsigned long size = vma->vm_end - vma->vm_start;
650 * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt
653 if (!valid_mmap_phys_addr_range(vma->vm_pgoff << PAGE_SHIFT, size))
655 prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
657 if (pgprot_val(prot) != pgprot_val(pgprot_noncached(vma->vm_page_prot)))
660 addr = pci_get_legacy_mem(bus);
662 return PTR_ERR(addr);
664 vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
665 vma->vm_page_prot = prot;
667 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
668 size, vma->vm_page_prot))
675 * ia64_pci_legacy_read - read from legacy I/O space
677 * @port: legacy port value
678 * @val: caller allocated storage for returned value
679 * @size: number of bytes to read
681 * Simply reads @size bytes from @port and puts the result in @val.
683 * Again, this (and the write routine) are generic versions that can be
684 * overridden by the platform. This is necessary on platforms that don't
685 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
687 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
710 * ia64_pci_legacy_write - perform a legacy I/O write
712 * @port: port to write
713 * @val: value to write
714 * @size: number of bytes to write from @val
716 * Simply writes @size bytes of @val to @port.
718 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
741 * pci_cacheline_size - determine cacheline size for PCI devices
744 * We want to use the line-size of the outer-most cache. We assume
745 * that this line-size is the same for all CPUs.
747 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
749 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
752 pci_cacheline_size (void)
754 u64 levels, unique_caches;
756 pal_cache_config_info_t cci;
757 static u8 cacheline_size;
760 return cacheline_size;
762 status = ia64_pal_cache_summary(&levels, &unique_caches);
764 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
765 __FUNCTION__, status);
766 return SMP_CACHE_BYTES;
769 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
772 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
773 __FUNCTION__, status);
774 return SMP_CACHE_BYTES;
776 cacheline_size = 1 << cci.pcci_line_size;
777 return cacheline_size;
781 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
782 * @dev: the PCI device for which MWI is enabled
784 * For ia64, we can get the cacheline sizes from PAL.
786 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
789 pcibios_prep_mwi (struct pci_dev *dev)
791 unsigned long desired_linesize, current_linesize;
795 desired_linesize = pci_cacheline_size();
797 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
798 current_linesize = 4 * pci_linesize;
799 if (desired_linesize != current_linesize) {
800 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
801 pci_name(dev), current_linesize);
802 if (current_linesize > desired_linesize) {
803 printk(" expected %lu bytes instead\n", desired_linesize);
806 printk(" correcting to %lu\n", desired_linesize);
807 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
813 int pci_vector_resources(int last, int nr_released)
815 int count = nr_released;
817 count += (IA64_LAST_DEVICE_VECTOR - last);