2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 * Copyright (C) 2004 Silicon Graphics, Inc.
11 * Note: Above list of copyright holders is incomplete...
13 #include <linux/config.h>
15 #include <linux/acpi.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/smp_lock.h>
23 #include <linux/spinlock.h>
25 #include <asm/machvec.h>
27 #include <asm/system.h>
32 #include <asm/hw_irq.h>
35 * Low-level SAL-based PCI configuration access functions. Note that SAL
36 * calls are already serialized (via sal_lock), so we don't need another
37 * synchronization mechanism here.
40 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
41 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
43 /* SAL 3.2 adds support for extended config space. */
45 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
46 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
49 pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
50 int reg, int len, u32 *value)
55 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
58 if ((seg | reg) <= 255) {
59 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
62 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
65 result = ia64_sal_pci_config_read(addr, mode, len, &data);
74 pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
75 int reg, int len, u32 value)
80 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
83 if ((seg | reg) <= 255) {
84 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
87 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
90 result = ia64_sal_pci_config_write(addr, mode, len, value);
96 static struct pci_raw_ops pci_sal_ops = {
98 .write = pci_sal_write
101 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
104 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
106 return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
107 devfn, where, size, value);
111 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
113 return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
114 devfn, where, size, value);
117 struct pci_ops pci_root_ops = {
122 /* Called by ACPI when it finds a new root bus. */
124 static struct pci_controller * __devinit
125 alloc_pci_controller (int seg)
127 struct pci_controller *controller;
129 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
133 memset(controller, 0, sizeof(*controller));
134 controller->segment = seg;
135 controller->node = -1;
139 struct pci_root_info {
140 struct pci_controller *controller;
145 new_space (u64 phys_base, int sparse)
151 return 0; /* legacy I/O port space */
153 mmio_base = (u64) ioremap(phys_base, 0);
154 for (i = 0; i < num_io_spaces; i++)
155 if (io_space[i].mmio_base == mmio_base &&
156 io_space[i].sparse == sparse)
159 if (num_io_spaces == MAX_IO_SPACES) {
160 printk(KERN_ERR "PCI: Too many IO port spaces "
161 "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
166 io_space[i].mmio_base = mmio_base;
167 io_space[i].sparse = sparse;
173 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
175 struct resource *resource;
177 u64 base, min, max, base_port;
178 unsigned int sparse = 0, space_nr, len;
180 resource = kzalloc(sizeof(*resource), GFP_KERNEL);
182 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
187 len = strlen(info->name) + 32;
188 name = kzalloc(len, GFP_KERNEL);
190 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
196 max = min + addr->address_length - 1;
197 if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
200 space_nr = new_space(addr->translation_offset, sparse);
204 base = __pa(io_space[space_nr].mmio_base);
205 base_port = IO_SPACE_BASE(space_nr);
206 snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
207 base_port + min, base_port + max);
210 * The SDM guarantees the legacy 0-64K space is sparse, but if the
211 * mapping is done by the processor (not the bridge), ACPI may not
217 resource->name = name;
218 resource->flags = IORESOURCE_MEM;
219 resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
220 resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
221 insert_resource(&iomem_resource, resource);
233 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
234 struct acpi_resource_address64 *addr)
239 * We're only interested in _CRS descriptors that are
240 * - address space descriptors for memory or I/O space
242 * - producers, i.e., the address space is routed downstream,
243 * not consumed by the bridge itself
245 status = acpi_resource_to_address64(resource, addr);
246 if (ACPI_SUCCESS(status) &&
247 (addr->resource_type == ACPI_MEMORY_RANGE ||
248 addr->resource_type == ACPI_IO_RANGE) &&
249 addr->address_length &&
250 addr->producer_consumer == ACPI_PRODUCER)
256 static acpi_status __devinit
257 count_window (struct acpi_resource *resource, void *data)
259 unsigned int *windows = (unsigned int *) data;
260 struct acpi_resource_address64 addr;
263 status = resource_to_window(resource, &addr);
264 if (ACPI_SUCCESS(status))
270 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
272 struct pci_root_info *info = data;
273 struct pci_window *window;
274 struct acpi_resource_address64 addr;
276 unsigned long flags, offset = 0;
277 struct resource *root;
279 /* Return AE_OK for non-window resources to keep scanning for more */
280 status = resource_to_window(res, &addr);
281 if (!ACPI_SUCCESS(status))
284 if (addr.resource_type == ACPI_MEMORY_RANGE) {
285 flags = IORESOURCE_MEM;
286 root = &iomem_resource;
287 offset = addr.translation_offset;
288 } else if (addr.resource_type == ACPI_IO_RANGE) {
289 flags = IORESOURCE_IO;
290 root = &ioport_resource;
291 offset = add_io_space(info, &addr);
297 window = &info->controller->window[info->controller->windows++];
298 window->resource.name = info->name;
299 window->resource.flags = flags;
300 window->resource.start = addr.minimum + offset;
301 window->resource.end = window->resource.start + addr.address_length - 1;
302 window->resource.child = NULL;
303 window->offset = offset;
305 if (insert_resource(root, &window->resource)) {
306 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
307 window->resource.start, window->resource.end,
308 root->name, info->name);
314 static void __devinit
315 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
320 for (i = 0; i < ctrl->windows; i++) {
321 struct resource *res = &ctrl->window[i].resource;
322 /* HP's firmware has a hack to work around a Windows bug.
323 * Ignore these tiny memory ranges */
324 if ((res->flags & IORESOURCE_MEM) &&
325 (res->end - res->start < 16))
327 if (j >= PCI_BUS_NUM_RESOURCES) {
328 printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
329 res->end, res->flags);
332 bus->resource[j++] = res;
336 struct pci_bus * __devinit
337 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
339 struct pci_root_info info;
340 struct pci_controller *controller;
341 unsigned int windows = 0;
342 struct pci_bus *pbus;
346 controller = alloc_pci_controller(domain);
350 controller->acpi_handle = device->handle;
352 pxm = acpi_get_pxm(controller->acpi_handle);
355 controller->node = pxm_to_nid_map[pxm];
358 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
360 controller->window = kmalloc_node(sizeof(*controller->window) * windows,
361 GFP_KERNEL, controller->node);
362 if (!controller->window)
365 name = kmalloc(16, GFP_KERNEL);
369 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
370 info.controller = controller;
372 acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
375 pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
377 pcibios_setup_root_windows(pbus, controller);
382 kfree(controller->window);
389 void pcibios_resource_to_bus(struct pci_dev *dev,
390 struct pci_bus_region *region, struct resource *res)
392 struct pci_controller *controller = PCI_CONTROLLER(dev);
393 unsigned long offset = 0;
396 for (i = 0; i < controller->windows; i++) {
397 struct pci_window *window = &controller->window[i];
398 if (!(window->resource.flags & res->flags))
400 if (window->resource.start > res->start)
402 if (window->resource.end < res->end)
404 offset = window->offset;
408 region->start = res->start - offset;
409 region->end = res->end - offset;
411 EXPORT_SYMBOL(pcibios_resource_to_bus);
413 void pcibios_bus_to_resource(struct pci_dev *dev,
414 struct resource *res, struct pci_bus_region *region)
416 struct pci_controller *controller = PCI_CONTROLLER(dev);
417 unsigned long offset = 0;
420 for (i = 0; i < controller->windows; i++) {
421 struct pci_window *window = &controller->window[i];
422 if (!(window->resource.flags & res->flags))
424 if (window->resource.start - window->offset > region->start)
426 if (window->resource.end - window->offset < region->end)
428 offset = window->offset;
432 res->start = region->start + offset;
433 res->end = region->end + offset;
435 EXPORT_SYMBOL(pcibios_bus_to_resource);
437 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
439 unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
440 struct resource *devr = &dev->resource[idx];
444 for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
445 struct resource *busr = dev->bus->resource[i];
447 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
449 if ((devr->start) && (devr->start >= busr->start) &&
450 (devr->end <= busr->end))
456 static void __devinit
457 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
459 struct pci_bus_region region;
462 for (i = start; i < limit; i++) {
463 if (!dev->resource[i].flags)
465 region.start = dev->resource[i].start;
466 region.end = dev->resource[i].end;
467 pcibios_bus_to_resource(dev, &dev->resource[i], ®ion);
468 if ((is_valid_resource(dev, i)))
469 pci_claim_resource(dev, i);
473 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
475 pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
478 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
480 pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
484 * Called after each bus is probed, but before its children are examined.
487 pcibios_fixup_bus (struct pci_bus *b)
492 pci_read_bridge_bases(b);
493 pcibios_fixup_bridge_resources(b->self);
495 list_for_each_entry(dev, &b->devices, bus_list)
496 pcibios_fixup_device_resources(dev);
502 pcibios_update_irq (struct pci_dev *dev, int irq)
504 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
506 /* ??? FIXME -- record old value for shutdown. */
510 pcibios_enable_resources (struct pci_dev *dev, int mask)
515 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
520 pci_read_config_word(dev, PCI_COMMAND, &cmd);
522 for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
523 /* Only set up the desired resources. */
524 if (!(mask & (1 << idx)))
527 r = &dev->resource[idx];
528 if (!(r->flags & type_mask))
530 if ((idx == PCI_ROM_RESOURCE) &&
531 (!(r->flags & IORESOURCE_ROM_ENABLE)))
533 if (!r->start && r->end) {
535 "PCI: Device %s not available because of resource collisions\n",
539 if (r->flags & IORESOURCE_IO)
540 cmd |= PCI_COMMAND_IO;
541 if (r->flags & IORESOURCE_MEM)
542 cmd |= PCI_COMMAND_MEMORY;
544 if (cmd != old_cmd) {
545 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
546 pci_write_config_word(dev, PCI_COMMAND, cmd);
552 pcibios_enable_device (struct pci_dev *dev, int mask)
556 ret = pcibios_enable_resources(dev, mask);
560 return acpi_pci_irq_enable(dev);
564 pcibios_disable_device (struct pci_dev *dev)
566 acpi_pci_irq_disable(dev);
570 pcibios_align_resource (void *data, struct resource *res,
571 unsigned long size, unsigned long align)
576 * PCI BIOS setup, always defaults to SAL interface
579 pcibios_setup (char *str)
585 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
586 enum pci_mmap_state mmap_state, int write_combine)
589 * I/O space cannot be accessed via normal processor loads and
590 * stores on this platform.
592 if (mmap_state == pci_mmap_io)
594 * XXX we could relax this for I/O spaces for which ACPI
595 * indicates that the space is 1-to-1 mapped. But at the
596 * moment, we don't support multiple PCI address spaces and
597 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
602 * Leave vm_pgoff as-is, the PCI space address is the physical
603 * address on this platform.
605 vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
607 if (write_combine && efi_range_is_wc(vma->vm_start,
608 vma->vm_end - vma->vm_start))
609 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
611 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
613 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
614 vma->vm_end - vma->vm_start, vma->vm_page_prot))
621 * ia64_pci_get_legacy_mem - generic legacy mem routine
622 * @bus: bus to get legacy memory base address for
624 * Find the base of legacy memory for @bus. This is typically the first
625 * megabyte of bus address space for @bus or is simply 0 on platforms whose
626 * chipsets support legacy I/O and memory routing. Returns the base address
627 * or an error pointer if an error occurred.
629 * This is the ia64 generic version of this routine. Other platforms
630 * are free to override it with a machine vector.
632 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
634 return (char *)__IA64_UNCACHED_OFFSET;
638 * pci_mmap_legacy_page_range - map legacy memory space to userland
639 * @bus: bus whose legacy space we're mapping
640 * @vma: vma passed in by mmap
642 * Map legacy memory space for this device back to userspace using a machine
643 * vector to get the base address.
646 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
650 addr = pci_get_legacy_mem(bus);
652 return PTR_ERR(addr);
654 vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
655 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
656 vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
658 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
659 vma->vm_end - vma->vm_start, vma->vm_page_prot))
666 * ia64_pci_legacy_read - read from legacy I/O space
668 * @port: legacy port value
669 * @val: caller allocated storage for returned value
670 * @size: number of bytes to read
672 * Simply reads @size bytes from @port and puts the result in @val.
674 * Again, this (and the write routine) are generic versions that can be
675 * overridden by the platform. This is necessary on platforms that don't
676 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
678 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
701 * ia64_pci_legacy_write - perform a legacy I/O write
703 * @port: port to write
704 * @val: value to write
705 * @size: number of bytes to write from @val
707 * Simply writes @size bytes of @val to @port.
709 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
732 * pci_cacheline_size - determine cacheline size for PCI devices
735 * We want to use the line-size of the outer-most cache. We assume
736 * that this line-size is the same for all CPUs.
738 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
740 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
743 pci_cacheline_size (void)
745 u64 levels, unique_caches;
747 pal_cache_config_info_t cci;
748 static u8 cacheline_size;
751 return cacheline_size;
753 status = ia64_pal_cache_summary(&levels, &unique_caches);
755 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
756 __FUNCTION__, status);
757 return SMP_CACHE_BYTES;
760 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
763 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
764 __FUNCTION__, status);
765 return SMP_CACHE_BYTES;
767 cacheline_size = 1 << cci.pcci_line_size;
768 return cacheline_size;
772 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
773 * @dev: the PCI device for which MWI is enabled
775 * For ia64, we can get the cacheline sizes from PAL.
777 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
780 pcibios_prep_mwi (struct pci_dev *dev)
782 unsigned long desired_linesize, current_linesize;
786 desired_linesize = pci_cacheline_size();
788 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
789 current_linesize = 4 * pci_linesize;
790 if (desired_linesize != current_linesize) {
791 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
792 pci_name(dev), current_linesize);
793 if (current_linesize > desired_linesize) {
794 printk(" expected %lu bytes instead\n", desired_linesize);
797 printk(" correcting to %lu\n", desired_linesize);
798 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
804 int pci_vector_resources(int last, int nr_released)
806 int count = nr_released;
808 count += (IA64_LAST_DEVICE_VECTOR - last);