2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 * Copyright (C) 2004 Silicon Graphics, Inc.
11 * Note: Above list of copyright holders is incomplete...
13 #include <linux/config.h>
15 #include <linux/acpi.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/smp_lock.h>
23 #include <linux/spinlock.h>
25 #include <asm/machvec.h>
27 #include <asm/segment.h>
28 #include <asm/system.h>
33 #include <asm/hw_irq.h>
37 * Low-level SAL-based PCI configuration access functions. Note that SAL
38 * calls are already serialized (via sal_lock), so we don't need another
39 * synchronization mechanism here.
42 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
43 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
45 /* SAL 3.2 adds support for extended config space. */
47 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
48 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
51 pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
52 int reg, int len, u32 *value)
57 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
60 if ((seg | reg) <= 255) {
61 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
64 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
67 result = ia64_sal_pci_config_read(addr, mode, len, &data);
76 pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
77 int reg, int len, u32 value)
82 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
85 if ((seg | reg) <= 255) {
86 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
89 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
92 result = ia64_sal_pci_config_write(addr, mode, len, value);
98 static struct pci_raw_ops pci_sal_ops = {
100 .write = pci_sal_write
103 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
106 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
108 return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
109 devfn, where, size, value);
113 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
115 return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
116 devfn, where, size, value);
119 struct pci_ops pci_root_ops = {
125 extern acpi_status acpi_map_iosapic(acpi_handle, u32, void *, void **);
126 static void acpi_map_iosapics(void)
128 acpi_get_devices(NULL, acpi_map_iosapic, NULL, NULL);
131 static void acpi_map_iosapics(void)
135 #endif /* CONFIG_NUMA */
145 subsys_initcall(pci_acpi_init);
147 /* Called by ACPI when it finds a new root bus. */
149 static struct pci_controller * __devinit
150 alloc_pci_controller (int seg)
152 struct pci_controller *controller;
154 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
158 memset(controller, 0, sizeof(*controller));
159 controller->segment = seg;
160 controller->node = -1;
165 add_io_space (struct acpi_resource_address64 *addr)
171 if (addr->address_translation_offset == 0)
172 return IO_SPACE_BASE(0); /* part of legacy IO space */
174 if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
177 offset = (u64) ioremap(addr->address_translation_offset, 0);
178 for (i = 0; i < num_io_spaces; i++)
179 if (io_space[i].mmio_base == offset &&
180 io_space[i].sparse == sparse)
181 return IO_SPACE_BASE(i);
183 if (num_io_spaces == MAX_IO_SPACES) {
184 printk("Too many IO port spaces\n");
189 io_space[i].mmio_base = offset;
190 io_space[i].sparse = sparse;
192 return IO_SPACE_BASE(i);
195 static acpi_status __devinit
196 count_window (struct acpi_resource *resource, void *data)
198 unsigned int *windows = (unsigned int *) data;
199 struct acpi_resource_address64 addr;
202 status = acpi_resource_to_address64(resource, &addr);
203 if (ACPI_SUCCESS(status))
204 if (addr.resource_type == ACPI_MEMORY_RANGE ||
205 addr.resource_type == ACPI_IO_RANGE)
211 struct pci_root_info {
212 struct pci_controller *controller;
216 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
218 struct pci_root_info *info = data;
219 struct pci_window *window;
220 struct acpi_resource_address64 addr;
222 unsigned long flags, offset = 0;
223 struct resource *root;
225 status = acpi_resource_to_address64(res, &addr);
226 if (!ACPI_SUCCESS(status))
229 if (!addr.address_length)
232 if (addr.resource_type == ACPI_MEMORY_RANGE) {
233 flags = IORESOURCE_MEM;
234 root = &iomem_resource;
235 offset = addr.address_translation_offset;
236 } else if (addr.resource_type == ACPI_IO_RANGE) {
237 flags = IORESOURCE_IO;
238 root = &ioport_resource;
239 offset = add_io_space(&addr);
245 window = &info->controller->window[info->controller->windows++];
246 window->resource.name = info->name;
247 window->resource.flags = flags;
248 window->resource.start = addr.min_address_range + offset;
249 window->resource.end = addr.max_address_range + offset;
250 window->resource.child = NULL;
251 window->offset = offset;
253 if (insert_resource(root, &window->resource)) {
254 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
255 window->resource.start, window->resource.end,
256 root->name, info->name);
262 static void __devinit
263 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
268 for (i = 0; i < ctrl->windows; i++) {
269 struct resource *res = &ctrl->window[i].resource;
270 /* HP's firmware has a hack to work around a Windows bug.
271 * Ignore these tiny memory ranges */
272 if ((res->flags & IORESOURCE_MEM) &&
273 (res->end - res->start < 16))
275 if (j >= PCI_BUS_NUM_RESOURCES) {
276 printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
277 res->end, res->flags);
280 bus->resource[j++] = res;
284 struct pci_bus * __devinit
285 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
287 struct pci_root_info info;
288 struct pci_controller *controller;
289 unsigned int windows = 0;
290 struct pci_bus *pbus;
294 controller = alloc_pci_controller(domain);
298 controller->acpi_handle = device->handle;
300 pxm = acpi_get_pxm(controller->acpi_handle);
303 controller->node = pxm_to_nid_map[pxm];
306 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
308 controller->window = kmalloc_node(sizeof(*controller->window) * windows,
309 GFP_KERNEL, controller->node);
310 if (!controller->window)
313 name = kmalloc(16, GFP_KERNEL);
317 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
318 info.controller = controller;
320 acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
323 pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
325 pcibios_setup_root_windows(pbus, controller);
330 kfree(controller->window);
337 void pcibios_resource_to_bus(struct pci_dev *dev,
338 struct pci_bus_region *region, struct resource *res)
340 struct pci_controller *controller = PCI_CONTROLLER(dev);
341 unsigned long offset = 0;
344 for (i = 0; i < controller->windows; i++) {
345 struct pci_window *window = &controller->window[i];
346 if (!(window->resource.flags & res->flags))
348 if (window->resource.start > res->start)
350 if (window->resource.end < res->end)
352 offset = window->offset;
356 region->start = res->start - offset;
357 region->end = res->end - offset;
359 EXPORT_SYMBOL(pcibios_resource_to_bus);
361 void pcibios_bus_to_resource(struct pci_dev *dev,
362 struct resource *res, struct pci_bus_region *region)
364 struct pci_controller *controller = PCI_CONTROLLER(dev);
365 unsigned long offset = 0;
368 for (i = 0; i < controller->windows; i++) {
369 struct pci_window *window = &controller->window[i];
370 if (!(window->resource.flags & res->flags))
372 if (window->resource.start - window->offset > region->start)
374 if (window->resource.end - window->offset < region->end)
376 offset = window->offset;
380 res->start = region->start + offset;
381 res->end = region->end + offset;
384 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
386 unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
387 struct resource *devr = &dev->resource[idx];
391 for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
392 struct resource *busr = dev->bus->resource[i];
394 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
396 if ((devr->start) && (devr->start >= busr->start) &&
397 (devr->end <= busr->end))
403 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
405 struct pci_bus_region region;
407 int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
408 PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
410 for (i = 0; i < limit; i++) {
411 if (!dev->resource[i].flags)
413 region.start = dev->resource[i].start;
414 region.end = dev->resource[i].end;
415 pcibios_bus_to_resource(dev, &dev->resource[i], ®ion);
416 if ((is_valid_resource(dev, i)))
417 pci_claim_resource(dev, i);
422 * Called after each bus is probed, but before its children are examined.
425 pcibios_fixup_bus (struct pci_bus *b)
430 pci_read_bridge_bases(b);
431 pcibios_fixup_device_resources(b->self);
433 list_for_each_entry(dev, &b->devices, bus_list)
434 pcibios_fixup_device_resources(dev);
440 pcibios_update_irq (struct pci_dev *dev, int irq)
442 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
444 /* ??? FIXME -- record old value for shutdown. */
448 pcibios_enable_resources (struct pci_dev *dev, int mask)
453 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
458 pci_read_config_word(dev, PCI_COMMAND, &cmd);
460 for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
461 /* Only set up the desired resources. */
462 if (!(mask & (1 << idx)))
465 r = &dev->resource[idx];
466 if (!(r->flags & type_mask))
468 if ((idx == PCI_ROM_RESOURCE) &&
469 (!(r->flags & IORESOURCE_ROM_ENABLE)))
471 if (!r->start && r->end) {
473 "PCI: Device %s not available because of resource collisions\n",
477 if (r->flags & IORESOURCE_IO)
478 cmd |= PCI_COMMAND_IO;
479 if (r->flags & IORESOURCE_MEM)
480 cmd |= PCI_COMMAND_MEMORY;
482 if (cmd != old_cmd) {
483 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
484 pci_write_config_word(dev, PCI_COMMAND, cmd);
490 pcibios_enable_device (struct pci_dev *dev, int mask)
494 ret = pcibios_enable_resources(dev, mask);
498 return acpi_pci_irq_enable(dev);
501 #ifdef CONFIG_ACPI_DEALLOCATE_IRQ
503 pcibios_disable_device (struct pci_dev *dev)
505 acpi_pci_irq_disable(dev);
507 #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */
510 pcibios_align_resource (void *data, struct resource *res,
511 unsigned long size, unsigned long align)
516 * PCI BIOS setup, always defaults to SAL interface
519 pcibios_setup (char *str)
525 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
526 enum pci_mmap_state mmap_state, int write_combine)
529 * I/O space cannot be accessed via normal processor loads and
530 * stores on this platform.
532 if (mmap_state == pci_mmap_io)
534 * XXX we could relax this for I/O spaces for which ACPI
535 * indicates that the space is 1-to-1 mapped. But at the
536 * moment, we don't support multiple PCI address spaces and
537 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
542 * Leave vm_pgoff as-is, the PCI space address is the physical
543 * address on this platform.
545 vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
547 if (write_combine && efi_range_is_wc(vma->vm_start,
548 vma->vm_end - vma->vm_start))
549 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
551 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
553 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
554 vma->vm_end - vma->vm_start, vma->vm_page_prot))
561 * ia64_pci_get_legacy_mem - generic legacy mem routine
562 * @bus: bus to get legacy memory base address for
564 * Find the base of legacy memory for @bus. This is typically the first
565 * megabyte of bus address space for @bus or is simply 0 on platforms whose
566 * chipsets support legacy I/O and memory routing. Returns the base address
567 * or an error pointer if an error occurred.
569 * This is the ia64 generic version of this routine. Other platforms
570 * are free to override it with a machine vector.
572 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
574 return (char *)__IA64_UNCACHED_OFFSET;
578 * pci_mmap_legacy_page_range - map legacy memory space to userland
579 * @bus: bus whose legacy space we're mapping
580 * @vma: vma passed in by mmap
582 * Map legacy memory space for this device back to userspace using a machine
583 * vector to get the base address.
586 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
590 addr = pci_get_legacy_mem(bus);
592 return PTR_ERR(addr);
594 vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
595 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
596 vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
598 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
599 vma->vm_end - vma->vm_start, vma->vm_page_prot))
606 * ia64_pci_legacy_read - read from legacy I/O space
608 * @port: legacy port value
609 * @val: caller allocated storage for returned value
610 * @size: number of bytes to read
612 * Simply reads @size bytes from @port and puts the result in @val.
614 * Again, this (and the write routine) are generic versions that can be
615 * overridden by the platform. This is necessary on platforms that don't
616 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
618 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
641 * ia64_pci_legacy_write - perform a legacy I/O write
643 * @port: port to write
644 * @val: value to write
645 * @size: number of bytes to write from @val
647 * Simply writes @size bytes of @val to @port.
649 int ia64_pci_legacy_write(struct pci_dev *bus, u16 port, u32 val, u8 size)
672 * pci_cacheline_size - determine cacheline size for PCI devices
675 * We want to use the line-size of the outer-most cache. We assume
676 * that this line-size is the same for all CPUs.
678 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
680 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
683 pci_cacheline_size (void)
685 u64 levels, unique_caches;
687 pal_cache_config_info_t cci;
688 static u8 cacheline_size;
691 return cacheline_size;
693 status = ia64_pal_cache_summary(&levels, &unique_caches);
695 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
696 __FUNCTION__, status);
697 return SMP_CACHE_BYTES;
700 status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
703 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
704 __FUNCTION__, status);
705 return SMP_CACHE_BYTES;
707 cacheline_size = 1 << cci.pcci_line_size;
708 return cacheline_size;
712 * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
713 * @dev: the PCI device for which MWI is enabled
715 * For ia64, we can get the cacheline sizes from PAL.
717 * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
720 pcibios_prep_mwi (struct pci_dev *dev)
722 unsigned long desired_linesize, current_linesize;
726 desired_linesize = pci_cacheline_size();
728 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
729 current_linesize = 4 * pci_linesize;
730 if (desired_linesize != current_linesize) {
731 printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
732 pci_name(dev), current_linesize);
733 if (current_linesize > desired_linesize) {
734 printk(" expected %lu bytes instead\n", desired_linesize);
737 printk(" correcting to %lu\n", desired_linesize);
738 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
744 int pci_vector_resources(int last, int nr_released)
746 int count = nr_released;
748 count += (IA64_LAST_DEVICE_VECTOR - last);