2 * kvm_minstate.h: min save macros
3 * Copyright (c) 2007, Intel Corporation.
5 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
6 * Xiantao Zhang (xiantao.zhang@intel.com)
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
24 #include <asm/asmmacro.h>
25 #include <asm/types.h>
26 #include <asm/kregs.h>
27 #include "asm-offsets.h"
29 #define KVM_MINSTATE_START_SAVE_MIN \
30 mov ar.rsc = 0;/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */\
32 mov.m r28 = ar.rnat; \
33 addl r22 = VMM_RBS_OFFSET,r1; /* compute base of RBS */ \
35 lfetch.fault.excl.nt1 [r22]; \
36 addl r1 = IA64_STK_OFFSET-VMM_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
37 mov r23 = ar.bspstore; /* save ar.bspstore */ \
39 mov ar.bspstore = r22; /* switch to kernel RBS */\
42 mov ar.rsc = 0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
46 #define KVM_MINSTATE_END_SAVE_MIN \
47 bsw.1; /* switch back to bank 1 (must be last in insn group) */\
51 #define PAL_VSA_SYNC_READ \
52 /* begin to call pal vps sync_read */ \
53 add r25 = VMM_VPD_BASE_OFFSET, r21; \
54 adds r20 = VMM_VCPU_VSA_BASE_OFFSET, r21; /* entry point */ \
56 ld8 r25 = [r25]; /* read vpd base */ \
59 add r20 = PAL_VPS_SYNC_READ,r20; \
68 add r24 = 0x20, r24; \
70 br.cond.sptk b0; /* call the service */ \
76 #define KVM_MINSTATE_GET_CURRENT(reg) mov reg=r21
79 * KVM_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
80 * the minimum state necessary that allows us to turn psr.ic back
83 * Assumed state upon entry:
85 * r31: contains saved predicates (pr)
87 * Upon exit, the state is as follows:
89 * r2 = points to &pt_regs.r16
90 * r8 = contents of ar.ccv
91 * r9 = contents of ar.csd
92 * r10 = contents of ar.ssd
94 * r12 = kernel sp (kernel virtual address)
95 * r13 = points to current task_struct (kernel virtual address)
96 * p15 = TRUE if psr.i is set in cr.ipsr
97 * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
100 * Note that psr.ic is NOT turned on by this macro. This is so that
101 * we can pass interruption state as arguments to a handler.
105 #define PT(f) (VMM_PT_REGS_##f##_OFFSET)
107 #define KVM_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
108 KVM_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
109 mov r27 = ar.rsc; /* M */ \
110 mov r20 = r1; /* A */ \
111 mov r25 = ar.unat; /* M */ \
112 mov r29 = cr.ipsr; /* M */ \
113 mov r26 = ar.pfs; /* I */ \
115 COVER; /* B;; (or nothing) */ \
117 tbit.z p0,p15 = r29,IA64_PSR_I_BIT; \
120 /* switch from user to kernel RBS: */ \
125 KVM_MINSTATE_START_SAVE_MIN \
126 adds r17 = 2*L1_CACHE_BYTES,r1;/* cache-line size */ \
127 adds r16 = PT(CR_IPSR),r1; \
129 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
130 st8 [r16] = r29; /* save cr.ipsr */ \
132 lfetch.fault.excl.nt1 [r17]; \
133 tbit.nz p15,p0 = r29,IA64_PSR_I_BIT; \
136 adds r16 = PT(R8),r1; /* initialize first base pointer */\
137 adds r17 = PT(R9),r1; /* initialize second base pointer */\
139 .mem.offset 0,0; st8.spill [r16] = r8,16; \
140 .mem.offset 8,0; st8.spill [r17] = r9,16; \
142 .mem.offset 0,0; st8.spill [r16] = r10,24; \
143 .mem.offset 8,0; st8.spill [r17] = r11,24; \
145 mov r9 = cr.iip; /* M */ \
146 mov r10 = ar.fpsr; /* M */ \
148 st8 [r16] = r9,16; /* save cr.iip */ \
149 st8 [r17] = r30,16; /* save cr.ifs */ \
150 sub r18 = r18,r22; /* r18=RSE.ndirty*8 */ \
152 st8 [r16] = r25,16; /* save ar.unat */ \
153 st8 [r17] = r26,16; /* save ar.pfs */ \
154 shl r18 = r18,16; /* calu ar.rsc used for "loadrs" */\
156 st8 [r16] = r27,16; /* save ar.rsc */ \
157 st8 [r17] = r28,16; /* save ar.rnat */ \
158 ;; /* avoid RAW on r16 & r17 */ \
159 st8 [r16] = r23,16; /* save ar.bspstore */ \
160 st8 [r17] = r31,16; /* save predicates */ \
162 st8 [r16] = r29,16; /* save b0 */ \
163 st8 [r17] = r18,16; /* save ar.rsc value for "loadrs" */\
165 .mem.offset 0,0; st8.spill [r16] = r20,16;/* save original r1 */ \
166 .mem.offset 8,0; st8.spill [r17] = r12,16; \
167 adds r12 = -16,r1; /* switch to kernel memory stack */ \
169 .mem.offset 0,0; st8.spill [r16] = r13,16; \
170 .mem.offset 8,0; st8.spill [r17] = r10,16; /* save ar.fpsr */\
171 mov r13 = r21; /* establish `current' */ \
173 .mem.offset 0,0; st8.spill [r16] = r15,16; \
174 .mem.offset 8,0; st8.spill [r17] = r14,16; \
176 .mem.offset 0,0; st8.spill [r16] = r2,16; \
177 .mem.offset 8,0; st8.spill [r17] = r3,16; \
178 adds r2 = VMM_PT_REGS_R16_OFFSET,r1; \
180 adds r16 = VMM_VCPU_IIPA_OFFSET,r13; \
181 adds r17 = VMM_VCPU_ISR_OFFSET,r13; \
192 movl r11 = FPSR_DEFAULT; /* L-unit */ \
193 adds r17 = VMM_VCPU_GP_OFFSET,r13; \
195 ld8 r1 = [r17];/* establish kernel global pointer */ \
198 KVM_MINSTATE_END_SAVE_MIN
201 * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
203 * Assumed state upon entry:
205 * r2: points to &pt_regs.f6
206 * r3: points to &pt_regs.f7
207 * r8: contents of ar.ccv
208 * r9: contents of ar.csd
209 * r10: contents of ar.ssd
212 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
214 #define KVM_SAVE_REST \
215 .mem.offset 0,0; st8.spill [r2] = r16,16; \
216 .mem.offset 8,0; st8.spill [r3] = r17,16; \
218 .mem.offset 0,0; st8.spill [r2] = r18,16; \
219 .mem.offset 8,0; st8.spill [r3] = r19,16; \
221 .mem.offset 0,0; st8.spill [r2] = r20,16; \
222 .mem.offset 8,0; st8.spill [r3] = r21,16; \
225 .mem.offset 0,0; st8.spill [r2] = r22,16; \
226 .mem.offset 8,0; st8.spill [r3] = r23,16; \
229 .mem.offset 0,0; st8.spill [r2] = r24,16; \
230 .mem.offset 8,0; st8.spill [r3] = r25,16; \
232 .mem.offset 0,0; st8.spill [r2] = r26,16; \
233 .mem.offset 8,0; st8.spill [r3] = r27,16; \
235 .mem.offset 0,0; st8.spill [r2] = r28,16; \
236 .mem.offset 8,0; st8.spill [r3] = r29,16; \
238 .mem.offset 0,0; st8.spill [r2] = r30,16; \
239 .mem.offset 8,0; st8.spill [r3] = r31,32; \
243 adds r24 = PT(B6)-PT(F7),r3; \
244 adds r25 = PT(B7)-PT(F7),r3; \
246 st8 [r24] = r18,16; /* b6 */ \
247 st8 [r25] = r19,16; /* b7 */ \
248 adds r2 = PT(R4)-PT(F6),r2; \
249 adds r3 = PT(R5)-PT(F7),r3; \
251 st8 [r24] = r9; /* ar.csd */ \
252 st8 [r25] = r10; /* ar.ssd */ \
255 adds r19 = PT(EML_UNAT)-PT(R4),r2; \
257 st8 [r19] = r18; /* eml_unat */ \
260 #define KVM_SAVE_EXTRA \
261 .mem.offset 0,0; st8.spill [r2] = r4,16; \
262 .mem.offset 8,0; st8.spill [r3] = r5,16; \
264 .mem.offset 0,0; st8.spill [r2] = r6,16; \
265 .mem.offset 8,0; st8.spill [r3] = r7; \
269 st8 [r2] = r26;/* eml_unat */ \
271 #define KVM_SAVE_MIN_WITH_COVER KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs,)
272 #define KVM_SAVE_MIN_WITH_COVER_R19 KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs, mov r15 = r19)
273 #define KVM_SAVE_MIN KVM_DO_SAVE_MIN( , mov r30 = r0, )