2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/screen_info.h>
39 #include <linux/dmi.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
45 #include <linux/cpufreq.h>
46 #include <linux/kexec.h>
47 #include <linux/crash_dump.h>
50 #include <asm/machvec.h>
52 #include <asm/meminit.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
58 #include <asm/sections.h>
59 #include <asm/setup.h>
61 #include <asm/system.h>
62 #include <asm/unistd.h>
63 #include <asm/hpsim.h>
65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
66 # error "struct cpuinfo_ia64 too big!"
70 unsigned long __per_cpu_offset[NR_CPUS];
71 EXPORT_SYMBOL(__per_cpu_offset);
74 extern void ia64_setup_printk_clock(void);
76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
78 unsigned long ia64_cycles_per_usec;
79 struct ia64_boot_param *ia64_boot_param;
80 struct screen_info screen_info;
81 unsigned long vga_console_iobase;
82 unsigned long vga_console_membase;
84 static struct resource data_resource = {
85 .name = "Kernel data",
86 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
89 static struct resource code_resource = {
90 .name = "Kernel code",
91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
93 extern char _text[], _end[], _etext[];
95 unsigned long ia64_max_cacheline_size;
97 int dma_get_cache_alignment(void)
99 return ia64_max_cacheline_size;
101 EXPORT_SYMBOL(dma_get_cache_alignment);
103 unsigned long ia64_iobase; /* virtual address for I/O accesses */
104 EXPORT_SYMBOL(ia64_iobase);
105 struct io_space io_space[MAX_IO_SPACES];
106 EXPORT_SYMBOL(io_space);
107 unsigned int num_io_spaces;
110 * "flush_icache_range()" needs to know what processor dependent stride size to use
111 * when it makes i-cache(s) coherent with d-caches.
113 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
114 unsigned long ia64_i_cache_stride_shift = ~0;
117 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
118 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
119 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
120 * address of the second buffer must be aligned to (merge_mask+1) in order to be
121 * mergeable). By default, we assume there is no I/O MMU which can merge physically
122 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
125 unsigned long ia64_max_iommu_merge_mask = ~0UL;
126 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
129 * We use a special marker for the end of memory and it uses the extra (+1) slot
131 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
132 int num_rsvd_regions __initdata;
136 * Filter incoming memory segments based on the primitive map created from the boot
137 * parameters. Segments contained in the map are removed from the memory ranges. A
138 * caller-specified function is called with the memory ranges that remain after filtering.
139 * This routine does not assume the incoming segments are sorted.
142 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
144 unsigned long range_start, range_end, prev_start;
145 void (*func)(unsigned long, unsigned long, int);
149 if (start == PAGE_OFFSET) {
150 printk(KERN_WARNING "warning: skipping physical page 0\n");
152 if (start >= end) return 0;
156 * lowest possible address(walker uses virtual)
158 prev_start = PAGE_OFFSET;
161 for (i = 0; i < num_rsvd_regions; ++i) {
162 range_start = max(start, prev_start);
163 range_end = min(end, rsvd_region[i].start);
165 if (range_start < range_end)
166 call_pernode_memory(__pa(range_start), range_end - range_start, func);
168 /* nothing more available in this segment */
169 if (range_end == end) return 0;
171 prev_start = rsvd_region[i].end;
173 /* end of memory marker allows full processing inside loop body */
178 sort_regions (struct rsvd_region *rsvd_region, int max)
182 /* simple bubble sorting */
184 for (j = 0; j < max; ++j) {
185 if (rsvd_region[j].start > rsvd_region[j+1].start) {
186 struct rsvd_region tmp;
187 tmp = rsvd_region[j];
188 rsvd_region[j] = rsvd_region[j + 1];
189 rsvd_region[j + 1] = tmp;
196 * Request address space for all standard resources
198 static int __init register_memory(void)
200 code_resource.start = ia64_tpa(_text);
201 code_resource.end = ia64_tpa(_etext) - 1;
202 data_resource.start = ia64_tpa(_etext);
203 data_resource.end = ia64_tpa(_end) - 1;
204 efi_initialize_iomem_resources(&code_resource, &data_resource);
209 __initcall(register_memory);
213 static void __init setup_crashkernel(unsigned long total, int *n)
215 unsigned long long base = 0, size = 0;
218 ret = parse_crashkernel(boot_command_line, total,
220 if (ret == 0 && size > 0) {
222 sort_regions(rsvd_region, *n);
223 base = kdump_find_rsvd_region(size,
227 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
228 "for crashkernel (System RAM: %ldMB)\n",
229 (unsigned long)(size >> 20),
230 (unsigned long)(base >> 20),
231 (unsigned long)(total >> 20));
232 rsvd_region[*n].start =
233 (unsigned long)__va(base);
234 rsvd_region[*n].end =
235 (unsigned long)__va(base + size);
237 crashk_res.start = base;
238 crashk_res.end = base + size - 1;
241 efi_memmap_res.start = ia64_boot_param->efi_memmap;
242 efi_memmap_res.end = efi_memmap_res.start +
243 ia64_boot_param->efi_memmap_size;
244 boot_param_res.start = __pa(ia64_boot_param);
245 boot_param_res.end = boot_param_res.start +
246 sizeof(*ia64_boot_param);
249 static inline void __init setup_crashkernel(unsigned long total, int *n)
254 * reserve_memory - setup reserved memory areas
256 * Setup the reserved memory areas set aside for the boot parameters,
257 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
258 * see include/asm-ia64/meminit.h if you need to define more.
261 reserve_memory (void)
264 unsigned long total_memory;
267 * none of the entries in this table overlap
269 rsvd_region[n].start = (unsigned long) ia64_boot_param;
270 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
273 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
274 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
277 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
278 rsvd_region[n].end = (rsvd_region[n].start
279 + strlen(__va(ia64_boot_param->command_line)) + 1);
282 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
283 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
286 #ifdef CONFIG_BLK_DEV_INITRD
287 if (ia64_boot_param->initrd_start) {
288 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
289 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
294 #ifdef CONFIG_PROC_VMCORE
295 if (reserve_elfcorehdr(&rsvd_region[n].start,
296 &rsvd_region[n].end) == 0)
300 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
303 setup_crashkernel(total_memory, &n);
305 /* end of memory marker */
306 rsvd_region[n].start = ~0UL;
307 rsvd_region[n].end = ~0UL;
310 num_rsvd_regions = n;
311 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
313 sort_regions(rsvd_region, num_rsvd_regions);
318 * find_initrd - get initrd parameters from the boot parameter structure
320 * Grab the initrd start and end from the boot parameter struct given us by
326 #ifdef CONFIG_BLK_DEV_INITRD
327 if (ia64_boot_param->initrd_start) {
328 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
329 initrd_end = initrd_start+ia64_boot_param->initrd_size;
331 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
332 initrd_start, ia64_boot_param->initrd_size);
340 unsigned long phys_iobase;
343 * Set `iobase' based on the EFI memory map or, failing that, the
344 * value firmware left in ar.k0.
346 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
347 * the port's virtual address, so ia32_load_state() loads it with a
348 * user virtual address. But in ia64 mode, glibc uses the
349 * *physical* address in ar.k0 to mmap the appropriate area from
350 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
351 * cases, user-mode can only use the legacy 0-64K I/O port space.
353 * ar.k0 is not involved in kernel I/O port accesses, which can use
354 * any of the I/O port spaces and are done via MMIO using the
355 * virtual mmio_base from the appropriate io_space[].
357 phys_iobase = efi_get_iobase();
359 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
360 printk(KERN_INFO "No I/O port range found in EFI memory map, "
361 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
363 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
364 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
366 /* setup legacy IO port space */
367 io_space[0].mmio_base = ia64_iobase;
368 io_space[0].sparse = 1;
373 * early_console_setup - setup debugging console
375 * Consoles started here require little enough setup that we can start using
376 * them very early in the boot process, either right after the machine
377 * vector initialization, or even before if the drivers can detect their hw.
379 * Returns non-zero if a console couldn't be setup.
381 static inline int __init
382 early_console_setup (char *cmdline)
386 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
388 extern int sn_serial_console_early_setup(void);
389 if (!sn_serial_console_early_setup())
393 #ifdef CONFIG_EFI_PCDP
394 if (!efi_setup_pcdp_console(cmdline))
397 if (!simcons_register())
400 return (earlycons) ? 0 : -1;
404 mark_bsp_online (void)
407 /* If we register an early console, allow CPU 0 to printk */
408 cpu_set(smp_processor_id(), cpu_online_map);
414 check_for_logical_procs (void)
416 pal_logical_to_physical_t info;
419 status = ia64_pal_logical_to_phys(0, &info);
421 printk(KERN_INFO "No logical to physical processor mapping "
426 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
431 * Total number of siblings that BSP has. Though not all of them
432 * may have booted successfully. The correct number of siblings
433 * booted is in info.overview_num_log.
435 smp_num_siblings = info.overview_tpc;
436 smp_num_cpucores = info.overview_cpp;
440 static __initdata int nomca;
441 static __init int setup_nomca(char *s)
446 early_param("nomca", setup_nomca);
448 #ifdef CONFIG_PROC_VMCORE
449 /* elfcorehdr= specifies the location of elf core header
450 * stored by the crashed kernel.
452 static int __init parse_elfcorehdr(char *arg)
457 elfcorehdr_addr = memparse(arg, &arg);
460 early_param("elfcorehdr", parse_elfcorehdr);
462 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end)
464 unsigned long length;
466 /* We get the address using the kernel command line,
467 * but the size is extracted from the EFI tables.
468 * Both address and size are required for reservation
472 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX)
475 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) {
476 elfcorehdr_addr = ELFCORE_ADDR_MAX;
480 *start = (unsigned long)__va(elfcorehdr_addr);
481 *end = *start + length;
485 #endif /* CONFIG_PROC_VMCORE */
488 setup_arch (char **cmdline_p)
492 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
494 *cmdline_p = __va(ia64_boot_param->command_line);
495 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
500 #ifdef CONFIG_IA64_GENERIC
501 /* machvec needs to be parsed from the command line
502 * before parse_early_param() is called to ensure
503 * that ia64_mv is initialised before any command line
504 * settings may cause console setup to occur
506 machvec_init_from_cmdline(*cmdline_p);
511 if (early_console_setup(*cmdline_p) == 0)
515 /* Initialize the ACPI boot-time table parser */
517 # ifdef CONFIG_ACPI_NUMA
522 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
524 #endif /* CONFIG_APCI_BOOT */
528 /* process SAL system table: */
529 ia64_sal_init(__va(efi.sal_systab));
531 ia64_setup_printk_clock();
534 cpu_physical_id(0) = hard_smp_processor_id();
535 check_for_logical_procs();
536 if (smp_num_cpucores > 1)
538 "cpu package is Multi-Core capable: number of cores=%d\n",
540 if (smp_num_siblings > 1)
542 "cpu package is Multi-Threading capable: number of siblings=%d\n",
546 cpu_init(); /* initialize the bootstrap CPU */
547 mmu_context_init(); /* initialize context_id bitmap */
549 check_sal_cache_flush();
557 # if defined(CONFIG_DUMMY_CONSOLE)
558 conswitchp = &dummy_con;
560 # if defined(CONFIG_VGA_CONSOLE)
562 * Non-legacy systems may route legacy VGA MMIO range to system
563 * memory. vga_con probes the MMIO hole, so memory looks like
564 * a VGA device to it. The EFI memory map can tell us if it's
565 * memory so we can avoid this problem.
567 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
568 conswitchp = &vga_con;
573 /* enable IA-64 Machine Check Abort Handling unless disabled */
577 platform_setup(cmdline_p);
582 * Display cpu info for all CPUs.
585 show_cpuinfo (struct seq_file *m, void *v)
588 # define lpj c->loops_per_jiffy
589 # define cpunum c->cpu
591 # define lpj loops_per_jiffy
596 const char *feature_name;
598 { 1UL << 0, "branchlong" },
599 { 1UL << 1, "spontaneous deferral"},
600 { 1UL << 2, "16-byte atomic ops" }
602 char features[128], *cp, *sep;
603 struct cpuinfo_ia64 *c = v;
605 unsigned long proc_freq;
610 /* build the feature string: */
611 memcpy(features, "standard", 9);
613 size = sizeof(features);
615 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) {
616 if (mask & feature_bits[i].mask) {
617 cp += snprintf(cp, size, "%s%s", sep,
618 feature_bits[i].feature_name),
620 mask &= ~feature_bits[i].mask;
621 size = sizeof(features) - (cp - features);
624 if (mask && size > 1) {
625 /* print unknown features as a hex value */
626 snprintf(cp, size, "%s0x%lx", sep, mask);
629 proc_freq = cpufreq_quick_get(cpunum);
631 proc_freq = c->proc_freq / 1000;
645 "cpu MHz : %lu.%03lu\n"
646 "itc MHz : %lu.%06lu\n"
647 "BogoMIPS : %lu.%02lu\n",
648 cpunum, c->vendor, c->family, c->model,
649 c->model_name, c->revision, c->archrev,
650 features, c->ppn, c->number,
651 proc_freq / 1000, proc_freq % 1000,
652 c->itc_freq / 1000000, c->itc_freq % 1000000,
653 lpj*HZ/500000, (lpj*HZ/5000) % 100);
655 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
656 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
661 c->socket_id, c->core_id, c->thread_id);
669 c_start (struct seq_file *m, loff_t *pos)
672 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
675 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
679 c_next (struct seq_file *m, void *v, loff_t *pos)
682 return c_start(m, pos);
686 c_stop (struct seq_file *m, void *v)
690 struct seq_operations cpuinfo_op = {
698 static char brandname[MAX_BRANDS][128];
700 static char * __cpuinit
701 get_model_name(__u8 family, __u8 model)
707 memcpy(brand, "Unknown", 8);
708 if (ia64_pal_get_brand_info(brand)) {
710 memcpy(brand, "Merced", 7);
711 else if (family == 0x1f) switch (model) {
712 case 0: memcpy(brand, "McKinley", 9); break;
713 case 1: memcpy(brand, "Madison", 8); break;
714 case 2: memcpy(brand, "Madison up to 9M cache", 23); break;
717 for (i = 0; i < MAX_BRANDS; i++)
718 if (strcmp(brandname[i], brand) == 0)
720 for (i = 0; i < MAX_BRANDS; i++)
721 if (brandname[i][0] == '\0')
722 return strcpy(brandname[i], brand);
725 "%s: Table overflow. Some processor model information will be missing\n",
730 static void __cpuinit
731 identify_cpu (struct cpuinfo_ia64 *c)
734 unsigned long bits[5];
740 u64 ppn; /* processor serial number */
744 unsigned revision : 8;
747 unsigned archrev : 8;
748 unsigned reserved : 24;
754 pal_vm_info_1_u_t vm1;
755 pal_vm_info_2_u_t vm2;
757 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
759 for (i = 0; i < 5; ++i)
760 cpuid.bits[i] = ia64_get_cpuid(i);
762 memcpy(c->vendor, cpuid.field.vendor, 16);
764 c->cpu = smp_processor_id();
766 /* below default values will be overwritten by identify_siblings()
767 * for Multi-Threading/Multi-Core capable CPUs
769 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
772 identify_siblings(c);
774 c->ppn = cpuid.field.ppn;
775 c->number = cpuid.field.number;
776 c->revision = cpuid.field.revision;
777 c->model = cpuid.field.model;
778 c->family = cpuid.field.family;
779 c->archrev = cpuid.field.archrev;
780 c->features = cpuid.field.features;
781 c->model_name = get_model_name(c->family, c->model);
783 status = ia64_pal_vm_summary(&vm1, &vm2);
784 if (status == PAL_STATUS_SUCCESS) {
785 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
786 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
788 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
789 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
793 setup_per_cpu_areas (void)
795 /* start_kernel() requires this... */
796 #ifdef CONFIG_ACPI_HOTPLUG_CPU
797 prefill_possible_map();
802 * Calculate the max. cache line size.
804 * In addition, the minimum of the i-cache stride sizes is calculated for
805 * "flush_icache_range()".
807 static void __cpuinit
808 get_max_cacheline_size (void)
810 unsigned long line_size, max = 1;
811 u64 l, levels, unique_caches;
812 pal_cache_config_info_t cci;
815 status = ia64_pal_cache_summary(&levels, &unique_caches);
817 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
818 __FUNCTION__, status);
819 max = SMP_CACHE_BYTES;
820 /* Safest setup for "flush_icache_range()" */
821 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
825 for (l = 0; l < levels; ++l) {
826 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
830 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
831 __FUNCTION__, l, status);
832 max = SMP_CACHE_BYTES;
833 /* The safest setup for "flush_icache_range()" */
834 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
835 cci.pcci_unified = 1;
837 line_size = 1 << cci.pcci_line_size;
840 if (!cci.pcci_unified) {
841 status = ia64_pal_cache_config_info(l,
842 /* cache_type (instruction)= */ 1,
846 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
847 __FUNCTION__, l, status);
848 /* The safest setup for "flush_icache_range()" */
849 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
852 if (cci.pcci_stride < ia64_i_cache_stride_shift)
853 ia64_i_cache_stride_shift = cci.pcci_stride;
856 if (max > ia64_max_cacheline_size)
857 ia64_max_cacheline_size = max;
861 * cpu_init() initializes state that is per-CPU. This function acts
862 * as a 'CPU state barrier', nothing should get across.
867 extern void __cpuinit ia64_mmu_init (void *);
868 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
869 unsigned long num_phys_stacked;
870 pal_vm_info_2_u_t vmi;
871 unsigned int max_ctx;
872 struct cpuinfo_ia64 *cpu_info;
875 cpu_data = per_cpu_init();
878 * insert boot cpu into sibling and core mapes
879 * (must be done after per_cpu area is setup)
881 if (smp_processor_id() == 0) {
882 cpu_set(0, per_cpu(cpu_sibling_map, 0));
883 cpu_set(0, cpu_core_map[0]);
888 * We set ar.k3 so that assembly code in MCA handler can compute
889 * physical addresses of per cpu variables with a simple:
890 * phys = ar.k3 + &per_cpu_var
892 ia64_set_kr(IA64_KR_PER_CPU_DATA,
893 ia64_tpa(cpu_data) - (long) __per_cpu_start);
895 get_max_cacheline_size();
898 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
899 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
900 * depends on the data returned by identify_cpu(). We break the dependency by
901 * accessing cpu_data() through the canonical per-CPU address.
903 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
904 identify_cpu(cpu_info);
906 #ifdef CONFIG_MCKINLEY
908 # define FEATURE_SET 16
909 struct ia64_pal_retval iprv;
911 if (cpu_info->family == 0x1f) {
912 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
913 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
914 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
915 (iprv.v1 | 0x80), FEATURE_SET, 0);
920 /* Clear the stack memory reserved for pt_regs: */
921 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
923 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
926 * Initialize the page-table base register to a global
927 * directory with all zeroes. This ensure that we can handle
928 * TLB-misses to user address-space even before we created the
929 * first user address-space. This may happen, e.g., due to
930 * aggressive use of lfetch.fault.
932 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
935 * Initialize default control register to defer speculative faults except
936 * for those arising from TLB misses, which are not deferred. The
937 * kernel MUST NOT depend on a particular setting of these bits (in other words,
938 * the kernel must have recovery code for all speculative accesses). Turn on
939 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
940 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
943 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
944 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
945 atomic_inc(&init_mm.mm_count);
946 current->active_mm = &init_mm;
950 ia64_mmu_init(ia64_imva(cpu_data));
951 ia64_mca_cpu_init(ia64_imva(cpu_data));
953 #ifdef CONFIG_IA32_SUPPORT
957 /* Clear ITC to eliminate sched_clock() overflows in human time. */
960 /* disable all local interrupt sources: */
961 ia64_set_itv(1 << 16);
962 ia64_set_lrr0(1 << 16);
963 ia64_set_lrr1(1 << 16);
964 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
965 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
967 /* clear TPR & XTP to enable all interrupt classes: */
968 ia64_setreg(_IA64_REG_CR_TPR, 0);
970 /* Clear any pending interrupts left by SAL/EFI */
971 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
978 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
979 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
980 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
982 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
983 max_ctx = (1U << 15) - 1; /* use architected minimum */
985 while (max_ctx < ia64_ctx.max_ctx) {
986 unsigned int old = ia64_ctx.max_ctx;
987 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
991 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
992 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
994 num_phys_stacked = 96;
996 /* size of physical stacked register partition plus 8 bytes: */
997 if (num_phys_stacked > max_num_phys_stacked) {
998 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
999 max_num_phys_stacked = num_phys_stacked;
1001 platform_cpu_init();
1002 pm_idle = default_idle;
1008 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1009 (unsigned long) __end___mckinley_e9_bundles);
1012 static int __init run_dmi_scan(void)
1017 core_initcall(run_dmi_scan);