2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/dmi.h>
41 #include <linux/serial.h>
42 #include <linux/serial_core.h>
43 #include <linux/efi.h>
44 #include <linux/initrd.h>
46 #include <linux/cpufreq.h>
49 #include <asm/machvec.h>
51 #include <asm/meminit.h>
53 #include <asm/patch.h>
54 #include <asm/pgtable.h>
55 #include <asm/processor.h>
57 #include <asm/sections.h>
58 #include <asm/serial.h>
59 #include <asm/setup.h>
61 #include <asm/system.h>
62 #include <asm/unistd.h>
63 #include <asm/system.h>
65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
66 # error "struct cpuinfo_ia64 too big!"
70 unsigned long __per_cpu_offset[NR_CPUS];
71 EXPORT_SYMBOL(__per_cpu_offset);
74 extern void ia64_setup_printk_clock(void);
76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
78 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
79 unsigned long ia64_cycles_per_usec;
80 struct ia64_boot_param *ia64_boot_param;
81 struct screen_info screen_info;
82 unsigned long vga_console_iobase;
83 unsigned long vga_console_membase;
85 static struct resource data_resource = {
86 .name = "Kernel data",
87 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
90 static struct resource code_resource = {
91 .name = "Kernel code",
92 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
94 extern void efi_initialize_iomem_resources(struct resource *,
96 extern char _text[], _end[], _etext[];
98 unsigned long ia64_max_cacheline_size;
100 int dma_get_cache_alignment(void)
102 return ia64_max_cacheline_size;
104 EXPORT_SYMBOL(dma_get_cache_alignment);
106 unsigned long ia64_iobase; /* virtual address for I/O accesses */
107 EXPORT_SYMBOL(ia64_iobase);
108 struct io_space io_space[MAX_IO_SPACES];
109 EXPORT_SYMBOL(io_space);
110 unsigned int num_io_spaces;
113 * "flush_icache_range()" needs to know what processor dependent stride size to use
114 * when it makes i-cache(s) coherent with d-caches.
116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
117 unsigned long ia64_i_cache_stride_shift = ~0;
120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
123 * address of the second buffer must be aligned to (merge_mask+1) in order to be
124 * mergeable). By default, we assume there is no I/O MMU which can merge physically
125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
128 unsigned long ia64_max_iommu_merge_mask = ~0UL;
129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
132 * We use a special marker for the end of memory and it uses the extra (+1) slot
134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
135 int num_rsvd_regions __initdata;
139 * Filter incoming memory segments based on the primitive map created from the boot
140 * parameters. Segments contained in the map are removed from the memory ranges. A
141 * caller-specified function is called with the memory ranges that remain after filtering.
142 * This routine does not assume the incoming segments are sorted.
145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
147 unsigned long range_start, range_end, prev_start;
148 void (*func)(unsigned long, unsigned long, int);
152 if (start == PAGE_OFFSET) {
153 printk(KERN_WARNING "warning: skipping physical page 0\n");
155 if (start >= end) return 0;
159 * lowest possible address(walker uses virtual)
161 prev_start = PAGE_OFFSET;
164 for (i = 0; i < num_rsvd_regions; ++i) {
165 range_start = max(start, prev_start);
166 range_end = min(end, rsvd_region[i].start);
168 if (range_start < range_end)
169 call_pernode_memory(__pa(range_start), range_end - range_start, func);
171 /* nothing more available in this segment */
172 if (range_end == end) return 0;
174 prev_start = rsvd_region[i].end;
176 /* end of memory marker allows full processing inside loop body */
181 sort_regions (struct rsvd_region *rsvd_region, int max)
185 /* simple bubble sorting */
187 for (j = 0; j < max; ++j) {
188 if (rsvd_region[j].start > rsvd_region[j+1].start) {
189 struct rsvd_region tmp;
190 tmp = rsvd_region[j];
191 rsvd_region[j] = rsvd_region[j + 1];
192 rsvd_region[j + 1] = tmp;
199 * Request address space for all standard resources
201 static int __init register_memory(void)
203 code_resource.start = ia64_tpa(_text);
204 code_resource.end = ia64_tpa(_etext) - 1;
205 data_resource.start = ia64_tpa(_etext);
206 data_resource.end = ia64_tpa(_end) - 1;
207 efi_initialize_iomem_resources(&code_resource, &data_resource);
212 __initcall(register_memory);
215 * reserve_memory - setup reserved memory areas
217 * Setup the reserved memory areas set aside for the boot parameters,
218 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
219 * see include/asm-ia64/meminit.h if you need to define more.
222 reserve_memory (void)
227 * none of the entries in this table overlap
229 rsvd_region[n].start = (unsigned long) ia64_boot_param;
230 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
233 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
234 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
237 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
238 rsvd_region[n].end = (rsvd_region[n].start
239 + strlen(__va(ia64_boot_param->command_line)) + 1);
242 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
243 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
246 #ifdef CONFIG_BLK_DEV_INITRD
247 if (ia64_boot_param->initrd_start) {
248 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
249 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
254 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
257 /* end of memory marker */
258 rsvd_region[n].start = ~0UL;
259 rsvd_region[n].end = ~0UL;
262 num_rsvd_regions = n;
263 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
265 sort_regions(rsvd_region, num_rsvd_regions);
269 * find_initrd - get initrd parameters from the boot parameter structure
271 * Grab the initrd start and end from the boot parameter struct given us by
277 #ifdef CONFIG_BLK_DEV_INITRD
278 if (ia64_boot_param->initrd_start) {
279 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
280 initrd_end = initrd_start+ia64_boot_param->initrd_size;
282 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
283 initrd_start, ia64_boot_param->initrd_size);
291 unsigned long phys_iobase;
294 * Set `iobase' based on the EFI memory map or, failing that, the
295 * value firmware left in ar.k0.
297 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
298 * the port's virtual address, so ia32_load_state() loads it with a
299 * user virtual address. But in ia64 mode, glibc uses the
300 * *physical* address in ar.k0 to mmap the appropriate area from
301 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
302 * cases, user-mode can only use the legacy 0-64K I/O port space.
304 * ar.k0 is not involved in kernel I/O port accesses, which can use
305 * any of the I/O port spaces and are done via MMIO using the
306 * virtual mmio_base from the appropriate io_space[].
308 phys_iobase = efi_get_iobase();
310 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
311 printk(KERN_INFO "No I/O port range found in EFI memory map, "
312 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
314 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
315 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
317 /* setup legacy IO port space */
318 io_space[0].mmio_base = ia64_iobase;
319 io_space[0].sparse = 1;
324 * early_console_setup - setup debugging console
326 * Consoles started here require little enough setup that we can start using
327 * them very early in the boot process, either right after the machine
328 * vector initialization, or even before if the drivers can detect their hw.
330 * Returns non-zero if a console couldn't be setup.
332 static inline int __init
333 early_console_setup (char *cmdline)
337 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
339 extern int sn_serial_console_early_setup(void);
340 if (!sn_serial_console_early_setup())
344 #ifdef CONFIG_EFI_PCDP
345 if (!efi_setup_pcdp_console(cmdline))
348 #ifdef CONFIG_SERIAL_8250_CONSOLE
349 if (!early_serial_console_init(cmdline))
353 return (earlycons) ? 0 : -1;
357 mark_bsp_online (void)
360 /* If we register an early console, allow CPU 0 to printk */
361 cpu_set(smp_processor_id(), cpu_online_map);
367 check_for_logical_procs (void)
369 pal_logical_to_physical_t info;
372 status = ia64_pal_logical_to_phys(0, &info);
374 printk(KERN_INFO "No logical to physical processor mapping "
379 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
384 * Total number of siblings that BSP has. Though not all of them
385 * may have booted successfully. The correct number of siblings
386 * booted is in info.overview_num_log.
388 smp_num_siblings = info.overview_tpc;
389 smp_num_cpucores = info.overview_cpp;
393 static __initdata int nomca;
394 static __init int setup_nomca(char *s)
399 early_param("nomca", setup_nomca);
402 setup_arch (char **cmdline_p)
406 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
408 *cmdline_p = __va(ia64_boot_param->command_line);
409 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
416 #ifdef CONFIG_IA64_GENERIC
420 if (early_console_setup(*cmdline_p) == 0)
424 /* Initialize the ACPI boot-time table parser */
426 # ifdef CONFIG_ACPI_NUMA
431 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
433 #endif /* CONFIG_APCI_BOOT */
437 /* process SAL system table: */
438 ia64_sal_init(__va(efi.sal_systab));
440 ia64_setup_printk_clock();
443 cpu_physical_id(0) = hard_smp_processor_id();
445 cpu_set(0, cpu_sibling_map[0]);
446 cpu_set(0, cpu_core_map[0]);
448 check_for_logical_procs();
449 if (smp_num_cpucores > 1)
451 "cpu package is Multi-Core capable: number of cores=%d\n",
453 if (smp_num_siblings > 1)
455 "cpu package is Multi-Threading capable: number of siblings=%d\n",
459 cpu_init(); /* initialize the bootstrap CPU */
460 mmu_context_init(); /* initialize context_id bitmap */
468 # if defined(CONFIG_DUMMY_CONSOLE)
469 conswitchp = &dummy_con;
471 # if defined(CONFIG_VGA_CONSOLE)
473 * Non-legacy systems may route legacy VGA MMIO range to system
474 * memory. vga_con probes the MMIO hole, so memory looks like
475 * a VGA device to it. The EFI memory map can tell us if it's
476 * memory so we can avoid this problem.
478 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
479 conswitchp = &vga_con;
484 /* enable IA-64 Machine Check Abort Handling unless disabled */
488 platform_setup(cmdline_p);
493 * Display cpu info for all cpu's.
496 show_cpuinfo (struct seq_file *m, void *v)
499 # define lpj c->loops_per_jiffy
500 # define cpunum c->cpu
502 # define lpj loops_per_jiffy
507 const char *feature_name;
509 { 1UL << 0, "branchlong" },
510 { 1UL << 1, "spontaneous deferral"},
511 { 1UL << 2, "16-byte atomic ops" }
513 char family[32], features[128], *cp, sep;
514 struct cpuinfo_ia64 *c = v;
516 unsigned long proc_freq;
522 case 0x07: memcpy(family, "Itanium", 8); break;
523 case 0x1f: memcpy(family, "Itanium 2", 10); break;
524 default: sprintf(family, "%u", c->family); break;
527 /* build the feature string: */
528 memcpy(features, " standard", 10);
531 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
532 if (mask & feature_bits[i].mask) {
537 strcpy(cp, feature_bits[i].feature_name);
538 cp += strlen(feature_bits[i].feature_name);
539 mask &= ~feature_bits[i].mask;
543 /* print unknown features as a hex value: */
546 sprintf(cp, " 0x%lx", mask);
549 proc_freq = cpufreq_quick_get(cpunum);
551 proc_freq = c->proc_freq / 1000;
561 "features :%s\n" /* don't change this---it _is_ right! */
564 "cpu MHz : %lu.%06lu\n"
565 "itc MHz : %lu.%06lu\n"
566 "BogoMIPS : %lu.%02lu\n",
567 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
568 features, c->ppn, c->number,
569 proc_freq / 1000, proc_freq % 1000,
570 c->itc_freq / 1000000, c->itc_freq % 1000000,
571 lpj*HZ/500000, (lpj*HZ/5000) % 100);
573 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
574 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
579 c->socket_id, c->core_id, c->thread_id);
587 c_start (struct seq_file *m, loff_t *pos)
590 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
593 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
597 c_next (struct seq_file *m, void *v, loff_t *pos)
600 return c_start(m, pos);
604 c_stop (struct seq_file *m, void *v)
608 struct seq_operations cpuinfo_op = {
615 static void __cpuinit
616 identify_cpu (struct cpuinfo_ia64 *c)
619 unsigned long bits[5];
625 u64 ppn; /* processor serial number */
629 unsigned revision : 8;
632 unsigned archrev : 8;
633 unsigned reserved : 24;
639 pal_vm_info_1_u_t vm1;
640 pal_vm_info_2_u_t vm2;
642 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
645 for (i = 0; i < 5; ++i)
646 cpuid.bits[i] = ia64_get_cpuid(i);
648 memcpy(c->vendor, cpuid.field.vendor, 16);
650 c->cpu = smp_processor_id();
652 /* below default values will be overwritten by identify_siblings()
653 * for Multi-Threading/Multi-Core capable cpu's
655 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
658 identify_siblings(c);
660 c->ppn = cpuid.field.ppn;
661 c->number = cpuid.field.number;
662 c->revision = cpuid.field.revision;
663 c->model = cpuid.field.model;
664 c->family = cpuid.field.family;
665 c->archrev = cpuid.field.archrev;
666 c->features = cpuid.field.features;
668 status = ia64_pal_vm_summary(&vm1, &vm2);
669 if (status == PAL_STATUS_SUCCESS) {
670 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
671 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
673 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
674 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
678 setup_per_cpu_areas (void)
680 /* start_kernel() requires this... */
681 #ifdef CONFIG_ACPI_HOTPLUG_CPU
682 prefill_possible_map();
687 * Calculate the max. cache line size.
689 * In addition, the minimum of the i-cache stride sizes is calculated for
690 * "flush_icache_range()".
692 static void __cpuinit
693 get_max_cacheline_size (void)
695 unsigned long line_size, max = 1;
696 unsigned int cache_size = 0;
697 u64 l, levels, unique_caches;
698 pal_cache_config_info_t cci;
701 status = ia64_pal_cache_summary(&levels, &unique_caches);
703 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
704 __FUNCTION__, status);
705 max = SMP_CACHE_BYTES;
706 /* Safest setup for "flush_icache_range()" */
707 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
711 for (l = 0; l < levels; ++l) {
712 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
716 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
717 __FUNCTION__, l, status);
718 max = SMP_CACHE_BYTES;
719 /* The safest setup for "flush_icache_range()" */
720 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
721 cci.pcci_unified = 1;
723 line_size = 1 << cci.pcci_line_size;
726 if (cache_size < cci.pcci_cache_size)
727 cache_size = cci.pcci_cache_size;
728 if (!cci.pcci_unified) {
729 status = ia64_pal_cache_config_info(l,
730 /* cache_type (instruction)= */ 1,
734 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
735 __FUNCTION__, l, status);
736 /* The safest setup for "flush_icache_range()" */
737 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
740 if (cci.pcci_stride < ia64_i_cache_stride_shift)
741 ia64_i_cache_stride_shift = cci.pcci_stride;
745 max_cache_size = max(max_cache_size, cache_size);
747 if (max > ia64_max_cacheline_size)
748 ia64_max_cacheline_size = max;
752 * cpu_init() initializes state that is per-CPU. This function acts
753 * as a 'CPU state barrier', nothing should get across.
758 extern void __cpuinit ia64_mmu_init (void *);
759 unsigned long num_phys_stacked;
760 pal_vm_info_2_u_t vmi;
761 unsigned int max_ctx;
762 struct cpuinfo_ia64 *cpu_info;
765 cpu_data = per_cpu_init();
768 * We set ar.k3 so that assembly code in MCA handler can compute
769 * physical addresses of per cpu variables with a simple:
770 * phys = ar.k3 + &per_cpu_var
772 ia64_set_kr(IA64_KR_PER_CPU_DATA,
773 ia64_tpa(cpu_data) - (long) __per_cpu_start);
775 get_max_cacheline_size();
778 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
779 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
780 * depends on the data returned by identify_cpu(). We break the dependency by
781 * accessing cpu_data() through the canonical per-CPU address.
783 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
784 identify_cpu(cpu_info);
786 #ifdef CONFIG_MCKINLEY
788 # define FEATURE_SET 16
789 struct ia64_pal_retval iprv;
791 if (cpu_info->family == 0x1f) {
792 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
793 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
794 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
795 (iprv.v1 | 0x80), FEATURE_SET, 0);
800 /* Clear the stack memory reserved for pt_regs: */
801 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
803 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
806 * Initialize the page-table base register to a global
807 * directory with all zeroes. This ensure that we can handle
808 * TLB-misses to user address-space even before we created the
809 * first user address-space. This may happen, e.g., due to
810 * aggressive use of lfetch.fault.
812 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
815 * Initialize default control register to defer speculative faults except
816 * for those arising from TLB misses, which are not deferred. The
817 * kernel MUST NOT depend on a particular setting of these bits (in other words,
818 * the kernel must have recovery code for all speculative accesses). Turn on
819 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
820 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
823 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
824 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
825 atomic_inc(&init_mm.mm_count);
826 current->active_mm = &init_mm;
830 ia64_mmu_init(ia64_imva(cpu_data));
831 ia64_mca_cpu_init(ia64_imva(cpu_data));
833 #ifdef CONFIG_IA32_SUPPORT
837 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
840 /* disable all local interrupt sources: */
841 ia64_set_itv(1 << 16);
842 ia64_set_lrr0(1 << 16);
843 ia64_set_lrr1(1 << 16);
844 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
845 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
847 /* clear TPR & XTP to enable all interrupt classes: */
848 ia64_setreg(_IA64_REG_CR_TPR, 0);
853 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
854 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
855 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
857 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
858 max_ctx = (1U << 15) - 1; /* use architected minimum */
860 while (max_ctx < ia64_ctx.max_ctx) {
861 unsigned int old = ia64_ctx.max_ctx;
862 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
866 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
867 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
869 num_phys_stacked = 96;
871 /* size of physical stacked register partition plus 8 bytes: */
872 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
874 pm_idle = default_idle;
878 * On SMP systems, when the scheduler does migration-cost autodetection,
879 * it needs a way to flush as much of the CPU's caches as possible.
881 void sched_cacheflush(void)
883 ia64_sal_cache_flush(3);
889 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
890 (unsigned long) __end___mckinley_e9_bundles);
893 static int __init run_dmi_scan(void)
898 core_initcall(run_dmi_scan);