2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/screen_info.h>
39 #include <linux/dmi.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
45 #include <linux/cpufreq.h>
46 #include <linux/kexec.h>
47 #include <linux/crash_dump.h>
50 #include <asm/machvec.h>
52 #include <asm/meminit.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
58 #include <asm/sections.h>
59 #include <asm/setup.h>
61 #include <asm/system.h>
62 #include <asm/unistd.h>
63 #include <asm/hpsim.h>
65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
66 # error "struct cpuinfo_ia64 too big!"
70 unsigned long __per_cpu_offset[NR_CPUS];
71 EXPORT_SYMBOL(__per_cpu_offset);
74 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
75 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
76 unsigned long ia64_cycles_per_usec;
77 struct ia64_boot_param *ia64_boot_param;
78 struct screen_info screen_info;
79 unsigned long vga_console_iobase;
80 unsigned long vga_console_membase;
82 static struct resource data_resource = {
83 .name = "Kernel data",
84 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
87 static struct resource code_resource = {
88 .name = "Kernel code",
89 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
92 static struct resource bss_resource = {
94 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
97 unsigned long ia64_max_cacheline_size;
99 int dma_get_cache_alignment(void)
101 return ia64_max_cacheline_size;
103 EXPORT_SYMBOL(dma_get_cache_alignment);
105 unsigned long ia64_iobase; /* virtual address for I/O accesses */
106 EXPORT_SYMBOL(ia64_iobase);
107 struct io_space io_space[MAX_IO_SPACES];
108 EXPORT_SYMBOL(io_space);
109 unsigned int num_io_spaces;
112 * "flush_icache_range()" needs to know what processor dependent stride size to use
113 * when it makes i-cache(s) coherent with d-caches.
115 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
116 unsigned long ia64_i_cache_stride_shift = ~0;
119 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
120 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
121 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
122 * address of the second buffer must be aligned to (merge_mask+1) in order to be
123 * mergeable). By default, we assume there is no I/O MMU which can merge physically
124 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
127 unsigned long ia64_max_iommu_merge_mask = ~0UL;
128 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
131 * We use a special marker for the end of memory and it uses the extra (+1) slot
133 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
134 int num_rsvd_regions __initdata;
138 * Filter incoming memory segments based on the primitive map created from the boot
139 * parameters. Segments contained in the map are removed from the memory ranges. A
140 * caller-specified function is called with the memory ranges that remain after filtering.
141 * This routine does not assume the incoming segments are sorted.
144 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
146 unsigned long range_start, range_end, prev_start;
147 void (*func)(unsigned long, unsigned long, int);
151 if (start == PAGE_OFFSET) {
152 printk(KERN_WARNING "warning: skipping physical page 0\n");
154 if (start >= end) return 0;
158 * lowest possible address(walker uses virtual)
160 prev_start = PAGE_OFFSET;
163 for (i = 0; i < num_rsvd_regions; ++i) {
164 range_start = max(start, prev_start);
165 range_end = min(end, rsvd_region[i].start);
167 if (range_start < range_end)
168 call_pernode_memory(__pa(range_start), range_end - range_start, func);
170 /* nothing more available in this segment */
171 if (range_end == end) return 0;
173 prev_start = rsvd_region[i].end;
175 /* end of memory marker allows full processing inside loop body */
180 sort_regions (struct rsvd_region *rsvd_region, int max)
184 /* simple bubble sorting */
186 for (j = 0; j < max; ++j) {
187 if (rsvd_region[j].start > rsvd_region[j+1].start) {
188 struct rsvd_region tmp;
189 tmp = rsvd_region[j];
190 rsvd_region[j] = rsvd_region[j + 1];
191 rsvd_region[j + 1] = tmp;
198 * Request address space for all standard resources
200 static int __init register_memory(void)
202 code_resource.start = ia64_tpa(_text);
203 code_resource.end = ia64_tpa(_etext) - 1;
204 data_resource.start = ia64_tpa(_etext);
205 data_resource.end = ia64_tpa(_edata) - 1;
206 bss_resource.start = ia64_tpa(__bss_start);
207 bss_resource.end = ia64_tpa(_end) - 1;
208 efi_initialize_iomem_resources(&code_resource, &data_resource,
214 __initcall(register_memory);
218 static void __init setup_crashkernel(unsigned long total, int *n)
220 unsigned long long base = 0, size = 0;
223 ret = parse_crashkernel(boot_command_line, total,
225 if (ret == 0 && size > 0) {
227 sort_regions(rsvd_region, *n);
228 base = kdump_find_rsvd_region(size,
232 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
233 "for crashkernel (System RAM: %ldMB)\n",
234 (unsigned long)(size >> 20),
235 (unsigned long)(base >> 20),
236 (unsigned long)(total >> 20));
237 rsvd_region[*n].start =
238 (unsigned long)__va(base);
239 rsvd_region[*n].end =
240 (unsigned long)__va(base + size);
242 crashk_res.start = base;
243 crashk_res.end = base + size - 1;
246 efi_memmap_res.start = ia64_boot_param->efi_memmap;
247 efi_memmap_res.end = efi_memmap_res.start +
248 ia64_boot_param->efi_memmap_size;
249 boot_param_res.start = __pa(ia64_boot_param);
250 boot_param_res.end = boot_param_res.start +
251 sizeof(*ia64_boot_param);
254 static inline void __init setup_crashkernel(unsigned long total, int *n)
259 * reserve_memory - setup reserved memory areas
261 * Setup the reserved memory areas set aside for the boot parameters,
262 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
263 * see include/asm-ia64/meminit.h if you need to define more.
266 reserve_memory (void)
269 unsigned long total_memory;
272 * none of the entries in this table overlap
274 rsvd_region[n].start = (unsigned long) ia64_boot_param;
275 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
278 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
279 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
282 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
283 rsvd_region[n].end = (rsvd_region[n].start
284 + strlen(__va(ia64_boot_param->command_line)) + 1);
287 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
288 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
291 #ifdef CONFIG_BLK_DEV_INITRD
292 if (ia64_boot_param->initrd_start) {
293 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
294 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
299 #ifdef CONFIG_PROC_VMCORE
300 if (reserve_elfcorehdr(&rsvd_region[n].start,
301 &rsvd_region[n].end) == 0)
305 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
308 setup_crashkernel(total_memory, &n);
310 /* end of memory marker */
311 rsvd_region[n].start = ~0UL;
312 rsvd_region[n].end = ~0UL;
315 num_rsvd_regions = n;
316 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
318 sort_regions(rsvd_region, num_rsvd_regions);
323 * find_initrd - get initrd parameters from the boot parameter structure
325 * Grab the initrd start and end from the boot parameter struct given us by
331 #ifdef CONFIG_BLK_DEV_INITRD
332 if (ia64_boot_param->initrd_start) {
333 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
334 initrd_end = initrd_start+ia64_boot_param->initrd_size;
336 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
337 initrd_start, ia64_boot_param->initrd_size);
345 unsigned long phys_iobase;
348 * Set `iobase' based on the EFI memory map or, failing that, the
349 * value firmware left in ar.k0.
351 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
352 * the port's virtual address, so ia32_load_state() loads it with a
353 * user virtual address. But in ia64 mode, glibc uses the
354 * *physical* address in ar.k0 to mmap the appropriate area from
355 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
356 * cases, user-mode can only use the legacy 0-64K I/O port space.
358 * ar.k0 is not involved in kernel I/O port accesses, which can use
359 * any of the I/O port spaces and are done via MMIO using the
360 * virtual mmio_base from the appropriate io_space[].
362 phys_iobase = efi_get_iobase();
364 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
365 printk(KERN_INFO "No I/O port range found in EFI memory map, "
366 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
368 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
369 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
371 /* setup legacy IO port space */
372 io_space[0].mmio_base = ia64_iobase;
373 io_space[0].sparse = 1;
378 * early_console_setup - setup debugging console
380 * Consoles started here require little enough setup that we can start using
381 * them very early in the boot process, either right after the machine
382 * vector initialization, or even before if the drivers can detect their hw.
384 * Returns non-zero if a console couldn't be setup.
386 static inline int __init
387 early_console_setup (char *cmdline)
391 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
393 extern int sn_serial_console_early_setup(void);
394 if (!sn_serial_console_early_setup())
398 #ifdef CONFIG_EFI_PCDP
399 if (!efi_setup_pcdp_console(cmdline))
402 if (!simcons_register())
405 return (earlycons) ? 0 : -1;
409 mark_bsp_online (void)
412 /* If we register an early console, allow CPU 0 to printk */
413 cpu_set(smp_processor_id(), cpu_online_map);
417 static __initdata int nomca;
418 static __init int setup_nomca(char *s)
423 early_param("nomca", setup_nomca);
425 #ifdef CONFIG_PROC_VMCORE
426 /* elfcorehdr= specifies the location of elf core header
427 * stored by the crashed kernel.
429 static int __init parse_elfcorehdr(char *arg)
434 elfcorehdr_addr = memparse(arg, &arg);
437 early_param("elfcorehdr", parse_elfcorehdr);
439 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end)
441 unsigned long length;
443 /* We get the address using the kernel command line,
444 * but the size is extracted from the EFI tables.
445 * Both address and size are required for reservation
449 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX)
452 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) {
453 elfcorehdr_addr = ELFCORE_ADDR_MAX;
457 *start = (unsigned long)__va(elfcorehdr_addr);
458 *end = *start + length;
462 #endif /* CONFIG_PROC_VMCORE */
465 setup_arch (char **cmdline_p)
469 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
471 *cmdline_p = __va(ia64_boot_param->command_line);
472 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
477 #ifdef CONFIG_IA64_GENERIC
478 /* machvec needs to be parsed from the command line
479 * before parse_early_param() is called to ensure
480 * that ia64_mv is initialised before any command line
481 * settings may cause console setup to occur
483 machvec_init_from_cmdline(*cmdline_p);
488 if (early_console_setup(*cmdline_p) == 0)
492 /* Initialize the ACPI boot-time table parser */
494 # ifdef CONFIG_ACPI_NUMA
496 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ?
497 32 : cpus_weight(early_cpu_possible_map)), additional_cpus);
501 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
503 #endif /* CONFIG_APCI_BOOT */
507 /* process SAL system table: */
508 ia64_sal_init(__va(efi.sal_systab));
511 cpu_physical_id(0) = hard_smp_processor_id();
514 cpu_init(); /* initialize the bootstrap CPU */
515 mmu_context_init(); /* initialize context_id bitmap */
517 check_sal_cache_flush();
525 # if defined(CONFIG_DUMMY_CONSOLE)
526 conswitchp = &dummy_con;
528 # if defined(CONFIG_VGA_CONSOLE)
530 * Non-legacy systems may route legacy VGA MMIO range to system
531 * memory. vga_con probes the MMIO hole, so memory looks like
532 * a VGA device to it. The EFI memory map can tell us if it's
533 * memory so we can avoid this problem.
535 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
536 conswitchp = &vga_con;
541 /* enable IA-64 Machine Check Abort Handling unless disabled */
545 platform_setup(cmdline_p);
550 * Display cpu info for all CPUs.
553 show_cpuinfo (struct seq_file *m, void *v)
556 # define lpj c->loops_per_jiffy
557 # define cpunum c->cpu
559 # define lpj loops_per_jiffy
564 const char *feature_name;
566 { 1UL << 0, "branchlong" },
567 { 1UL << 1, "spontaneous deferral"},
568 { 1UL << 2, "16-byte atomic ops" }
570 char features[128], *cp, *sep;
571 struct cpuinfo_ia64 *c = v;
573 unsigned long proc_freq;
578 /* build the feature string: */
579 memcpy(features, "standard", 9);
581 size = sizeof(features);
583 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) {
584 if (mask & feature_bits[i].mask) {
585 cp += snprintf(cp, size, "%s%s", sep,
586 feature_bits[i].feature_name),
588 mask &= ~feature_bits[i].mask;
589 size = sizeof(features) - (cp - features);
592 if (mask && size > 1) {
593 /* print unknown features as a hex value */
594 snprintf(cp, size, "%s0x%lx", sep, mask);
597 proc_freq = cpufreq_quick_get(cpunum);
599 proc_freq = c->proc_freq / 1000;
613 "cpu MHz : %lu.%03lu\n"
614 "itc MHz : %lu.%06lu\n"
615 "BogoMIPS : %lu.%02lu\n",
616 cpunum, c->vendor, c->family, c->model,
617 c->model_name, c->revision, c->archrev,
618 features, c->ppn, c->number,
619 proc_freq / 1000, proc_freq % 1000,
620 c->itc_freq / 1000000, c->itc_freq % 1000000,
621 lpj*HZ/500000, (lpj*HZ/5000) % 100);
623 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
624 if (c->socket_id != -1)
625 seq_printf(m, "physical id: %u\n", c->socket_id);
626 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
630 c->core_id, c->thread_id);
638 c_start (struct seq_file *m, loff_t *pos)
641 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
644 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
648 c_next (struct seq_file *m, void *v, loff_t *pos)
651 return c_start(m, pos);
655 c_stop (struct seq_file *m, void *v)
659 const struct seq_operations cpuinfo_op = {
667 static char brandname[MAX_BRANDS][128];
669 static char * __cpuinit
670 get_model_name(__u8 family, __u8 model)
676 memcpy(brand, "Unknown", 8);
677 if (ia64_pal_get_brand_info(brand)) {
679 memcpy(brand, "Merced", 7);
680 else if (family == 0x1f) switch (model) {
681 case 0: memcpy(brand, "McKinley", 9); break;
682 case 1: memcpy(brand, "Madison", 8); break;
683 case 2: memcpy(brand, "Madison up to 9M cache", 23); break;
686 for (i = 0; i < MAX_BRANDS; i++)
687 if (strcmp(brandname[i], brand) == 0)
689 for (i = 0; i < MAX_BRANDS; i++)
690 if (brandname[i][0] == '\0')
691 return strcpy(brandname[i], brand);
694 "%s: Table overflow. Some processor model information will be missing\n",
699 static void __cpuinit
700 identify_cpu (struct cpuinfo_ia64 *c)
703 unsigned long bits[5];
709 u64 ppn; /* processor serial number */
713 unsigned revision : 8;
716 unsigned archrev : 8;
717 unsigned reserved : 24;
723 pal_vm_info_1_u_t vm1;
724 pal_vm_info_2_u_t vm2;
726 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
728 for (i = 0; i < 5; ++i)
729 cpuid.bits[i] = ia64_get_cpuid(i);
731 memcpy(c->vendor, cpuid.field.vendor, 16);
733 c->cpu = smp_processor_id();
735 /* below default values will be overwritten by identify_siblings()
736 * for Multi-Threading/Multi-Core capable CPUs
738 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
741 identify_siblings(c);
743 if (c->threads_per_core > smp_num_siblings)
744 smp_num_siblings = c->threads_per_core;
746 c->ppn = cpuid.field.ppn;
747 c->number = cpuid.field.number;
748 c->revision = cpuid.field.revision;
749 c->model = cpuid.field.model;
750 c->family = cpuid.field.family;
751 c->archrev = cpuid.field.archrev;
752 c->features = cpuid.field.features;
753 c->model_name = get_model_name(c->family, c->model);
755 status = ia64_pal_vm_summary(&vm1, &vm2);
756 if (status == PAL_STATUS_SUCCESS) {
757 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
758 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
760 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
761 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
765 setup_per_cpu_areas (void)
767 /* start_kernel() requires this... */
768 #ifdef CONFIG_ACPI_HOTPLUG_CPU
769 prefill_possible_map();
774 * Calculate the max. cache line size.
776 * In addition, the minimum of the i-cache stride sizes is calculated for
777 * "flush_icache_range()".
779 static void __cpuinit
780 get_max_cacheline_size (void)
782 unsigned long line_size, max = 1;
783 u64 l, levels, unique_caches;
784 pal_cache_config_info_t cci;
787 status = ia64_pal_cache_summary(&levels, &unique_caches);
789 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
791 max = SMP_CACHE_BYTES;
792 /* Safest setup for "flush_icache_range()" */
793 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
797 for (l = 0; l < levels; ++l) {
798 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
802 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
803 __func__, l, status);
804 max = SMP_CACHE_BYTES;
805 /* The safest setup for "flush_icache_range()" */
806 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
807 cci.pcci_unified = 1;
809 line_size = 1 << cci.pcci_line_size;
812 if (!cci.pcci_unified) {
813 status = ia64_pal_cache_config_info(l,
814 /* cache_type (instruction)= */ 1,
818 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
819 __func__, l, status);
820 /* The safest setup for "flush_icache_range()" */
821 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
824 if (cci.pcci_stride < ia64_i_cache_stride_shift)
825 ia64_i_cache_stride_shift = cci.pcci_stride;
828 if (max > ia64_max_cacheline_size)
829 ia64_max_cacheline_size = max;
833 * cpu_init() initializes state that is per-CPU. This function acts
834 * as a 'CPU state barrier', nothing should get across.
839 extern void __cpuinit ia64_mmu_init (void *);
840 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
841 unsigned long num_phys_stacked;
842 pal_vm_info_2_u_t vmi;
843 unsigned int max_ctx;
844 struct cpuinfo_ia64 *cpu_info;
847 cpu_data = per_cpu_init();
850 * insert boot cpu into sibling and core mapes
851 * (must be done after per_cpu area is setup)
853 if (smp_processor_id() == 0) {
854 cpu_set(0, per_cpu(cpu_sibling_map, 0));
855 cpu_set(0, cpu_core_map[0]);
860 * We set ar.k3 so that assembly code in MCA handler can compute
861 * physical addresses of per cpu variables with a simple:
862 * phys = ar.k3 + &per_cpu_var
864 ia64_set_kr(IA64_KR_PER_CPU_DATA,
865 ia64_tpa(cpu_data) - (long) __per_cpu_start);
867 get_max_cacheline_size();
870 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
871 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
872 * depends on the data returned by identify_cpu(). We break the dependency by
873 * accessing cpu_data() through the canonical per-CPU address.
875 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
876 identify_cpu(cpu_info);
878 #ifdef CONFIG_MCKINLEY
880 # define FEATURE_SET 16
881 struct ia64_pal_retval iprv;
883 if (cpu_info->family == 0x1f) {
884 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
885 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
886 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
887 (iprv.v1 | 0x80), FEATURE_SET, 0);
892 /* Clear the stack memory reserved for pt_regs: */
893 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
895 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
898 * Initialize the page-table base register to a global
899 * directory with all zeroes. This ensure that we can handle
900 * TLB-misses to user address-space even before we created the
901 * first user address-space. This may happen, e.g., due to
902 * aggressive use of lfetch.fault.
904 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
907 * Initialize default control register to defer speculative faults except
908 * for those arising from TLB misses, which are not deferred. The
909 * kernel MUST NOT depend on a particular setting of these bits (in other words,
910 * the kernel must have recovery code for all speculative accesses). Turn on
911 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
912 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
915 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
916 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
917 atomic_inc(&init_mm.mm_count);
918 current->active_mm = &init_mm;
922 ia64_mmu_init(ia64_imva(cpu_data));
923 ia64_mca_cpu_init(ia64_imva(cpu_data));
925 #ifdef CONFIG_IA32_SUPPORT
929 /* Clear ITC to eliminate sched_clock() overflows in human time. */
932 /* disable all local interrupt sources: */
933 ia64_set_itv(1 << 16);
934 ia64_set_lrr0(1 << 16);
935 ia64_set_lrr1(1 << 16);
936 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
937 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
939 /* clear TPR & XTP to enable all interrupt classes: */
940 ia64_setreg(_IA64_REG_CR_TPR, 0);
942 /* Clear any pending interrupts left by SAL/EFI */
943 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
950 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
951 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
952 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
954 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
955 max_ctx = (1U << 15) - 1; /* use architected minimum */
957 while (max_ctx < ia64_ctx.max_ctx) {
958 unsigned int old = ia64_ctx.max_ctx;
959 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
963 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
964 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
966 num_phys_stacked = 96;
968 /* size of physical stacked register partition plus 8 bytes: */
969 if (num_phys_stacked > max_num_phys_stacked) {
970 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
971 max_num_phys_stacked = num_phys_stacked;
974 pm_idle = default_idle;
980 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
981 (unsigned long) __end___mckinley_e9_bundles);
984 static int __init run_dmi_scan(void)
989 core_initcall(run_dmi_scan);