4 * Prints processor specific information reported by PAL.
5 * This code is based on specification of PAL as of the
6 * Intel IA-64 Architecture Software Developer's Manual v1.0.
9 * Copyright (C) 2000-2001, 2003 Hewlett-Packard Co
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 2004 Intel Corporation
12 * Ashok Raj <ashok.raj@intel.com>
14 * 05/26/2000 S.Eranian initial release
15 * 08/21/2000 S.Eranian updated to July 2000 PAL specs
16 * 02/05/2001 S.Eranian fixed module support
17 * 10/23/2001 S.Eranian updated pal_perf_mon_info bug fixes
18 * 03/24/2004 Ashok Raj updated to work with CPU Hotplug
19 * 10/26/2006 Russ Anderson updated processor features to rev 2.2 spec
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/proc_fs.h>
26 #include <linux/module.h>
27 #include <linux/efi.h>
28 #include <linux/notifier.h>
29 #include <linux/cpu.h>
30 #include <linux/cpumask.h>
35 #include <asm/processor.h>
36 #include <linux/smp.h>
38 MODULE_AUTHOR("Stephane Eranian <eranian@hpl.hp.com>");
39 MODULE_DESCRIPTION("/proc interface to IA-64 PAL");
40 MODULE_LICENSE("GPL");
42 #define PALINFO_VERSION "0.5"
44 typedef int (*palinfo_func_t)(char*);
47 const char *name; /* name of the proc entry */
48 palinfo_func_t proc_read; /* function to call for reading */
49 struct proc_dir_entry *entry; /* registered entry (removal) */
54 * A bunch of string array to get pretty printing
57 static char *cache_types[] = {
61 "Data/Instruction" /* unified */
64 static const char *cache_mattrib[]={
71 static const char *cache_st_hints[]={
75 "Non-temporal, all levels",
82 static const char *cache_ld_hints[]={
84 "Non-temporal, level 1",
86 "Non-temporal, all levels",
93 static const char *rse_hints[]={
97 "eager loads and stores"
100 #define RSE_HINTS_COUNT ARRAY_SIZE(rse_hints)
102 static const char *mem_attrib[]={
114 * Take a 64bit vector and produces a string such that
115 * if bit n is set then 2^n in clear text is generated. The adjustment
116 * to the right unit is also done.
119 * - a pointer to a buffer to hold the string
122 * - a pointer to the end of the buffer
126 bitvector_process(char *p, u64 vector)
129 const char *units[]={ "", "K", "M", "G", "T" };
131 for (i=0, j=0; i < 64; i++ , j=i/10) {
133 p += sprintf(p, "%d%s ", 1 << (i-j*10), units[j]);
141 * Take a 64bit vector and produces a string such that
142 * if bit n is set then register n is present. The function
143 * takes into account consecutive registers and prints out ranges.
146 * - a pointer to a buffer to hold the string
149 * - a pointer to the end of the buffer
153 bitregister_process(char *p, u64 *reg_info, int max)
155 int i, begin, skip = 0;
156 u64 value = reg_info[0];
158 value >>= i = begin = ffs(value) - 1;
160 for(; i < max; i++ ) {
162 if (i != 0 && (i%64) == 0) value = *++reg_info;
164 if ((value & 0x1) == 0 && skip == 0) {
166 p += sprintf(p, "%d-%d ", begin, i-1);
168 p += sprintf(p, "%d ", i-1);
171 } else if ((value & 0x1) && skip == 1) {
179 p += sprintf(p, "%d-127", begin);
181 p += sprintf(p, "127");
188 power_info(char *page)
192 u64 halt_info_buffer[8];
193 pal_power_mgmt_info_u_t *halt_info =(pal_power_mgmt_info_u_t *)halt_info_buffer;
196 status = ia64_pal_halt_info(halt_info);
197 if (status != 0) return 0;
199 for (i=0; i < 8 ; i++ ) {
200 if (halt_info[i].pal_power_mgmt_info_s.im == 1) {
201 p += sprintf(p, "Power level %d:\n"
202 "\tentry_latency : %d cycles\n"
203 "\texit_latency : %d cycles\n"
204 "\tpower consumption : %d mW\n"
205 "\tCache+TLB coherency : %s\n", i,
206 halt_info[i].pal_power_mgmt_info_s.entry_latency,
207 halt_info[i].pal_power_mgmt_info_s.exit_latency,
208 halt_info[i].pal_power_mgmt_info_s.power_consumption,
209 halt_info[i].pal_power_mgmt_info_s.co ? "Yes" : "No");
211 p += sprintf(p,"Power level %d: not implemented\n",i);
218 cache_info(char *page)
221 u64 i, levels, unique_caches;
222 pal_cache_config_info_t cci;
226 if ((status = ia64_pal_cache_summary(&levels, &unique_caches)) != 0) {
227 printk(KERN_ERR "ia64_pal_cache_summary=%ld\n", status);
231 p += sprintf(p, "Cache levels : %ld\nUnique caches : %ld\n\n", levels, unique_caches);
233 for (i=0; i < levels; i++) {
235 for (j=2; j >0 ; j--) {
237 /* even without unification some level may not be present */
238 if ((status=ia64_pal_cache_config_info(i,j, &cci)) != 0) {
242 "%s Cache level %lu:\n"
243 "\tSize : %u bytes\n"
245 cache_types[j+cci.pcci_unified], i+1,
246 cci.pcci_cache_size);
248 if (cci.pcci_unified) p += sprintf(p, "Unified ");
250 p += sprintf(p, "%s\n", cache_mattrib[cci.pcci_cache_attr]);
253 "\tAssociativity : %d\n"
254 "\tLine size : %d bytes\n"
255 "\tStride : %d bytes\n",
256 cci.pcci_assoc, 1<<cci.pcci_line_size, 1<<cci.pcci_stride);
258 p += sprintf(p, "\tStore latency : N/A\n");
260 p += sprintf(p, "\tStore latency : %d cycle(s)\n",
261 cci.pcci_st_latency);
264 "\tLoad latency : %d cycle(s)\n"
265 "\tStore hints : ", cci.pcci_ld_latency);
267 for(k=0; k < 8; k++ ) {
268 if ( cci.pcci_st_hints & 0x1)
269 p += sprintf(p, "[%s]", cache_st_hints[k]);
270 cci.pcci_st_hints >>=1;
272 p += sprintf(p, "\n\tLoad hints : ");
274 for(k=0; k < 8; k++ ) {
275 if (cci.pcci_ld_hints & 0x1)
276 p += sprintf(p, "[%s]", cache_ld_hints[k]);
277 cci.pcci_ld_hints >>=1;
280 "\n\tAlias boundary : %d byte(s)\n"
283 1<<cci.pcci_alias_boundary, cci.pcci_tag_lsb,
286 /* when unified, data(j=2) is enough */
287 if (cci.pcci_unified) break;
298 u64 tr_pages =0, vw_pages=0, tc_pages;
300 pal_vm_info_1_u_t vm_info_1;
301 pal_vm_info_2_u_t vm_info_2;
302 pal_tc_info_u_t tc_info;
303 ia64_ptce_info_t ptce;
308 if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
309 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
313 "Physical Address Space : %d bits\n"
314 "Virtual Address Space : %d bits\n"
315 "Protection Key Registers(PKR) : %d\n"
316 "Implemented bits in PKR.key : %d\n"
317 "Hash Tag ID : 0x%x\n"
318 "Size of RR.rid : %d\n"
320 vm_info_1.pal_vm_info_1_s.phys_add_size,
321 vm_info_2.pal_vm_info_2_s.impl_va_msb+1,
322 vm_info_1.pal_vm_info_1_s.max_pkr+1,
323 vm_info_1.pal_vm_info_1_s.key_size,
324 vm_info_1.pal_vm_info_1_s.hash_tag_id,
325 vm_info_2.pal_vm_info_2_s.rid_size);
326 if (vm_info_2.pal_vm_info_2_s.max_purges == PAL_MAX_PURGES)
327 p += sprintf(p, "unlimited\n");
329 p += sprintf(p, "%d\n",
330 vm_info_2.pal_vm_info_2_s.max_purges ?
331 vm_info_2.pal_vm_info_2_s.max_purges : 1);
334 if (ia64_pal_mem_attrib(&attrib) == 0) {
335 p += sprintf(p, "Supported memory attributes : ");
337 for (i = 0; i < 8; i++) {
338 if (attrib & (1 << i)) {
339 p += sprintf(p, "%s%s", sep, mem_attrib[i]);
343 p += sprintf(p, "\n");
346 if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) {
347 printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status);
351 "\nTLB walker : %simplemented\n"
352 "Number of DTR : %d\n"
353 "Number of ITR : %d\n"
354 "TLB insertable page sizes : ",
355 vm_info_1.pal_vm_info_1_s.vw ? "" : "not ",
356 vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
357 vm_info_1.pal_vm_info_1_s.max_itr_entry+1);
360 p = bitvector_process(p, tr_pages);
362 p += sprintf(p, "\nTLB purgeable page sizes : ");
364 p = bitvector_process(p, vw_pages);
366 if ((status=ia64_get_ptce(&ptce)) != 0) {
367 printk(KERN_ERR "ia64_get_ptce=%ld\n", status);
370 "\nPurge base address : 0x%016lx\n"
371 "Purge outer loop count : %d\n"
372 "Purge inner loop count : %d\n"
373 "Purge outer loop stride : %d\n"
374 "Purge inner loop stride : %d\n",
375 ptce.base, ptce.count[0], ptce.count[1],
376 ptce.stride[0], ptce.stride[1]);
380 "Unique TC(s) : %d\n",
381 vm_info_1.pal_vm_info_1_s.num_tc_levels,
382 vm_info_1.pal_vm_info_1_s.max_unique_tcs);
384 for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) {
385 for (j=2; j>0 ; j--) {
386 tc_pages = 0; /* just in case */
389 /* even without unification, some levels may not be present */
390 if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) {
395 "\n%s Translation Cache Level %d:\n"
397 "\tAssociativity : %d\n"
398 "\tNumber of entries : %d\n"
400 cache_types[j+tc_info.tc_unified], i+1,
402 tc_info.tc_associativity,
403 tc_info.tc_num_entries);
406 p += sprintf(p, "PreferredPageSizeOptimized ");
407 if (tc_info.tc_unified)
408 p += sprintf(p, "Unified ");
409 if (tc_info.tc_reduce_tr)
410 p += sprintf(p, "TCReduction");
412 p += sprintf(p, "\n\tSupported page sizes: ");
414 p = bitvector_process(p, tc_pages);
416 /* when unified date (j=2) is enough */
417 if (tc_info.tc_unified)
422 p += sprintf(p, "\n");
429 register_info(char *page)
439 "AR(s) with read side-effects",
441 "CR(s) with read side-effects",
444 for(info=0; info < 4; info++) {
446 if (ia64_pal_register_info(info, ®_info[0], ®_info[1]) != 0) return 0;
448 p += sprintf(p, "%-32s : ", info_type[info]);
450 p = bitregister_process(p, reg_info, 128);
452 p += sprintf(p, "\n");
455 if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) {
458 "RSE stacked physical registers : %ld\n"
459 "RSE load/store hints : %ld (%s)\n",
460 phys_stacked, hints.ph_data,
461 hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)");
463 if (ia64_pal_debug_info(&iregs, &dregs))
467 "Instruction debug register pairs : %ld\n"
468 "Data debug register pairs : %ld\n", iregs, dregs);
473 static const char *proc_features[]={
474 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
475 NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
476 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
477 NULL,NULL,NULL,NULL,NULL, NULL,NULL,NULL,NULL,
478 "Unimplemented instruction address fault",
479 "INIT, PMI, and LINT pins",
480 "Simple unimplemented instr addresses",
481 "Variable P-state performance",
482 "Virtual machine features implemented",
483 "XIP,XPSR,XFS implemented",
484 "XR1-XR3 implemented",
485 "Disable dynamic predicate prediction",
486 "Disable processor physical number",
487 "Disable dynamic data cache prefetch",
488 "Disable dynamic inst cache prefetch",
489 "Disable dynamic branch prediction",
490 NULL, NULL, NULL, NULL,
492 "Enable MCA on Data Poisoning",
493 "Enable vmsw instruction",
494 "Enable extern environmental notification",
495 "Disable BINIT on processor time-out",
496 "Disable dynamic power management (DPM)",
499 "Enable CMCI promotion",
500 "Enable MCA to BINIT promotion",
501 "Enable MCA promotion",
502 "Enable BERR promotion"
507 processor_info(char *page)
510 const char **v = proc_features;
511 u64 avail=1, status=1, control=1;
515 if ((ret=ia64_pal_proc_get_features(&avail, &status, &control)) != 0) return 0;
517 for(i=0; i < 64; i++, v++,avail >>=1, status >>=1, control >>=1) {
518 if ( ! *v ) continue;
519 p += sprintf(p, "%-40s : %s%s %s\n", *v,
520 avail & 0x1 ? "" : "NotImpl",
521 avail & 0x1 ? (status & 0x1 ? "On" : "Off"): "",
522 avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
527 static const char *bus_features[]={
528 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
529 NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
530 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
532 "Request Bus Parking",
534 "Enable Half Transfer",
535 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
536 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
537 NULL, NULL, NULL, NULL,
538 "Enable Cache Line Repl. Shared",
539 "Enable Cache Line Repl. Exclusive",
540 "Disable Transaction Queuing",
541 "Disable Response Error Checking",
542 "Disable Bus Error Checking",
543 "Disable Bus Requester Internal Error Signalling",
544 "Disable Bus Requester Error Signalling",
545 "Disable Bus Initialization Event Checking",
546 "Disable Bus Initialization Event Signalling",
547 "Disable Bus Address Error Checking",
548 "Disable Bus Address Error Signalling",
549 "Disable Bus Data Error Checking"
557 const char **v = bus_features;
558 pal_bus_features_u_t av, st, ct;
559 u64 avail, status, control;
563 if ((ret=ia64_pal_bus_get_features(&av, &st, &ct)) != 0) return 0;
565 avail = av.pal_bus_features_val;
566 status = st.pal_bus_features_val;
567 control = ct.pal_bus_features_val;
569 for(i=0; i < 64; i++, v++, avail >>=1, status >>=1, control >>=1) {
570 if ( ! *v ) continue;
571 p += sprintf(p, "%-48s : %s%s %s\n", *v,
572 avail & 0x1 ? "" : "NotImpl",
573 avail & 0x1 ? (status & 0x1 ? "On" : "Off"): "",
574 avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
580 version_info(char *page)
582 pal_version_u_t min_ver, cur_ver;
585 if (ia64_pal_version(&min_ver, &cur_ver) != 0)
589 "PAL_vendor : 0x%02x (min=0x%02x)\n"
590 "PAL_A : %02x.%02x (min=%02x.%02x)\n"
591 "PAL_B : %02x.%02x (min=%02x.%02x)\n",
592 cur_ver.pal_version_s.pv_pal_vendor,
593 min_ver.pal_version_s.pv_pal_vendor,
594 cur_ver.pal_version_s.pv_pal_a_model,
595 cur_ver.pal_version_s.pv_pal_a_rev,
596 min_ver.pal_version_s.pv_pal_a_model,
597 min_ver.pal_version_s.pv_pal_a_rev,
598 cur_ver.pal_version_s.pv_pal_b_model,
599 cur_ver.pal_version_s.pv_pal_b_rev,
600 min_ver.pal_version_s.pv_pal_b_model,
601 min_ver.pal_version_s.pv_pal_b_rev);
606 perfmon_info(char *page)
610 pal_perf_mon_info_u_t pm_info;
612 if (ia64_pal_perf_mon_info(pm_buffer, &pm_info) != 0) return 0;
615 "PMC/PMD pairs : %d\n"
616 "Counter width : %d bits\n"
617 "Cycle event number : %d\n"
618 "Retired event number : %d\n"
619 "Implemented PMC : ",
620 pm_info.pal_perf_mon_info_s.generic, pm_info.pal_perf_mon_info_s.width,
621 pm_info.pal_perf_mon_info_s.cycles, pm_info.pal_perf_mon_info_s.retired);
623 p = bitregister_process(p, pm_buffer, 256);
624 p += sprintf(p, "\nImplemented PMD : ");
625 p = bitregister_process(p, pm_buffer+4, 256);
626 p += sprintf(p, "\nCycles count capable : ");
627 p = bitregister_process(p, pm_buffer+8, 256);
628 p += sprintf(p, "\nRetired bundles count capable : ");
630 #ifdef CONFIG_ITANIUM
632 * PAL_PERF_MON_INFO reports that only PMC4 can be used to count CPU_CYCLES
633 * which is wrong, both PMC4 and PMD5 support it.
635 if (pm_buffer[12] == 0x10) pm_buffer[12]=0x30;
638 p = bitregister_process(p, pm_buffer+12, 256);
640 p += sprintf(p, "\n");
646 frequency_info(char *page)
649 struct pal_freq_ratio proc, itc, bus;
652 if (ia64_pal_freq_base(&base) == -1)
653 p += sprintf(p, "Output clock : not implemented\n");
655 p += sprintf(p, "Output clock : %ld ticks/s\n", base);
657 if (ia64_pal_freq_ratios(&proc, &bus, &itc) != 0) return 0;
660 "Processor/Clock ratio : %d/%d\n"
661 "Bus/Clock ratio : %d/%d\n"
662 "ITC/Clock ratio : %d/%d\n",
663 proc.num, proc.den, bus.num, bus.den, itc.num, itc.den);
673 pal_tr_valid_u_t tr_valid;
675 pal_vm_info_1_u_t vm_info_1;
676 pal_vm_info_2_u_t vm_info_2;
711 if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
712 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
715 max[0] = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
716 max[1] = vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
718 for (i=0; i < 2; i++ ) {
719 for (j=0; j < max[i]; j++) {
721 status = ia64_pal_tr_read(j, i, tr_buffer, &tr_valid);
723 printk(KERN_ERR "palinfo: pal call failed on tr[%lu:%lu]=%ld\n",
728 ifa_reg = (struct ifa_reg *)&tr_buffer[2];
730 if (ifa_reg->valid == 0) continue;
732 gr_reg = (struct gr_reg *)tr_buffer;
733 itir_reg = (struct itir_reg *)&tr_buffer[1];
734 rid_reg = (struct rid_reg *)&tr_buffer[3];
736 pgm = -1 << (itir_reg->ps - 12);
738 "%cTR%lu: av=%d pv=%d dv=%d mv=%d\n"
743 tr_valid.pal_tr_valid_s.access_rights_valid,
744 tr_valid.pal_tr_valid_s.priv_level_valid,
745 tr_valid.pal_tr_valid_s.dirty_bit_valid,
746 tr_valid.pal_tr_valid_s.mem_attr_valid,
747 (gr_reg->ppn & pgm)<< 12, (ifa_reg->vpn & pgm)<< 12);
749 p = bitvector_process(p, 1<< itir_reg->ps);
758 gr_reg->pl, gr_reg->ar, rid_reg->rid, gr_reg->p, gr_reg->ma,
768 * List {name,function} pairs for every entry in /proc/palinfo/cpu*
770 static palinfo_entry_t palinfo_entries[]={
771 { "version_info", version_info, },
772 { "vm_info", vm_info, },
773 { "cache_info", cache_info, },
774 { "power_info", power_info, },
775 { "register_info", register_info, },
776 { "processor_info", processor_info, },
777 { "perfmon_info", perfmon_info, },
778 { "frequency_info", frequency_info, },
779 { "bus_info", bus_info },
780 { "tr_info", tr_info, }
783 #define NR_PALINFO_ENTRIES (int) ARRAY_SIZE(palinfo_entries)
786 * this array is used to keep track of the proc entries we create. This is
787 * required in the module mode when we need to remove all entries. The procfs code
788 * does not do recursion of deletion
791 * - +1 accounts for the cpuN directory entry in /proc/pal
793 #define NR_PALINFO_PROC_ENTRIES (NR_CPUS*(NR_PALINFO_ENTRIES+1))
795 static struct proc_dir_entry *palinfo_proc_entries[NR_PALINFO_PROC_ENTRIES];
796 static struct proc_dir_entry *palinfo_dir;
799 * This data structure is used to pass which cpu,function is being requested
800 * It must fit in a 64bit quantity to be passed to the proc callback routine
802 * In SMP mode, when we get a request for another CPU, we must call that
803 * other CPU using IPI and wait for the result before returning.
808 unsigned req_cpu: 32; /* for which CPU this info is */
809 unsigned func_id: 32; /* which function is requested */
813 #define req_cpu pal_func_cpu.req_cpu
814 #define func_id pal_func_cpu.func_id
819 * used to hold information about final function to call
822 palinfo_func_t func; /* pointer to function to call */
823 char *page; /* buffer to store results */
824 int ret; /* return value from call */
825 } palinfo_smp_data_t;
829 * this function does the actual final call and he called
830 * from the smp code, i.e., this is the palinfo callback routine
833 palinfo_smp_call(void *info)
835 palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
837 printk(KERN_ERR "palinfo: data pointer is NULL\n");
838 data->ret = 0; /* no output */
841 /* does this actual call */
842 data->ret = (*data->func)(data->page);
846 * function called to trigger the IPI, we need to access a remote CPU
848 * 0 : error or nothing to output
849 * otherwise how many bytes in the "page" buffer were written
852 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
854 palinfo_smp_data_t ptr;
857 ptr.func = palinfo_entries[f->func_id].proc_read;
859 ptr.ret = 0; /* just in case */
862 /* will send IPI to other CPU and wait for completion of remote call */
863 if ((ret=smp_call_function_single(f->req_cpu, palinfo_smp_call, &ptr, 0, 1))) {
864 printk(KERN_ERR "palinfo: remote CPU call from %d to %d on function %d: "
865 "error %d\n", smp_processor_id(), f->req_cpu, f->func_id, ret);
870 #else /* ! CONFIG_SMP */
872 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
874 printk(KERN_ERR "palinfo: should not be called with non SMP kernel\n");
877 #endif /* CONFIG_SMP */
880 * Entry point routine: all calls go through this function
883 palinfo_read_entry(char *page, char **start, off_t off, int count, int *eof, void *data)
886 pal_func_cpu_u_t *f = (pal_func_cpu_u_t *)&data;
889 * in SMP mode, we may need to call another CPU to get correct
890 * information. PAL, by definition, is processor specific
892 if (f->req_cpu == get_cpu())
893 len = (*palinfo_entries[f->func_id].proc_read)(page);
895 len = palinfo_handle_smp(f, page);
899 if (len <= off+count) *eof = 1;
904 if (len>count) len = count;
911 create_palinfo_proc_entries(unsigned int cpu)
913 # define CPUSTR "cpu%d"
916 struct proc_dir_entry **pdir;
917 struct proc_dir_entry *cpu_dir;
919 char cpustr[sizeof(CPUSTR)];
923 * we keep track of created entries in a depth-first order for
924 * cleanup purposes. Each entry is stored into palinfo_proc_entries
926 sprintf(cpustr,CPUSTR, cpu);
928 cpu_dir = proc_mkdir(cpustr, palinfo_dir);
933 * Compute the location to store per cpu entries
934 * We dont store the top level entry in this list, but
935 * remove it finally after removing all cpu entries.
937 pdir = &palinfo_proc_entries[cpu*(NR_PALINFO_ENTRIES+1)];
939 for (j=0; j < NR_PALINFO_ENTRIES; j++) {
941 *pdir = create_proc_read_entry(
942 palinfo_entries[j].name, 0, cpu_dir,
943 palinfo_read_entry, (void *)f.value);
945 (*pdir)->owner = THIS_MODULE;
951 remove_palinfo_proc_entries(unsigned int hcpu)
954 struct proc_dir_entry *cpu_dir, **pdir;
956 pdir = &palinfo_proc_entries[hcpu*(NR_PALINFO_ENTRIES+1)];
959 for (j=0; j < (NR_PALINFO_ENTRIES); j++) {
961 remove_proc_entry ((*pdir)->name, cpu_dir);
967 remove_proc_entry(cpu_dir->name, palinfo_dir);
971 static int palinfo_cpu_callback(struct notifier_block *nfb,
972 unsigned long action, void *hcpu)
974 unsigned int hotcpu = (unsigned long)hcpu;
978 case CPU_ONLINE_FROZEN:
979 create_palinfo_proc_entries(hotcpu);
982 case CPU_DEAD_FROZEN:
983 remove_palinfo_proc_entries(hotcpu);
989 static struct notifier_block palinfo_cpu_notifier =
991 .notifier_call = palinfo_cpu_callback,
1000 printk(KERN_INFO "PAL Information Facility v%s\n", PALINFO_VERSION);
1001 palinfo_dir = proc_mkdir("pal", NULL);
1003 /* Create palinfo dirs in /proc for all online cpus */
1004 for_each_online_cpu(i) {
1005 create_palinfo_proc_entries(i);
1008 /* Register for future delivery via notify registration */
1009 register_hotcpu_notifier(&palinfo_cpu_notifier);
1019 /* remove all nodes: depth first pass. Could optimize this */
1020 for_each_online_cpu(i) {
1021 remove_palinfo_proc_entries(i);
1025 * Remove the top level entry finally
1027 remove_proc_entry(palinfo_dir->name, NULL);
1030 * Unregister from cpu notifier callbacks
1032 unregister_hotcpu_notifier(&palinfo_cpu_notifier);
1035 module_init(palinfo_init);
1036 module_exit(palinfo_exit);