3 * IA-64 Processor Programmers Reference Vol 2
5 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
6 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
7 * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
8 * David Mosberger <davidm@hpl.hp.com>
9 * Stephane Eranian <eranian@hpl.hp.com>
11 * 05/22/2000 eranian Added support for stacked register calls
12 * 05/24/2000 eranian Added support for physical mode static calls
15 #include <asm/asmmacro.h>
16 #include <asm/processor.h>
20 data8 ia64_pal_default_handler
24 * Set the PAL entry point address. This could be written in C code, but we do it here
25 * to keep it all in one module (besides, it's so trivial that it's
28 * in0 Address of the PAL entry point (text address, NOT a function descriptor).
30 GLOBAL_ENTRY(ia64_pal_handler_init)
31 alloc r3=ar.pfs,1,0,0,0
32 movl r2=pal_entry_point
36 END(ia64_pal_handler_init)
39 * Default PAL call handler. This needs to be coded in assembly because it uses
40 * the static calling convention, i.e., the RSE may not be used and calls are
41 * done via "br.cond" (not "br.call").
43 GLOBAL_ENTRY(ia64_pal_default_handler)
46 END(ia64_pal_default_handler)
49 * Make a PAL call using the static calling convention.
51 * in0 Index of PAL service
52 * in1 - in3 Remaining PAL arguments
54 GLOBAL_ENTRY(ia64_pal_call_static)
55 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
56 alloc loc1 = ar.pfs,4,5,0,0
57 movl loc2 = pal_entry_point
64 ld8 loc2 = [loc2] // loc2 <- entry point
66 mov loc4=ar.rsc // save RSE configuration
68 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
82 mov ar.rsc = loc4 // restore RSE configuration
86 srlz.d // seralize restoration of psr.l
88 END(ia64_pal_call_static)
91 * Make a PAL call using the stacked registers calling convention.
94 * in0 Index of PAL service
95 * in2 - in3 Remaning PAL arguments
97 GLOBAL_ENTRY(ia64_pal_call_stacked)
98 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
99 alloc loc1 = ar.pfs,4,4,4,0
100 movl loc2 = pal_entry_point
102 mov r28 = in0 // Index MUST be copied to r28
103 mov out0 = in0 // AND in0 of PAL function
107 ld8 loc2 = [loc2] // loc2 <- entry point
116 br.call.sptk.many rp=b7 // now make the call
117 .ret0: mov psr.l = loc3
121 srlz.d // serialize restoration of psr.l
123 END(ia64_pal_call_stacked)
126 * Make a physical mode PAL call using the static registers calling convention.
129 * in0 Index of PAL service
130 * in2 - in3 Remaning PAL arguments
132 * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
133 * So we don't need to clear them.
135 #define PAL_PSR_BITS_TO_CLEAR \
136 (IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_DB | IA64_PSR_RT | \
137 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | \
138 IA64_PSR_DFL | IA64_PSR_DFH)
140 #define PAL_PSR_BITS_TO_SET \
144 GLOBAL_ENTRY(ia64_pal_call_phys_static)
145 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
146 alloc loc1 = ar.pfs,4,7,0,0
147 movl loc2 = pal_entry_point
149 mov r28 = in0 // copy procedure index
150 mov r8 = ip // save ip to compute branch
151 mov loc0 = rp // save rp
155 ld8 loc2 = [loc2] // loc2 <- entry point
156 mov r29 = in1 // first argument
157 mov r30 = in2 // copy arg2
158 mov r31 = in3 // copy arg3
160 mov loc3 = psr // save psr
161 adds r8 = 1f-1b,r8 // calculate return address for call
163 mov loc4=ar.rsc // save RSE configuration
164 dep.z loc2=loc2,0,61 // convert pal entry point to physical
165 tpa r8=r8 // convert rp to physical
167 mov b7 = loc2 // install target to branch reg
168 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
169 movl r16=PAL_PSR_BITS_TO_CLEAR
170 movl r17=PAL_PSR_BITS_TO_SET
172 or loc3=loc3,r17 // add in psr the bits to set
174 andcm r16=loc3,r16 // removes bits to clear from psr
175 br.call.sptk.many rp=ia64_switch_mode_phys
176 .ret1: mov rp = r8 // install return address (physical)
181 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
182 mov r16=loc3 // r16= original psr
185 br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
187 mov psr.l = loc3 // restore init PSR
192 mov ar.rsc=loc4 // restore RSE configuration
193 srlz.d // seralize restoration of psr.l
195 END(ia64_pal_call_phys_static)
198 * Make a PAL call using the stacked registers in physical mode.
201 * in0 Index of PAL service
202 * in2 - in3 Remaning PAL arguments
204 GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
205 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
206 alloc loc1 = ar.pfs,5,7,4,0
207 movl loc2 = pal_entry_point
209 mov r28 = in0 // copy procedure index
210 mov loc0 = rp // save rp
214 ld8 loc2 = [loc2] // loc2 <- entry point
215 mov loc3 = psr // save psr
217 mov loc4=ar.rsc // save RSE configuration
218 dep.z loc2=loc2,0,61 // convert pal entry point to physical
220 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
221 movl r16=PAL_PSR_BITS_TO_CLEAR
222 movl r17=PAL_PSR_BITS_TO_SET
224 or loc3=loc3,r17 // add in psr the bits to set
225 mov b7 = loc2 // install target to branch reg
227 andcm r16=loc3,r16 // removes bits to clear from psr
228 br.call.sptk.many rp=ia64_switch_mode_phys
230 mov out0 = in0 // first argument
231 mov out1 = in1 // copy arg2
232 mov out2 = in2 // copy arg3
233 mov out3 = in3 // copy arg3
237 br.call.sptk.many rp=b7 // now make the call
239 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
240 mov r16=loc3 // r16= original psr
243 br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
245 mov psr.l = loc3 // restore init PSR
249 mov ar.rsc=loc4 // restore RSE configuration
250 srlz.d // seralize restoration of psr.l
252 END(ia64_pal_call_phys_stacked)
255 * Save scratch fp scratch regs which aren't saved in pt_regs already (fp10-fp15).
257 * NOTE: We need to do this since firmware (SAL and PAL) may use any of the scratch
258 * regs fp-low partition.
261 * in0 Address of stack storage for fp regs
263 GLOBAL_ENTRY(ia64_save_scratch_fpregs)
264 alloc r3=ar.pfs,1,0,0,0
267 stf.spill [in0] = f10,32
268 stf.spill [r2] = f11,32
270 stf.spill [in0] = f12,32
271 stf.spill [r2] = f13,32
273 stf.spill [in0] = f14,32
274 stf.spill [r2] = f15,32
276 END(ia64_save_scratch_fpregs)
279 * Load scratch fp scratch regs (fp10-fp15)
282 * in0 Address of stack storage for fp regs
284 GLOBAL_ENTRY(ia64_load_scratch_fpregs)
285 alloc r3=ar.pfs,1,0,0,0
288 ldf.fill f10 = [in0],32
289 ldf.fill f11 = [r2],32
291 ldf.fill f12 = [in0],32
292 ldf.fill f13 = [r2],32
294 ldf.fill f14 = [in0],32
295 ldf.fill f15 = [r2],32
297 END(ia64_load_scratch_fpregs)