2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
37 /* SMP boot always wants to use real time delay to allow sufficient time for
38 * the APs to come online */
39 #define USE_REAL_TIME_DELAY
41 #include <linux/module.h>
42 #include <linux/init.h>
43 #include <linux/kernel.h>
46 #include <linux/sched.h>
47 #include <linux/kernel_stat.h>
48 #include <linux/smp_lock.h>
49 #include <linux/bootmem.h>
50 #include <linux/notifier.h>
51 #include <linux/cpu.h>
52 #include <linux/percpu.h>
54 #include <linux/delay.h>
55 #include <linux/mc146818rtc.h>
56 #include <asm/tlbflush.h>
58 #include <asm/arch_hooks.h>
61 #include <asm/genapic.h>
63 #include <mach_apic.h>
64 #include <mach_wakecpu.h>
65 #include <smpboot_hooks.h>
67 /* Set if we find a B stepping CPU */
68 static int __devinitdata smp_b_stepping;
70 /* Number of siblings per CPU package */
71 int smp_num_siblings = 1;
72 EXPORT_SYMBOL(smp_num_siblings);
74 /* Last level cache ID of each logical CPU */
75 int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID};
77 /* representing HT siblings of each logical CPU */
78 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
79 EXPORT_SYMBOL(cpu_sibling_map);
81 /* representing HT and core siblings of each logical CPU */
82 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
83 EXPORT_SYMBOL(cpu_core_map);
85 /* bitmap of online cpus */
86 cpumask_t cpu_online_map __read_mostly;
87 EXPORT_SYMBOL(cpu_online_map);
89 cpumask_t cpu_callin_map;
90 cpumask_t cpu_callout_map;
91 EXPORT_SYMBOL(cpu_callout_map);
92 cpumask_t cpu_possible_map;
93 EXPORT_SYMBOL(cpu_possible_map);
94 static cpumask_t smp_commenced_mask;
96 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
97 * is no way to resync one AP against BP. TBD: for prescott and above, we
98 * should use IA64's algorithm
100 static int __devinitdata tsc_sync_disabled;
102 /* Per CPU bogomips and other parameters */
103 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
104 EXPORT_SYMBOL(cpu_data);
106 u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
107 { [0 ... NR_CPUS-1] = 0xff };
108 EXPORT_SYMBOL(x86_cpu_to_apicid);
110 u8 apicid_2_node[MAX_APICID];
113 * Trampoline 80x86 program as an array.
116 extern unsigned char trampoline_data [];
117 extern unsigned char trampoline_end [];
118 static unsigned char *trampoline_base;
119 static int trampoline_exec;
121 static void map_cpu_to_logical_apicid(void);
123 /* State of each CPU. */
124 DEFINE_PER_CPU(int, cpu_state) = { 0 };
127 * Currently trivial. Write the real->protected mode
128 * bootstrap into the page concerned. The caller
129 * has made sure it's suitably aligned.
132 static unsigned long __devinit setup_trampoline(void)
134 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
135 return virt_to_phys(trampoline_base);
139 * We are called very early to get the low memory for the
140 * SMP bootup trampoline page.
142 void __init smp_alloc_memory(void)
144 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
146 * Has to be in very low memory so we can execute
149 if (__pa(trampoline_base) >= 0x9F000)
152 * Make the SMP trampoline executable:
154 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
158 * The bootstrap kernel entry code has set these up. Save them for
162 static void __cpuinit smp_store_cpu_info(int id)
164 struct cpuinfo_x86 *c = cpu_data + id;
170 * Mask B, Pentium, but not Pentium MMX
172 if (c->x86_vendor == X86_VENDOR_INTEL &&
174 c->x86_mask >= 1 && c->x86_mask <= 4 &&
177 * Remember we have B step Pentia with bugs
182 * Certain Athlons might work (for various values of 'work') in SMP
183 * but they are not certified as MP capable.
185 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
187 if (num_possible_cpus() == 1)
190 /* Athlon 660/661 is valid. */
191 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
194 /* Duron 670 is valid */
195 if ((c->x86_model==7) && (c->x86_mask==0))
199 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
200 * It's worth noting that the A5 stepping (662) of some Athlon XP's
201 * have the MP bit set.
202 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
204 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
205 ((c->x86_model==7) && (c->x86_mask>=1)) ||
210 /* If we get here, it's not a certified SMP capable AMD system. */
211 add_taint(TAINT_UNSAFE_SMP);
219 * TSC synchronization.
221 * We first check whether all CPUs have their TSC's synchronized,
222 * then we print a warning if not, and always resync.
227 atomic_t count_start;
229 unsigned long long values[NR_CPUS];
230 } tsc __cpuinitdata = {
231 .start_flag = ATOMIC_INIT(0),
232 .count_start = ATOMIC_INIT(0),
233 .count_stop = ATOMIC_INIT(0),
238 static void __init synchronize_tsc_bp(void)
241 unsigned long long t0;
242 unsigned long long sum, avg;
244 unsigned int one_usec;
247 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
249 /* convert from kcyc/sec to cyc/usec */
250 one_usec = cpu_khz / 1000;
252 atomic_set(&tsc.start_flag, 1);
256 * We loop a few times to get a primed instruction cache,
257 * then the last pass is more or less synchronized and
258 * the BP and APs set their cycle counters to zero all at
259 * once. This reduces the chance of having random offsets
260 * between the processors, and guarantees that the maximum
261 * delay between the cycle counters is never bigger than
262 * the latency of information-passing (cachelines) between
265 for (i = 0; i < NR_LOOPS; i++) {
267 * all APs synchronize but they loop on '== num_cpus'
269 while (atomic_read(&tsc.count_start) != num_booting_cpus()-1)
271 atomic_set(&tsc.count_stop, 0);
274 * this lets the APs save their current TSC:
276 atomic_inc(&tsc.count_start);
278 rdtscll(tsc.values[smp_processor_id()]);
280 * We clear the TSC in the last loop:
286 * Wait for all APs to leave the synchronization point:
288 while (atomic_read(&tsc.count_stop) != num_booting_cpus()-1)
290 atomic_set(&tsc.count_start, 0);
292 atomic_inc(&tsc.count_stop);
296 for (i = 0; i < NR_CPUS; i++) {
297 if (cpu_isset(i, cpu_callout_map)) {
303 do_div(avg, num_booting_cpus());
305 for (i = 0; i < NR_CPUS; i++) {
306 if (!cpu_isset(i, cpu_callout_map))
308 delta = tsc.values[i] - avg;
312 * We report bigger than 2 microseconds clock differences.
314 if (delta > 2*one_usec) {
322 do_div(realdelta, one_usec);
323 if (tsc.values[i] < avg)
324 realdelta = -realdelta;
327 printk(KERN_INFO "CPU#%d had %Ld usecs TSC "
328 "skew, fixed it up.\n", i, realdelta);
335 static void __cpuinit synchronize_tsc_ap(void)
340 * Not every cpu is online at the time
341 * this gets called, so we first wait for the BP to
342 * finish SMP initialization:
344 while (!atomic_read(&tsc.start_flag))
347 for (i = 0; i < NR_LOOPS; i++) {
348 atomic_inc(&tsc.count_start);
349 while (atomic_read(&tsc.count_start) != num_booting_cpus())
352 rdtscll(tsc.values[smp_processor_id()]);
356 atomic_inc(&tsc.count_stop);
357 while (atomic_read(&tsc.count_stop) != num_booting_cpus())
363 extern void calibrate_delay(void);
365 static atomic_t init_deasserted;
367 static void __cpuinit smp_callin(void)
370 unsigned long timeout;
373 * If waken up by an INIT in an 82489DX configuration
374 * we may get here before an INIT-deassert IPI reaches
375 * our local APIC. We have to wait for the IPI or we'll
376 * lock up on an APIC access.
378 wait_for_init_deassert(&init_deasserted);
381 * (This works even if the APIC is not enabled.)
383 phys_id = GET_APIC_ID(apic_read(APIC_ID));
384 cpuid = smp_processor_id();
385 if (cpu_isset(cpuid, cpu_callin_map)) {
386 printk("huh, phys CPU#%d, CPU#%d already present??\n",
390 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
393 * STARTUP IPIs are fragile beasts as they might sometimes
394 * trigger some glue motherboard logic. Complete APIC bus
395 * silence for 1 second, this overestimates the time the
396 * boot CPU is spending to send the up to 2 STARTUP IPIs
397 * by a factor of two. This should be enough.
401 * Waiting 2s total for startup (udelay is not yet working)
403 timeout = jiffies + 2*HZ;
404 while (time_before(jiffies, timeout)) {
406 * Has the boot CPU finished it's STARTUP sequence?
408 if (cpu_isset(cpuid, cpu_callout_map))
413 if (!time_before(jiffies, timeout)) {
414 printk("BUG: CPU%d started up but did not get a callout!\n",
420 * the boot CPU has finished the init stage and is spinning
421 * on callin_map until we finish. We are free to set up this
422 * CPU, first the APIC. (this is probably redundant on most
426 Dprintk("CALLIN, before setup_local_APIC().\n");
427 smp_callin_clear_local_apic();
429 map_cpu_to_logical_apicid();
435 Dprintk("Stack at about %p\n",&cpuid);
438 * Save our processor parameters
440 smp_store_cpu_info(cpuid);
442 disable_APIC_timer();
445 * Allow the master to continue.
447 cpu_set(cpuid, cpu_callin_map);
450 * Synchronize the TSC with the BP
452 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
453 synchronize_tsc_ap();
458 /* maps the cpu to the sched domain representing multi-core */
459 cpumask_t cpu_coregroup_map(int cpu)
461 struct cpuinfo_x86 *c = cpu_data + cpu;
463 * For perf, we return last level cache shared map.
464 * And for power savings, we return cpu_core_map
466 if (sched_mc_power_savings || sched_smt_power_savings)
467 return cpu_core_map[cpu];
469 return c->llc_shared_map;
472 /* representing cpus for which sibling maps can be computed */
473 static cpumask_t cpu_sibling_setup_map;
476 set_cpu_sibling_map(int cpu)
479 struct cpuinfo_x86 *c = cpu_data;
481 cpu_set(cpu, cpu_sibling_setup_map);
483 if (smp_num_siblings > 1) {
484 for_each_cpu_mask(i, cpu_sibling_setup_map) {
485 if (c[cpu].phys_proc_id == c[i].phys_proc_id &&
486 c[cpu].cpu_core_id == c[i].cpu_core_id) {
487 cpu_set(i, cpu_sibling_map[cpu]);
488 cpu_set(cpu, cpu_sibling_map[i]);
489 cpu_set(i, cpu_core_map[cpu]);
490 cpu_set(cpu, cpu_core_map[i]);
491 cpu_set(i, c[cpu].llc_shared_map);
492 cpu_set(cpu, c[i].llc_shared_map);
496 cpu_set(cpu, cpu_sibling_map[cpu]);
499 cpu_set(cpu, c[cpu].llc_shared_map);
501 if (current_cpu_data.x86_max_cores == 1) {
502 cpu_core_map[cpu] = cpu_sibling_map[cpu];
503 c[cpu].booted_cores = 1;
507 for_each_cpu_mask(i, cpu_sibling_setup_map) {
508 if (cpu_llc_id[cpu] != BAD_APICID &&
509 cpu_llc_id[cpu] == cpu_llc_id[i]) {
510 cpu_set(i, c[cpu].llc_shared_map);
511 cpu_set(cpu, c[i].llc_shared_map);
513 if (c[cpu].phys_proc_id == c[i].phys_proc_id) {
514 cpu_set(i, cpu_core_map[cpu]);
515 cpu_set(cpu, cpu_core_map[i]);
517 * Does this new cpu bringup a new core?
519 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
521 * for each core in package, increment
522 * the booted_cores for this new cpu
524 if (first_cpu(cpu_sibling_map[i]) == i)
525 c[cpu].booted_cores++;
527 * increment the core count for all
528 * the other cpus in this package
532 } else if (i != cpu && !c[cpu].booted_cores)
533 c[cpu].booted_cores = c[i].booted_cores;
539 * Activate a secondary processor.
541 static void __cpuinit start_secondary(void *unused)
544 * Don't put *anything* before secondary_cpu_init(), SMP
545 * booting is too fragile that we want to limit the
546 * things done here to the most necessary things.
548 secondary_cpu_init();
551 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
553 setup_secondary_APIC_clock();
554 if (nmi_watchdog == NMI_IO_APIC) {
555 disable_8259A_irq(0);
556 enable_NMI_through_LVT0(NULL);
561 * low-memory mappings have been cleared, flush them from
562 * the local TLBs too.
566 /* This must be done before setting cpu_online_map */
567 set_cpu_sibling_map(raw_smp_processor_id());
571 * We need to hold call_lock, so there is no inconsistency
572 * between the time smp_call_function() determines number of
573 * IPI receipients, and the time when the determination is made
574 * for which cpus receive the IPI. Holding this
575 * lock helps us to not include this cpu in a currently in progress
576 * smp_call_function().
578 lock_ipi_call_lock();
579 cpu_set(smp_processor_id(), cpu_online_map);
580 unlock_ipi_call_lock();
581 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
583 /* We can take interrupts now: we're officially "up". */
591 * Everything has been set up for the secondary
592 * CPUs - they just need to reload everything
593 * from the task structure
594 * This function must not return.
596 void __devinit initialize_secondary(void)
599 * switch to the per CPU GDT we already set up
602 cpu_set_gdt(current_thread_info()->cpu);
605 * We don't actually need to load the full TSS,
606 * basically just the stack pointer and the eip.
613 :"m" (current->thread.esp),"m" (current->thread.eip));
616 /* Static state in head.S used to set up a CPU */
621 extern struct i386_pda *start_pda;
622 extern struct Xgt_desc_struct cpu_gdt_descr;
626 /* which logical CPUs are on which nodes */
627 cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
628 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
629 EXPORT_SYMBOL(node_2_cpu_mask);
630 /* which node each logical CPU is on */
631 int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
632 EXPORT_SYMBOL(cpu_2_node);
634 /* set up a mapping between cpu and node. */
635 static inline void map_cpu_to_node(int cpu, int node)
637 printk("Mapping cpu %d to node %d\n", cpu, node);
638 cpu_set(cpu, node_2_cpu_mask[node]);
639 cpu_2_node[cpu] = node;
642 /* undo a mapping between cpu and node. */
643 static inline void unmap_cpu_to_node(int cpu)
647 printk("Unmapping cpu %d from all nodes\n", cpu);
648 for (node = 0; node < MAX_NUMNODES; node ++)
649 cpu_clear(cpu, node_2_cpu_mask[node]);
652 #else /* !CONFIG_NUMA */
654 #define map_cpu_to_node(cpu, node) ({})
655 #define unmap_cpu_to_node(cpu) ({})
657 #endif /* CONFIG_NUMA */
659 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
661 static void map_cpu_to_logical_apicid(void)
663 int cpu = smp_processor_id();
664 int apicid = logical_smp_processor_id();
665 int node = apicid_to_node(apicid);
667 if (!node_online(node))
668 node = first_online_node;
670 cpu_2_logical_apicid[cpu] = apicid;
671 map_cpu_to_node(cpu, node);
674 static void unmap_cpu_to_logical_apicid(int cpu)
676 cpu_2_logical_apicid[cpu] = BAD_APICID;
677 unmap_cpu_to_node(cpu);
681 static inline void __inquire_remote_apic(int apicid)
683 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
684 char *names[] = { "ID", "VERSION", "SPIV" };
687 printk("Inquiring remote APIC #%d...\n", apicid);
689 for (i = 0; i < ARRAY_SIZE(regs); i++) {
690 printk("... APIC #%d %s: ", apicid, names[i]);
695 apic_wait_icr_idle();
697 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
698 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
703 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
704 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
707 case APIC_ICR_RR_VALID:
708 status = apic_read(APIC_RRR);
709 printk("%08x\n", status);
718 #ifdef WAKE_SECONDARY_VIA_NMI
720 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
721 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
722 * won't ... remember to clear down the APIC, etc later.
725 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
727 unsigned long send_status = 0, accept_status = 0;
731 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
733 /* Boot on the stack */
734 /* Kick the second */
735 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
737 Dprintk("Waiting for send to finish...\n");
742 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
743 } while (send_status && (timeout++ < 1000));
746 * Give the other CPU some time to accept the IPI.
750 * Due to the Pentium erratum 3AP.
752 maxlvt = get_maxlvt();
754 apic_read_around(APIC_SPIV);
755 apic_write(APIC_ESR, 0);
757 accept_status = (apic_read(APIC_ESR) & 0xEF);
758 Dprintk("NMI sent.\n");
761 printk("APIC never delivered???\n");
763 printk("APIC delivery error (%lx).\n", accept_status);
765 return (send_status | accept_status);
767 #endif /* WAKE_SECONDARY_VIA_NMI */
769 #ifdef WAKE_SECONDARY_VIA_INIT
771 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
773 unsigned long send_status = 0, accept_status = 0;
774 int maxlvt, timeout, num_starts, j;
777 * Be paranoid about clearing APIC errors.
779 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
780 apic_read_around(APIC_SPIV);
781 apic_write(APIC_ESR, 0);
785 Dprintk("Asserting INIT.\n");
788 * Turn INIT on target chip
790 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
795 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
798 Dprintk("Waiting for send to finish...\n");
803 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
804 } while (send_status && (timeout++ < 1000));
808 Dprintk("Deasserting INIT.\n");
811 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
814 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
816 Dprintk("Waiting for send to finish...\n");
821 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
822 } while (send_status && (timeout++ < 1000));
824 atomic_set(&init_deasserted, 1);
827 * Should we send STARTUP IPIs ?
829 * Determine this based on the APIC version.
830 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
832 if (APIC_INTEGRATED(apic_version[phys_apicid]))
838 * Paravirt / VMI wants a startup IPI hook here to set up the
839 * target processor state.
841 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
842 (unsigned long) stack_start.esp);
845 * Run STARTUP IPI loop.
847 Dprintk("#startup loops: %d.\n", num_starts);
849 maxlvt = get_maxlvt();
851 for (j = 1; j <= num_starts; j++) {
852 Dprintk("Sending STARTUP #%d.\n",j);
853 apic_read_around(APIC_SPIV);
854 apic_write(APIC_ESR, 0);
856 Dprintk("After apic_write.\n");
863 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
865 /* Boot on the stack */
866 /* Kick the second */
867 apic_write_around(APIC_ICR, APIC_DM_STARTUP
868 | (start_eip >> 12));
871 * Give the other CPU some time to accept the IPI.
875 Dprintk("Startup point 1.\n");
877 Dprintk("Waiting for send to finish...\n");
882 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
883 } while (send_status && (timeout++ < 1000));
886 * Give the other CPU some time to accept the IPI.
890 * Due to the Pentium erratum 3AP.
893 apic_read_around(APIC_SPIV);
894 apic_write(APIC_ESR, 0);
896 accept_status = (apic_read(APIC_ESR) & 0xEF);
897 if (send_status || accept_status)
900 Dprintk("After Startup.\n");
903 printk("APIC never delivered???\n");
905 printk("APIC delivery error (%lx).\n", accept_status);
907 return (send_status | accept_status);
909 #endif /* WAKE_SECONDARY_VIA_INIT */
911 extern cpumask_t cpu_initialized;
912 static inline int alloc_cpu_id(void)
916 cpus_complement(tmp_map, cpu_present_map);
917 cpu = first_cpu(tmp_map);
923 #ifdef CONFIG_HOTPLUG_CPU
924 static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS];
925 static inline struct task_struct * alloc_idle_task(int cpu)
927 struct task_struct *idle;
929 if ((idle = cpu_idle_tasks[cpu]) != NULL) {
930 /* initialize thread_struct. we really want to avoid destroy
933 idle->thread.esp = (unsigned long)task_pt_regs(idle);
934 init_idle(idle, cpu);
937 idle = fork_idle(cpu);
940 cpu_idle_tasks[cpu] = idle;
944 #define alloc_idle_task(cpu) fork_idle(cpu)
947 static int __cpuinit do_boot_cpu(int apicid, int cpu)
949 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
950 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
951 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
954 struct task_struct *idle;
955 unsigned long boot_error;
957 unsigned long start_eip;
958 unsigned short nmi_high = 0, nmi_low = 0;
961 * We can't use kernel_thread since we must avoid to
962 * reschedule the child.
964 idle = alloc_idle_task(cpu);
966 panic("failed fork for CPU %d", cpu);
968 /* Pre-allocate and initialize the CPU's GDT and PDA so it
969 doesn't have to do any memory allocation during the
970 delicate CPU-bringup phase. */
971 if (!init_gdt(cpu, idle)) {
972 printk(KERN_INFO "Couldn't allocate GDT/PDA for CPU %d\n", cpu);
976 idle->thread.eip = (unsigned long) start_secondary;
977 /* start_eip had better be page-aligned! */
978 start_eip = setup_trampoline();
981 alternatives_smp_switch(1);
983 /* So we see what's up */
984 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
985 /* Stack for startup_32 can be just as for start_secondary onwards */
986 stack_start.esp = (void *) idle->thread.esp;
990 x86_cpu_to_apicid[cpu] = apicid;
992 * This grunge runs the startup process for
993 * the targeted processor.
996 atomic_set(&init_deasserted, 0);
998 Dprintk("Setting warm reset code and vector.\n");
1000 store_NMI_vector(&nmi_high, &nmi_low);
1002 smpboot_setup_warm_reset_vector(start_eip);
1005 * Starting actual IPI sequence...
1007 boot_error = wakeup_secondary_cpu(apicid, start_eip);
1011 * allow APs to start initializing.
1013 Dprintk("Before Callout %d.\n", cpu);
1014 cpu_set(cpu, cpu_callout_map);
1015 Dprintk("After Callout %d.\n", cpu);
1018 * Wait 5s total for a response
1020 for (timeout = 0; timeout < 50000; timeout++) {
1021 if (cpu_isset(cpu, cpu_callin_map))
1022 break; /* It has booted */
1026 if (cpu_isset(cpu, cpu_callin_map)) {
1027 /* number CPUs logically, starting from 1 (BSP is 0) */
1029 printk("CPU%d: ", cpu);
1030 print_cpu_info(&cpu_data[cpu]);
1031 Dprintk("CPU has booted.\n");
1034 if (*((volatile unsigned char *)trampoline_base)
1036 /* trampoline started but...? */
1037 printk("Stuck ??\n");
1039 /* trampoline code not run */
1040 printk("Not responding.\n");
1041 inquire_remote_apic(apicid);
1046 /* Try to put things back the way they were before ... */
1047 unmap_cpu_to_logical_apicid(cpu);
1048 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
1049 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
1052 x86_cpu_to_apicid[cpu] = apicid;
1053 cpu_set(cpu, cpu_present_map);
1056 /* mark "stuck" area as not stuck */
1057 *((volatile unsigned long *)trampoline_base) = 0;
1062 #ifdef CONFIG_HOTPLUG_CPU
1063 void cpu_exit_clear(void)
1065 int cpu = raw_smp_processor_id();
1073 cpu_clear(cpu, cpu_callout_map);
1074 cpu_clear(cpu, cpu_callin_map);
1076 cpu_clear(cpu, smp_commenced_mask);
1077 unmap_cpu_to_logical_apicid(cpu);
1080 struct warm_boot_cpu_info {
1081 struct completion *complete;
1082 struct work_struct task;
1087 static void __cpuinit do_warm_boot_cpu(struct work_struct *work)
1089 struct warm_boot_cpu_info *info =
1090 container_of(work, struct warm_boot_cpu_info, task);
1091 do_boot_cpu(info->apicid, info->cpu);
1092 complete(info->complete);
1095 static int __cpuinit __smp_prepare_cpu(int cpu)
1097 DECLARE_COMPLETION_ONSTACK(done);
1098 struct warm_boot_cpu_info info;
1100 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
1102 apicid = x86_cpu_to_apicid[cpu];
1103 if (apicid == BAD_APICID) {
1109 * the CPU isn't initialized at boot time, allocate gdt table here.
1110 * cpu_init will initialize it
1112 if (!cpu_gdt_descr->address) {
1113 cpu_gdt_descr->address = get_zeroed_page(GFP_KERNEL);
1114 if (!cpu_gdt_descr->address)
1115 printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu);
1120 info.complete = &done;
1121 info.apicid = apicid;
1123 INIT_WORK(&info.task, do_warm_boot_cpu);
1125 tsc_sync_disabled = 1;
1127 /* init low mem mapping */
1128 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1129 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
1131 schedule_work(&info.task);
1132 wait_for_completion(&done);
1134 tsc_sync_disabled = 0;
1142 static void smp_tune_scheduling(void)
1144 unsigned long cachesize; /* kB */
1147 cachesize = boot_cpu_data.x86_cache_size;
1150 max_cache_size = cachesize * 1024;
1155 * Cycle through the processors sending APIC IPIs to boot each.
1158 static int boot_cpu_logical_apicid;
1159 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1161 #ifdef CONFIG_X86_NUMAQ
1162 EXPORT_SYMBOL(xquad_portio);
1165 static void __init smp_boot_cpus(unsigned int max_cpus)
1167 int apicid, cpu, bit, kicked;
1168 unsigned long bogosum = 0;
1171 * Setup boot CPU information
1173 smp_store_cpu_info(0); /* Final full version of the data */
1174 printk("CPU%d: ", 0);
1175 print_cpu_info(&cpu_data[0]);
1177 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1178 boot_cpu_logical_apicid = logical_smp_processor_id();
1179 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1181 current_thread_info()->cpu = 0;
1182 smp_tune_scheduling();
1184 set_cpu_sibling_map(0);
1187 * If we couldn't find an SMP configuration at boot time,
1188 * get out of here now!
1190 if (!smp_found_config && !acpi_lapic) {
1191 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1192 smpboot_clear_io_apic_irqs();
1193 phys_cpu_present_map = physid_mask_of_physid(0);
1194 if (APIC_init_uniprocessor())
1195 printk(KERN_NOTICE "Local APIC not detected."
1196 " Using dummy APIC emulation.\n");
1197 map_cpu_to_logical_apicid();
1198 cpu_set(0, cpu_sibling_map[0]);
1199 cpu_set(0, cpu_core_map[0]);
1204 * Should not be necessary because the MP table should list the boot
1205 * CPU too, but we do it for the sake of robustness anyway.
1206 * Makes no sense to do this check in clustered apic mode, so skip it
1208 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1209 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1210 boot_cpu_physical_apicid);
1211 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1215 * If we couldn't find a local APIC, then get out of here now!
1217 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1218 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1219 boot_cpu_physical_apicid);
1220 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1221 smpboot_clear_io_apic_irqs();
1222 phys_cpu_present_map = physid_mask_of_physid(0);
1223 cpu_set(0, cpu_sibling_map[0]);
1224 cpu_set(0, cpu_core_map[0]);
1228 verify_local_APIC();
1231 * If SMP should be disabled, then really disable it!
1234 smp_found_config = 0;
1235 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1236 smpboot_clear_io_apic_irqs();
1237 phys_cpu_present_map = physid_mask_of_physid(0);
1238 cpu_set(0, cpu_sibling_map[0]);
1239 cpu_set(0, cpu_core_map[0]);
1245 map_cpu_to_logical_apicid();
1248 setup_portio_remap();
1251 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1253 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1254 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1255 * clustered apic ID.
1257 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1260 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1261 apicid = cpu_present_to_apicid(bit);
1263 * Don't even attempt to start the boot CPU!
1265 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1268 if (!check_apicid_present(bit))
1270 if (max_cpus <= cpucount+1)
1273 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1274 printk("CPU #%d not responding - cannot use it.\n",
1281 * Cleanup possible dangling ends...
1283 smpboot_restore_warm_reset_vector();
1286 * Allow the user to impress friends.
1288 Dprintk("Before bogomips.\n");
1289 for (cpu = 0; cpu < NR_CPUS; cpu++)
1290 if (cpu_isset(cpu, cpu_callout_map))
1291 bogosum += cpu_data[cpu].loops_per_jiffy;
1293 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1295 bogosum/(500000/HZ),
1296 (bogosum/(5000/HZ))%100);
1298 Dprintk("Before bogocount - setting activated=1.\n");
1301 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1304 * Don't taint if we are running SMP kernel on a single non-MP
1307 if (tainted & TAINT_UNSAFE_SMP) {
1309 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1311 tainted &= ~TAINT_UNSAFE_SMP;
1314 Dprintk("Boot done.\n");
1317 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1320 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1321 cpus_clear(cpu_sibling_map[cpu]);
1322 cpus_clear(cpu_core_map[cpu]);
1325 cpu_set(0, cpu_sibling_map[0]);
1326 cpu_set(0, cpu_core_map[0]);
1328 smpboot_setup_io_apic();
1330 setup_boot_APIC_clock();
1333 * Synchronize the TSC with the AP
1335 if (cpu_has_tsc && cpucount && cpu_khz)
1336 synchronize_tsc_bp();
1339 /* These are wrappers to interface to the new boot process. Someone
1340 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1341 void __init smp_prepare_cpus(unsigned int max_cpus)
1343 smp_commenced_mask = cpumask_of_cpu(0);
1344 cpu_callin_map = cpumask_of_cpu(0);
1346 smp_boot_cpus(max_cpus);
1349 void __devinit smp_prepare_boot_cpu(void)
1351 cpu_set(smp_processor_id(), cpu_online_map);
1352 cpu_set(smp_processor_id(), cpu_callout_map);
1353 cpu_set(smp_processor_id(), cpu_present_map);
1354 cpu_set(smp_processor_id(), cpu_possible_map);
1355 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
1358 #ifdef CONFIG_HOTPLUG_CPU
1360 remove_siblinginfo(int cpu)
1363 struct cpuinfo_x86 *c = cpu_data;
1365 for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
1366 cpu_clear(cpu, cpu_core_map[sibling]);
1368 * last thread sibling in this cpu core going down
1370 if (cpus_weight(cpu_sibling_map[cpu]) == 1)
1371 c[sibling].booted_cores--;
1374 for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
1375 cpu_clear(cpu, cpu_sibling_map[sibling]);
1376 cpus_clear(cpu_sibling_map[cpu]);
1377 cpus_clear(cpu_core_map[cpu]);
1378 c[cpu].phys_proc_id = 0;
1379 c[cpu].cpu_core_id = 0;
1380 cpu_clear(cpu, cpu_sibling_setup_map);
1383 int __cpu_disable(void)
1385 cpumask_t map = cpu_online_map;
1386 int cpu = smp_processor_id();
1389 * Perhaps use cpufreq to drop frequency, but that could go
1390 * into generic code.
1392 * We won't take down the boot processor on i386 due to some
1393 * interrupts only being able to be serviced by the BSP.
1394 * Especially so if we're not using an IOAPIC -zwane
1398 if (nmi_watchdog == NMI_LOCAL_APIC)
1399 stop_apic_nmi_watchdog(NULL);
1401 /* Allow any queued timer interrupts to get serviced */
1404 local_irq_disable();
1406 remove_siblinginfo(cpu);
1408 cpu_clear(cpu, map);
1410 /* It's now safe to remove this processor from the online map */
1411 cpu_clear(cpu, cpu_online_map);
1415 void __cpu_die(unsigned int cpu)
1417 /* We don't do anything here: idle task is faking death itself. */
1420 for (i = 0; i < 10; i++) {
1421 /* They ack this in play_dead by setting CPU_DEAD */
1422 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1423 printk ("CPU %d is now offline\n", cpu);
1424 if (1 == num_online_cpus())
1425 alternatives_smp_switch(0);
1430 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1432 #else /* ... !CONFIG_HOTPLUG_CPU */
1433 int __cpu_disable(void)
1438 void __cpu_die(unsigned int cpu)
1440 /* We said "no" in __cpu_disable */
1443 #endif /* CONFIG_HOTPLUG_CPU */
1445 int __cpuinit __cpu_up(unsigned int cpu)
1447 #ifdef CONFIG_HOTPLUG_CPU
1451 * We do warm boot only on cpus that had booted earlier
1452 * Otherwise cold boot is all handled from smp_boot_cpus().
1453 * cpu_callin_map is set during AP kickstart process. Its reset
1454 * when a cpu is taken offline from cpu_exit_clear().
1456 if (!cpu_isset(cpu, cpu_callin_map))
1457 ret = __smp_prepare_cpu(cpu);
1463 /* In case one didn't come up */
1464 if (!cpu_isset(cpu, cpu_callin_map)) {
1465 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1471 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1472 /* Unleash the CPU! */
1473 cpu_set(cpu, smp_commenced_mask);
1474 while (!cpu_isset(cpu, cpu_online_map))
1477 #ifdef CONFIG_X86_GENERICARCH
1478 if (num_online_cpus() > 8 && genapic == &apic_default)
1479 panic("Default flat APIC routing can't be used with > 8 cpus\n");
1485 void __init smp_cpus_done(unsigned int max_cpus)
1487 #ifdef CONFIG_X86_IO_APIC
1488 setup_ioapic_dest();
1491 #ifndef CONFIG_HOTPLUG_CPU
1493 * Disable executability of the SMP trampoline:
1495 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1499 void __init smp_intr_init(void)
1502 * IRQ0 must be given a fixed assignment and initialized,
1503 * because it's used before the IO-APIC is set up.
1505 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1508 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1509 * IPI, driven by wakeup.
1511 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1513 /* IPI for invalidation */
1514 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1516 /* IPI for generic function call */
1517 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1521 * If the BIOS enumerates physical processors before logical,
1522 * maxcpus=N at enumeration-time can be used to disable HT.
1524 static int __init parse_maxcpus(char *arg)
1526 extern unsigned int maxcpus;
1528 maxcpus = simple_strtoul(arg, NULL, 0);
1531 early_param("maxcpus", parse_maxcpus);