2 * machine_kexec.c - handle transition of Linux booting another kernel
3 * Copyright (C) 2002-2005 Eric Biederman <ebiederm@xmission.com>
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
10 #include <linux/kexec.h>
11 #include <linux/delay.h>
12 #include <asm/pgtable.h>
13 #include <asm/pgalloc.h>
14 #include <asm/tlbflush.h>
15 #include <asm/mmu_context.h>
18 #include <asm/cpufeature.h>
20 #include <asm/system.h>
22 #define PAGE_ALIGNED __attribute__ ((__aligned__(PAGE_SIZE)))
24 #define L0_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
25 #define L1_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
26 #define L2_ATTR (_PAGE_PRESENT)
28 #define LEVEL0_SIZE (1UL << 12UL)
30 #ifndef CONFIG_X86_PAE
31 #define LEVEL1_SIZE (1UL << 22UL)
32 static u32 pgtable_level1[1024] PAGE_ALIGNED;
34 static void identity_map_page(unsigned long address)
36 unsigned long level1_index, level2_index;
39 /* Find the current page table */
40 pgtable_level2 = __va(read_cr3());
42 /* Find the indexes of the physical address to identity map */
43 level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
44 level2_index = address / LEVEL1_SIZE;
46 /* Identity map the page table entry */
47 pgtable_level1[level1_index] = address | L0_ATTR;
48 pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
50 /* Flush the tlb so the new mapping takes effect.
51 * Global tlb entries are not flushed but that is not an issue.
53 load_cr3(pgtable_level2);
57 #define LEVEL1_SIZE (1UL << 21UL)
58 #define LEVEL2_SIZE (1UL << 30UL)
59 static u64 pgtable_level1[512] PAGE_ALIGNED;
60 static u64 pgtable_level2[512] PAGE_ALIGNED;
62 static void identity_map_page(unsigned long address)
64 unsigned long level1_index, level2_index, level3_index;
67 /* Find the current page table */
68 pgtable_level3 = __va(read_cr3());
70 /* Find the indexes of the physical address to identity map */
71 level1_index = (address % LEVEL1_SIZE)/LEVEL0_SIZE;
72 level2_index = (address % LEVEL2_SIZE)/LEVEL1_SIZE;
73 level3_index = address / LEVEL2_SIZE;
75 /* Identity map the page table entry */
76 pgtable_level1[level1_index] = address | L0_ATTR;
77 pgtable_level2[level2_index] = __pa(pgtable_level1) | L1_ATTR;
78 set_64bit(&pgtable_level3[level3_index],
79 __pa(pgtable_level2) | L2_ATTR);
81 /* Flush the tlb so the new mapping takes effect.
82 * Global tlb entries are not flushed but that is not an issue.
84 load_cr3(pgtable_level3);
88 static void set_idt(void *newidt, __u16 limit)
90 struct Xgt_desc_struct curidt;
92 /* ia32 supports unaliged loads & stores */
94 curidt.address = (unsigned long)newidt;
96 __asm__ __volatile__ (
103 static void set_gdt(void *newgdt, __u16 limit)
105 struct Xgt_desc_struct curgdt;
107 /* ia32 supports unaligned loads & stores */
109 curgdt.address = (unsigned long)newgdt;
111 __asm__ __volatile__ (
117 static void load_segments(void)
120 #define STR(X) __STR(X)
122 __asm__ __volatile__ (
123 "\tljmp $"STR(__KERNEL_CS)",$1f\n"
125 "\tmovl $"STR(__KERNEL_DS)",%eax\n"
136 typedef asmlinkage NORET_TYPE void (*relocate_new_kernel_t)(
137 unsigned long indirection_page,
138 unsigned long reboot_code_buffer,
139 unsigned long start_address,
140 unsigned int has_pae) ATTRIB_NORET;
142 const extern unsigned char relocate_new_kernel[];
143 extern void relocate_new_kernel_end(void);
144 const extern unsigned int relocate_new_kernel_size;
147 * A architecture hook called to validate the
148 * proposed image and prepare the control pages
149 * as needed. The pages for KEXEC_CONTROL_CODE_SIZE
150 * have been allocated, but the segments have yet
151 * been copied into the kernel.
153 * Do what every setup is needed on image and the
154 * reboot code buffer to allow us to avoid allocations
159 int machine_kexec_prepare(struct kimage *image)
165 * Undo anything leftover by machine_kexec_prepare
166 * when an image is freed.
168 void machine_kexec_cleanup(struct kimage *image)
173 * Do not allocate memory (or fail in any way) in machine_kexec().
174 * We are past the point of no return, committed to rebooting now.
176 NORET_TYPE void machine_kexec(struct kimage *image)
178 unsigned long page_list;
179 unsigned long reboot_code_buffer;
181 relocate_new_kernel_t rnk;
183 /* Interrupts aren't acceptable while we reboot */
186 /* Compute some offsets */
187 reboot_code_buffer = page_to_pfn(image->control_code_page)
189 page_list = image->head;
191 /* Set up an identity mapping for the reboot_code_buffer */
192 identity_map_page(reboot_code_buffer);
195 memcpy((void *)reboot_code_buffer, relocate_new_kernel,
196 relocate_new_kernel_size);
198 /* The segment registers are funny things, they are
199 * automatically loaded from a table, in memory wherever you
200 * set them to a specific selector, but this table is never
201 * accessed again you set the segment to a different selector.
203 * The more common model is are caches where the behide
204 * the scenes work is done, but is also dropped at arbitrary
207 * I take advantage of this here by force loading the
208 * segments, before I zap the gdt with an invalid value.
211 /* The gdt & idt are now invalid.
212 * If you want to load them you must set up your own idt & gdt.
214 set_gdt(phys_to_virt(0),0);
215 set_idt(phys_to_virt(0),0);
218 rnk = (relocate_new_kernel_t) reboot_code_buffer;
219 (*rnk)(page_list, reboot_code_buffer, image->start, cpu_has_pae);