2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
42 #include <asm/msidef.h>
43 #include <asm/hypertransport.h>
45 #include <mach_apic.h>
46 #include <mach_apicdef.h>
50 int (*ioapic_renumber_irq)(int ioapic, int irq);
51 atomic_t irq_mis_count;
53 /* Where if anywhere is the i8259 connect in external int mode */
54 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
56 static DEFINE_SPINLOCK(ioapic_lock);
57 static DEFINE_SPINLOCK(vector_lock);
59 int timer_over_8254 __initdata = 1;
62 * Is the SiS APIC rmw bug present ?
63 * -1 = don't know, 0 = no, 1 = yes
65 int sis_apic_bug = -1;
68 * # of IRQ routing registers
70 int nr_ioapic_registers[MAX_IO_APICS];
72 static int disable_timer_pin_1 __initdata;
75 * Rough estimation of how many shared IRQs there are, can
78 #define MAX_PLUS_SHARED_IRQS NR_IRQS
79 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
82 * This is performance-critical, we want to do it O(1)
84 * the indexing order of this array favors 1:1 mappings
85 * between pins and IRQs.
88 static struct irq_pin_list {
90 } irq_2_pin[PIN_MAP_SIZE];
93 struct { u32 w1, w2; };
94 struct IO_APIC_route_entry entry;
97 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
101 spin_lock_irqsave(&ioapic_lock, flags);
102 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
103 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
104 spin_unlock_irqrestore(&ioapic_lock, flags);
108 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
111 union entry_union eu;
113 spin_lock_irqsave(&ioapic_lock, flags);
114 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
115 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
116 spin_unlock_irqrestore(&ioapic_lock, flags);
120 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
121 * shared ISA-space IRQs, so we have to support them. We are super
122 * fast in the common case, and fast for shared ISA-space IRQs.
124 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
126 static int first_free_entry = NR_IRQS;
127 struct irq_pin_list *entry = irq_2_pin + irq;
130 entry = irq_2_pin + entry->next;
132 if (entry->pin != -1) {
133 entry->next = first_free_entry;
134 entry = irq_2_pin + entry->next;
135 if (++first_free_entry >= PIN_MAP_SIZE)
136 panic("io_apic.c: whoops");
143 * Reroute an IRQ to a different pin.
145 static void __init replace_pin_at_irq(unsigned int irq,
146 int oldapic, int oldpin,
147 int newapic, int newpin)
149 struct irq_pin_list *entry = irq_2_pin + irq;
152 if (entry->apic == oldapic && entry->pin == oldpin) {
153 entry->apic = newapic;
158 entry = irq_2_pin + entry->next;
162 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
164 struct irq_pin_list *entry = irq_2_pin + irq;
165 unsigned int pin, reg;
171 reg = io_apic_read(entry->apic, 0x10 + pin*2);
174 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
177 entry = irq_2_pin + entry->next;
182 static void __mask_IO_APIC_irq (unsigned int irq)
184 __modify_IO_APIC_irq(irq, 0x00010000, 0);
188 static void __unmask_IO_APIC_irq (unsigned int irq)
190 __modify_IO_APIC_irq(irq, 0, 0x00010000);
193 /* mask = 1, trigger = 0 */
194 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
196 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
199 /* mask = 0, trigger = 1 */
200 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
202 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
205 static void mask_IO_APIC_irq (unsigned int irq)
209 spin_lock_irqsave(&ioapic_lock, flags);
210 __mask_IO_APIC_irq(irq);
211 spin_unlock_irqrestore(&ioapic_lock, flags);
214 static void unmask_IO_APIC_irq (unsigned int irq)
218 spin_lock_irqsave(&ioapic_lock, flags);
219 __unmask_IO_APIC_irq(irq);
220 spin_unlock_irqrestore(&ioapic_lock, flags);
223 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
225 struct IO_APIC_route_entry entry;
227 /* Check delivery_mode to be sure we're not clearing an SMI pin */
228 entry = ioapic_read_entry(apic, pin);
229 if (entry.delivery_mode == dest_SMI)
233 * Disable it in the IO-APIC irq-routing table:
235 memset(&entry, 0, sizeof(entry));
237 ioapic_write_entry(apic, pin, entry);
240 static void clear_IO_APIC (void)
244 for (apic = 0; apic < nr_ioapics; apic++)
245 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
246 clear_IO_APIC_pin(apic, pin);
250 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
254 struct irq_pin_list *entry = irq_2_pin + irq;
255 unsigned int apicid_value;
258 cpus_and(tmp, cpumask, cpu_online_map);
262 cpus_and(cpumask, tmp, CPU_MASK_ALL);
264 apicid_value = cpu_mask_to_apicid(cpumask);
265 /* Prepare to do the io_apic_write */
266 apicid_value = apicid_value << 24;
267 spin_lock_irqsave(&ioapic_lock, flags);
272 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
275 entry = irq_2_pin + entry->next;
277 set_native_irq_info(irq, cpumask);
278 spin_unlock_irqrestore(&ioapic_lock, flags);
281 #if defined(CONFIG_IRQBALANCE)
282 # include <asm/processor.h> /* kernel_thread() */
283 # include <linux/kernel_stat.h> /* kstat */
284 # include <linux/slab.h> /* kmalloc() */
285 # include <linux/timer.h> /* time_after() */
287 #ifdef CONFIG_BALANCED_IRQ_DEBUG
288 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
289 # define Dprintk(x...) do { TDprintk(x); } while (0)
291 # define TDprintk(x...)
292 # define Dprintk(x...)
295 #define IRQBALANCE_CHECK_ARCH -999
296 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
297 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
298 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
299 #define BALANCED_IRQ_LESS_DELTA (HZ)
301 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
302 static int physical_balance __read_mostly;
303 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
305 static struct irq_cpu_info {
306 unsigned long * last_irq;
307 unsigned long * irq_delta;
309 } irq_cpu_data[NR_CPUS];
311 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
312 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
313 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
315 #define IDLE_ENOUGH(cpu,now) \
316 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
318 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
320 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
322 static cpumask_t balance_irq_affinity[NR_IRQS] = {
323 [0 ... NR_IRQS-1] = CPU_MASK_ALL
326 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
328 balance_irq_affinity[irq] = mask;
331 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
332 unsigned long now, int direction)
340 if (unlikely(cpu == curr_cpu))
343 if (direction == 1) {
352 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
353 (search_idle && !IDLE_ENOUGH(cpu,now)));
358 static inline void balance_irq(int cpu, int irq)
360 unsigned long now = jiffies;
361 cpumask_t allowed_mask;
362 unsigned int new_cpu;
364 if (irqbalance_disabled)
367 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
368 new_cpu = move(cpu, allowed_mask, now, 1);
369 if (cpu != new_cpu) {
370 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
374 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
377 Dprintk("Rotating IRQs among CPUs.\n");
378 for_each_online_cpu(i) {
379 for (j = 0; j < NR_IRQS; j++) {
380 if (!irq_desc[j].action)
382 /* Is it a significant load ? */
383 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
384 useful_load_threshold)
389 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
390 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
394 static void do_irq_balance(void)
397 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
398 unsigned long move_this_load = 0;
399 int max_loaded = 0, min_loaded = 0;
401 unsigned long useful_load_threshold = balanced_irq_interval + 10;
403 int tmp_loaded, first_attempt = 1;
404 unsigned long tmp_cpu_irq;
405 unsigned long imbalance = 0;
406 cpumask_t allowed_mask, target_cpu_mask, tmp;
408 for_each_possible_cpu(i) {
413 package_index = CPU_TO_PACKAGEINDEX(i);
414 for (j = 0; j < NR_IRQS; j++) {
415 unsigned long value_now, delta;
416 /* Is this an active IRQ? */
417 if (!irq_desc[j].action)
419 if ( package_index == i )
420 IRQ_DELTA(package_index,j) = 0;
421 /* Determine the total count per processor per IRQ */
422 value_now = (unsigned long) kstat_cpu(i).irqs[j];
424 /* Determine the activity per processor per IRQ */
425 delta = value_now - LAST_CPU_IRQ(i,j);
427 /* Update last_cpu_irq[][] for the next time */
428 LAST_CPU_IRQ(i,j) = value_now;
430 /* Ignore IRQs whose rate is less than the clock */
431 if (delta < useful_load_threshold)
433 /* update the load for the processor or package total */
434 IRQ_DELTA(package_index,j) += delta;
436 /* Keep track of the higher numbered sibling as well */
437 if (i != package_index)
440 * We have sibling A and sibling B in the package
442 * cpu_irq[A] = load for cpu A + load for cpu B
443 * cpu_irq[B] = load for cpu B
445 CPU_IRQ(package_index) += delta;
448 /* Find the least loaded processor package */
449 for_each_online_cpu(i) {
450 if (i != CPU_TO_PACKAGEINDEX(i))
452 if (min_cpu_irq > CPU_IRQ(i)) {
453 min_cpu_irq = CPU_IRQ(i);
457 max_cpu_irq = ULONG_MAX;
460 /* Look for heaviest loaded processor.
461 * We may come back to get the next heaviest loaded processor.
462 * Skip processors with trivial loads.
466 for_each_online_cpu(i) {
467 if (i != CPU_TO_PACKAGEINDEX(i))
469 if (max_cpu_irq <= CPU_IRQ(i))
471 if (tmp_cpu_irq < CPU_IRQ(i)) {
472 tmp_cpu_irq = CPU_IRQ(i);
477 if (tmp_loaded == -1) {
478 /* In the case of small number of heavy interrupt sources,
479 * loading some of the cpus too much. We use Ingo's original
480 * approach to rotate them around.
482 if (!first_attempt && imbalance >= useful_load_threshold) {
483 rotate_irqs_among_cpus(useful_load_threshold);
486 goto not_worth_the_effort;
489 first_attempt = 0; /* heaviest search */
490 max_cpu_irq = tmp_cpu_irq; /* load */
491 max_loaded = tmp_loaded; /* processor */
492 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
494 Dprintk("max_loaded cpu = %d\n", max_loaded);
495 Dprintk("min_loaded cpu = %d\n", min_loaded);
496 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
497 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
498 Dprintk("load imbalance = %lu\n", imbalance);
500 /* if imbalance is less than approx 10% of max load, then
501 * observe diminishing returns action. - quit
503 if (imbalance < (max_cpu_irq >> 3)) {
504 Dprintk("Imbalance too trivial\n");
505 goto not_worth_the_effort;
509 /* if we select an IRQ to move that can't go where we want, then
510 * see if there is another one to try.
514 for (j = 0; j < NR_IRQS; j++) {
515 /* Is this an active IRQ? */
516 if (!irq_desc[j].action)
518 if (imbalance <= IRQ_DELTA(max_loaded,j))
520 /* Try to find the IRQ that is closest to the imbalance
521 * without going over.
523 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
524 move_this_load = IRQ_DELTA(max_loaded,j);
528 if (selected_irq == -1) {
532 imbalance = move_this_load;
534 /* For physical_balance case, we accumlated both load
535 * values in the one of the siblings cpu_irq[],
536 * to use the same code for physical and logical processors
537 * as much as possible.
539 * NOTE: the cpu_irq[] array holds the sum of the load for
540 * sibling A and sibling B in the slot for the lowest numbered
541 * sibling (A), _AND_ the load for sibling B in the slot for
542 * the higher numbered sibling.
544 * We seek the least loaded sibling by making the comparison
547 load = CPU_IRQ(min_loaded) >> 1;
548 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
549 if (load > CPU_IRQ(j)) {
550 /* This won't change cpu_sibling_map[min_loaded] */
556 cpus_and(allowed_mask,
558 balance_irq_affinity[selected_irq]);
559 target_cpu_mask = cpumask_of_cpu(min_loaded);
560 cpus_and(tmp, target_cpu_mask, allowed_mask);
562 if (!cpus_empty(tmp)) {
564 Dprintk("irq = %d moved to cpu = %d\n",
565 selected_irq, min_loaded);
566 /* mark for change destination */
567 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
569 /* Since we made a change, come back sooner to
570 * check for more variation.
572 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
573 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
578 not_worth_the_effort:
580 * if we did not find an IRQ to move, then adjust the time interval
583 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
584 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
585 Dprintk("IRQ worth rotating not found\n");
589 static int balanced_irq(void *unused)
592 unsigned long prev_balance_time = jiffies;
593 long time_remaining = balanced_irq_interval;
597 /* push everything to CPU 0 to give us a starting point. */
598 for (i = 0 ; i < NR_IRQS ; i++) {
599 irq_desc[i].pending_mask = cpumask_of_cpu(0);
600 set_pending_irq(i, cpumask_of_cpu(0));
604 time_remaining = schedule_timeout_interruptible(time_remaining);
606 if (time_after(jiffies,
607 prev_balance_time+balanced_irq_interval)) {
610 prev_balance_time = jiffies;
611 time_remaining = balanced_irq_interval;
618 static int __init balanced_irq_init(void)
621 struct cpuinfo_x86 *c;
624 cpus_shift_right(tmp, cpu_online_map, 2);
626 /* When not overwritten by the command line ask subarchitecture. */
627 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
628 irqbalance_disabled = NO_BALANCE_IRQ;
629 if (irqbalance_disabled)
632 /* disable irqbalance completely if there is only one processor online */
633 if (num_online_cpus() < 2) {
634 irqbalance_disabled = 1;
638 * Enable physical balance only if more than 1 physical processor
641 if (smp_num_siblings > 1 && !cpus_empty(tmp))
642 physical_balance = 1;
644 for_each_online_cpu(i) {
645 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
646 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
647 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
648 printk(KERN_ERR "balanced_irq_init: out of memory");
651 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
652 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
655 printk(KERN_INFO "Starting balanced_irq\n");
656 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
659 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
661 for_each_possible_cpu(i) {
662 kfree(irq_cpu_data[i].irq_delta);
663 irq_cpu_data[i].irq_delta = NULL;
664 kfree(irq_cpu_data[i].last_irq);
665 irq_cpu_data[i].last_irq = NULL;
670 int __init irqbalance_disable(char *str)
672 irqbalance_disabled = 1;
676 __setup("noirqbalance", irqbalance_disable);
678 late_initcall(balanced_irq_init);
679 #endif /* CONFIG_IRQBALANCE */
680 #endif /* CONFIG_SMP */
683 void fastcall send_IPI_self(int vector)
690 apic_wait_icr_idle();
691 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
693 * Send the IPI. The write to APIC_ICR fires this off.
695 apic_write_around(APIC_ICR, cfg);
697 #endif /* !CONFIG_SMP */
701 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
702 * specific CPU-side IRQs.
706 static int pirq_entries [MAX_PIRQS];
707 static int pirqs_enabled;
708 int skip_ioapic_setup;
710 static int __init ioapic_setup(char *str)
712 skip_ioapic_setup = 1;
716 __setup("noapic", ioapic_setup);
718 static int __init ioapic_pirq_setup(char *str)
721 int ints[MAX_PIRQS+1];
723 get_options(str, ARRAY_SIZE(ints), ints);
725 for (i = 0; i < MAX_PIRQS; i++)
726 pirq_entries[i] = -1;
729 apic_printk(APIC_VERBOSE, KERN_INFO
730 "PIRQ redirection, working around broken MP-BIOS.\n");
732 if (ints[0] < MAX_PIRQS)
735 for (i = 0; i < max; i++) {
736 apic_printk(APIC_VERBOSE, KERN_DEBUG
737 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
739 * PIRQs are mapped upside down, usually.
741 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
746 __setup("pirq=", ioapic_pirq_setup);
749 * Find the IRQ entry number of a certain pin.
751 static int find_irq_entry(int apic, int pin, int type)
755 for (i = 0; i < mp_irq_entries; i++)
756 if (mp_irqs[i].mpc_irqtype == type &&
757 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
758 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
759 mp_irqs[i].mpc_dstirq == pin)
766 * Find the pin to which IRQ[irq] (ISA) is connected
768 static int __init find_isa_irq_pin(int irq, int type)
772 for (i = 0; i < mp_irq_entries; i++) {
773 int lbus = mp_irqs[i].mpc_srcbus;
775 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
776 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
777 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
778 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
780 (mp_irqs[i].mpc_irqtype == type) &&
781 (mp_irqs[i].mpc_srcbusirq == irq))
783 return mp_irqs[i].mpc_dstirq;
788 static int __init find_isa_irq_apic(int irq, int type)
792 for (i = 0; i < mp_irq_entries; i++) {
793 int lbus = mp_irqs[i].mpc_srcbus;
795 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
796 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
797 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
798 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
800 (mp_irqs[i].mpc_irqtype == type) &&
801 (mp_irqs[i].mpc_srcbusirq == irq))
804 if (i < mp_irq_entries) {
806 for(apic = 0; apic < nr_ioapics; apic++) {
807 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
816 * Find a specific PCI IRQ entry.
817 * Not an __init, possibly needed by modules
819 static int pin_2_irq(int idx, int apic, int pin);
821 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
823 int apic, i, best_guess = -1;
825 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
826 "slot:%d, pin:%d.\n", bus, slot, pin);
827 if (mp_bus_id_to_pci_bus[bus] == -1) {
828 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
831 for (i = 0; i < mp_irq_entries; i++) {
832 int lbus = mp_irqs[i].mpc_srcbus;
834 for (apic = 0; apic < nr_ioapics; apic++)
835 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
836 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
839 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
840 !mp_irqs[i].mpc_irqtype &&
842 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
843 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
845 if (!(apic || IO_APIC_IRQ(irq)))
848 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
851 * Use the first all-but-pin matching entry as a
852 * best-guess fuzzy result for broken mptables.
860 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
863 * This function currently is only a helper for the i386 smp boot process where
864 * we need to reprogram the ioredtbls to cater for the cpus which have come online
865 * so mask in all cases should simply be TARGET_CPUS
868 void __init setup_ioapic_dest(void)
870 int pin, ioapic, irq, irq_entry;
872 if (skip_ioapic_setup == 1)
875 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
876 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
877 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
880 irq = pin_2_irq(irq_entry, ioapic, pin);
881 set_ioapic_affinity_irq(irq, TARGET_CPUS);
889 * EISA Edge/Level control register, ELCR
891 static int EISA_ELCR(unsigned int irq)
894 unsigned int port = 0x4d0 + (irq >> 3);
895 return (inb(port) >> (irq & 7)) & 1;
897 apic_printk(APIC_VERBOSE, KERN_INFO
898 "Broken MPtable reports ISA irq %d\n", irq);
902 /* EISA interrupts are always polarity zero and can be edge or level
903 * trigger depending on the ELCR value. If an interrupt is listed as
904 * EISA conforming in the MP table, that means its trigger type must
905 * be read in from the ELCR */
907 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
908 #define default_EISA_polarity(idx) (0)
910 /* ISA interrupts are always polarity zero edge triggered,
911 * when listed as conforming in the MP table. */
913 #define default_ISA_trigger(idx) (0)
914 #define default_ISA_polarity(idx) (0)
916 /* PCI interrupts are always polarity one level triggered,
917 * when listed as conforming in the MP table. */
919 #define default_PCI_trigger(idx) (1)
920 #define default_PCI_polarity(idx) (1)
922 /* MCA interrupts are always polarity zero level triggered,
923 * when listed as conforming in the MP table. */
925 #define default_MCA_trigger(idx) (1)
926 #define default_MCA_polarity(idx) (0)
928 /* NEC98 interrupts are always polarity zero edge triggered,
929 * when listed as conforming in the MP table. */
931 #define default_NEC98_trigger(idx) (0)
932 #define default_NEC98_polarity(idx) (0)
934 static int __init MPBIOS_polarity(int idx)
936 int bus = mp_irqs[idx].mpc_srcbus;
940 * Determine IRQ line polarity (high active or low active):
942 switch (mp_irqs[idx].mpc_irqflag & 3)
944 case 0: /* conforms, ie. bus-type dependent polarity */
946 switch (mp_bus_id_to_type[bus])
948 case MP_BUS_ISA: /* ISA pin */
950 polarity = default_ISA_polarity(idx);
953 case MP_BUS_EISA: /* EISA pin */
955 polarity = default_EISA_polarity(idx);
958 case MP_BUS_PCI: /* PCI pin */
960 polarity = default_PCI_polarity(idx);
963 case MP_BUS_MCA: /* MCA pin */
965 polarity = default_MCA_polarity(idx);
968 case MP_BUS_NEC98: /* NEC 98 pin */
970 polarity = default_NEC98_polarity(idx);
975 printk(KERN_WARNING "broken BIOS!!\n");
982 case 1: /* high active */
987 case 2: /* reserved */
989 printk(KERN_WARNING "broken BIOS!!\n");
993 case 3: /* low active */
998 default: /* invalid */
1000 printk(KERN_WARNING "broken BIOS!!\n");
1008 static int MPBIOS_trigger(int idx)
1010 int bus = mp_irqs[idx].mpc_srcbus;
1014 * Determine IRQ trigger mode (edge or level sensitive):
1016 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1018 case 0: /* conforms, ie. bus-type dependent */
1020 switch (mp_bus_id_to_type[bus])
1022 case MP_BUS_ISA: /* ISA pin */
1024 trigger = default_ISA_trigger(idx);
1027 case MP_BUS_EISA: /* EISA pin */
1029 trigger = default_EISA_trigger(idx);
1032 case MP_BUS_PCI: /* PCI pin */
1034 trigger = default_PCI_trigger(idx);
1037 case MP_BUS_MCA: /* MCA pin */
1039 trigger = default_MCA_trigger(idx);
1042 case MP_BUS_NEC98: /* NEC 98 pin */
1044 trigger = default_NEC98_trigger(idx);
1049 printk(KERN_WARNING "broken BIOS!!\n");
1061 case 2: /* reserved */
1063 printk(KERN_WARNING "broken BIOS!!\n");
1072 default: /* invalid */
1074 printk(KERN_WARNING "broken BIOS!!\n");
1082 static inline int irq_polarity(int idx)
1084 return MPBIOS_polarity(idx);
1087 static inline int irq_trigger(int idx)
1089 return MPBIOS_trigger(idx);
1092 static int pin_2_irq(int idx, int apic, int pin)
1095 int bus = mp_irqs[idx].mpc_srcbus;
1098 * Debugging check, we are in big trouble if this message pops up!
1100 if (mp_irqs[idx].mpc_dstirq != pin)
1101 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1103 switch (mp_bus_id_to_type[bus])
1105 case MP_BUS_ISA: /* ISA pin */
1110 irq = mp_irqs[idx].mpc_srcbusirq;
1113 case MP_BUS_PCI: /* PCI pin */
1116 * PCI IRQs are mapped in order
1120 irq += nr_ioapic_registers[i++];
1124 * For MPS mode, so far only needed by ES7000 platform
1126 if (ioapic_renumber_irq)
1127 irq = ioapic_renumber_irq(apic, irq);
1133 printk(KERN_ERR "unknown bus type %d.\n",bus);
1140 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1142 if ((pin >= 16) && (pin <= 23)) {
1143 if (pirq_entries[pin-16] != -1) {
1144 if (!pirq_entries[pin-16]) {
1145 apic_printk(APIC_VERBOSE, KERN_DEBUG
1146 "disabling PIRQ%d\n", pin-16);
1148 irq = pirq_entries[pin-16];
1149 apic_printk(APIC_VERBOSE, KERN_DEBUG
1150 "using PIRQ%d -> IRQ %d\n",
1158 static inline int IO_APIC_irq_trigger(int irq)
1162 for (apic = 0; apic < nr_ioapics; apic++) {
1163 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1164 idx = find_irq_entry(apic,pin,mp_INT);
1165 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1166 return irq_trigger(idx);
1170 * nonexistent IRQs are edge default
1175 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1176 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1178 static int __assign_irq_vector(int irq)
1180 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1183 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1185 if (IO_APIC_VECTOR(irq) > 0)
1186 return IO_APIC_VECTOR(irq);
1188 current_vector += 8;
1189 if (current_vector == SYSCALL_VECTOR)
1190 current_vector += 8;
1192 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1196 current_vector = FIRST_DEVICE_VECTOR + offset;
1199 vector = current_vector;
1200 IO_APIC_VECTOR(irq) = vector;
1205 static int assign_irq_vector(int irq)
1207 unsigned long flags;
1210 spin_lock_irqsave(&vector_lock, flags);
1211 vector = __assign_irq_vector(irq);
1212 spin_unlock_irqrestore(&vector_lock, flags);
1216 static struct irq_chip ioapic_chip;
1218 #define IOAPIC_AUTO -1
1219 #define IOAPIC_EDGE 0
1220 #define IOAPIC_LEVEL 1
1222 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1224 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1225 trigger == IOAPIC_LEVEL)
1226 set_irq_chip_and_handler(irq, &ioapic_chip,
1227 handle_fasteoi_irq);
1229 set_irq_chip_and_handler(irq, &ioapic_chip,
1231 set_intr_gate(vector, interrupt[irq]);
1234 static void __init setup_IO_APIC_irqs(void)
1236 struct IO_APIC_route_entry entry;
1237 int apic, pin, idx, irq, first_notcon = 1, vector;
1238 unsigned long flags;
1240 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1242 for (apic = 0; apic < nr_ioapics; apic++) {
1243 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1246 * add it to the IO-APIC irq-routing table:
1248 memset(&entry,0,sizeof(entry));
1250 entry.delivery_mode = INT_DELIVERY_MODE;
1251 entry.dest_mode = INT_DEST_MODE;
1252 entry.mask = 0; /* enable IRQ */
1253 entry.dest.logical.logical_dest =
1254 cpu_mask_to_apicid(TARGET_CPUS);
1256 idx = find_irq_entry(apic,pin,mp_INT);
1259 apic_printk(APIC_VERBOSE, KERN_DEBUG
1260 " IO-APIC (apicid-pin) %d-%d",
1261 mp_ioapics[apic].mpc_apicid,
1265 apic_printk(APIC_VERBOSE, ", %d-%d",
1266 mp_ioapics[apic].mpc_apicid, pin);
1270 entry.trigger = irq_trigger(idx);
1271 entry.polarity = irq_polarity(idx);
1273 if (irq_trigger(idx)) {
1278 irq = pin_2_irq(idx, apic, pin);
1280 * skip adding the timer int on secondary nodes, which causes
1281 * a small but painful rift in the time-space continuum
1283 if (multi_timer_check(apic, irq))
1286 add_pin_to_irq(irq, apic, pin);
1288 if (!apic && !IO_APIC_IRQ(irq))
1291 if (IO_APIC_IRQ(irq)) {
1292 vector = assign_irq_vector(irq);
1293 entry.vector = vector;
1294 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1296 if (!apic && (irq < 16))
1297 disable_8259A_irq(irq);
1299 ioapic_write_entry(apic, pin, entry);
1300 spin_lock_irqsave(&ioapic_lock, flags);
1301 set_native_irq_info(irq, TARGET_CPUS);
1302 spin_unlock_irqrestore(&ioapic_lock, flags);
1307 apic_printk(APIC_VERBOSE, " not connected.\n");
1311 * Set up the 8259A-master output pin:
1313 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1315 struct IO_APIC_route_entry entry;
1317 memset(&entry,0,sizeof(entry));
1319 disable_8259A_irq(0);
1322 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1325 * We use logical delivery to get the timer IRQ
1328 entry.dest_mode = INT_DEST_MODE;
1329 entry.mask = 0; /* unmask IRQ now */
1330 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1331 entry.delivery_mode = INT_DELIVERY_MODE;
1334 entry.vector = vector;
1337 * The timer IRQ doesn't have to know that behind the
1338 * scene we have a 8259A-master in AEOI mode ...
1340 irq_desc[0].chip = &ioapic_chip;
1341 set_irq_handler(0, handle_edge_irq);
1344 * Add it to the IO-APIC irq-routing table:
1346 ioapic_write_entry(apic, pin, entry);
1348 enable_8259A_irq(0);
1351 static inline void UNEXPECTED_IO_APIC(void)
1355 void __init print_IO_APIC(void)
1358 union IO_APIC_reg_00 reg_00;
1359 union IO_APIC_reg_01 reg_01;
1360 union IO_APIC_reg_02 reg_02;
1361 union IO_APIC_reg_03 reg_03;
1362 unsigned long flags;
1364 if (apic_verbosity == APIC_QUIET)
1367 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1368 for (i = 0; i < nr_ioapics; i++)
1369 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1370 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1373 * We are a bit conservative about what we expect. We have to
1374 * know about every hardware change ASAP.
1376 printk(KERN_INFO "testing the IO APIC.......................\n");
1378 for (apic = 0; apic < nr_ioapics; apic++) {
1380 spin_lock_irqsave(&ioapic_lock, flags);
1381 reg_00.raw = io_apic_read(apic, 0);
1382 reg_01.raw = io_apic_read(apic, 1);
1383 if (reg_01.bits.version >= 0x10)
1384 reg_02.raw = io_apic_read(apic, 2);
1385 if (reg_01.bits.version >= 0x20)
1386 reg_03.raw = io_apic_read(apic, 3);
1387 spin_unlock_irqrestore(&ioapic_lock, flags);
1389 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1390 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1391 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1392 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1393 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1394 if (reg_00.bits.ID >= get_physical_broadcast())
1395 UNEXPECTED_IO_APIC();
1396 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1397 UNEXPECTED_IO_APIC();
1399 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1400 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1401 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1402 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1403 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1404 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1405 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1406 (reg_01.bits.entries != 0x2E) &&
1407 (reg_01.bits.entries != 0x3F)
1409 UNEXPECTED_IO_APIC();
1411 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1412 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1413 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1414 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1415 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1416 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1417 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1419 UNEXPECTED_IO_APIC();
1420 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1421 UNEXPECTED_IO_APIC();
1424 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1425 * but the value of reg_02 is read as the previous read register
1426 * value, so ignore it if reg_02 == reg_01.
1428 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1429 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1430 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1431 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1432 UNEXPECTED_IO_APIC();
1436 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1437 * or reg_03, but the value of reg_0[23] is read as the previous read
1438 * register value, so ignore it if reg_03 == reg_0[12].
1440 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1441 reg_03.raw != reg_01.raw) {
1442 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1443 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1444 if (reg_03.bits.__reserved_1)
1445 UNEXPECTED_IO_APIC();
1448 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1450 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1451 " Stat Dest Deli Vect: \n");
1453 for (i = 0; i <= reg_01.bits.entries; i++) {
1454 struct IO_APIC_route_entry entry;
1456 entry = ioapic_read_entry(apic, i);
1458 printk(KERN_DEBUG " %02x %03X %02X ",
1460 entry.dest.logical.logical_dest,
1461 entry.dest.physical.physical_dest
1464 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1469 entry.delivery_status,
1471 entry.delivery_mode,
1476 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1477 for (i = 0; i < NR_IRQS; i++) {
1478 struct irq_pin_list *entry = irq_2_pin + i;
1481 printk(KERN_DEBUG "IRQ%d ", i);
1483 printk("-> %d:%d", entry->apic, entry->pin);
1486 entry = irq_2_pin + entry->next;
1491 printk(KERN_INFO ".................................... done.\n");
1498 static void print_APIC_bitfield (int base)
1503 if (apic_verbosity == APIC_QUIET)
1506 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1507 for (i = 0; i < 8; i++) {
1508 v = apic_read(base + i*0x10);
1509 for (j = 0; j < 32; j++) {
1519 void /*__init*/ print_local_APIC(void * dummy)
1521 unsigned int v, ver, maxlvt;
1523 if (apic_verbosity == APIC_QUIET)
1526 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1527 smp_processor_id(), hard_smp_processor_id());
1528 v = apic_read(APIC_ID);
1529 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1530 v = apic_read(APIC_LVR);
1531 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1532 ver = GET_APIC_VERSION(v);
1533 maxlvt = get_maxlvt();
1535 v = apic_read(APIC_TASKPRI);
1536 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1538 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1539 v = apic_read(APIC_ARBPRI);
1540 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1541 v & APIC_ARBPRI_MASK);
1542 v = apic_read(APIC_PROCPRI);
1543 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1546 v = apic_read(APIC_EOI);
1547 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1548 v = apic_read(APIC_RRR);
1549 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1550 v = apic_read(APIC_LDR);
1551 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1552 v = apic_read(APIC_DFR);
1553 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1554 v = apic_read(APIC_SPIV);
1555 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1557 printk(KERN_DEBUG "... APIC ISR field:\n");
1558 print_APIC_bitfield(APIC_ISR);
1559 printk(KERN_DEBUG "... APIC TMR field:\n");
1560 print_APIC_bitfield(APIC_TMR);
1561 printk(KERN_DEBUG "... APIC IRR field:\n");
1562 print_APIC_bitfield(APIC_IRR);
1564 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1565 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1566 apic_write(APIC_ESR, 0);
1567 v = apic_read(APIC_ESR);
1568 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1571 v = apic_read(APIC_ICR);
1572 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1573 v = apic_read(APIC_ICR2);
1574 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1576 v = apic_read(APIC_LVTT);
1577 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1579 if (maxlvt > 3) { /* PC is LVT#4. */
1580 v = apic_read(APIC_LVTPC);
1581 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1583 v = apic_read(APIC_LVT0);
1584 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1585 v = apic_read(APIC_LVT1);
1586 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1588 if (maxlvt > 2) { /* ERR is LVT#3. */
1589 v = apic_read(APIC_LVTERR);
1590 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1593 v = apic_read(APIC_TMICT);
1594 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1595 v = apic_read(APIC_TMCCT);
1596 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1597 v = apic_read(APIC_TDCR);
1598 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1602 void print_all_local_APICs (void)
1604 on_each_cpu(print_local_APIC, NULL, 1, 1);
1607 void /*__init*/ print_PIC(void)
1610 unsigned long flags;
1612 if (apic_verbosity == APIC_QUIET)
1615 printk(KERN_DEBUG "\nprinting PIC contents\n");
1617 spin_lock_irqsave(&i8259A_lock, flags);
1619 v = inb(0xa1) << 8 | inb(0x21);
1620 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1622 v = inb(0xa0) << 8 | inb(0x20);
1623 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1627 v = inb(0xa0) << 8 | inb(0x20);
1631 spin_unlock_irqrestore(&i8259A_lock, flags);
1633 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1635 v = inb(0x4d1) << 8 | inb(0x4d0);
1636 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1641 static void __init enable_IO_APIC(void)
1643 union IO_APIC_reg_01 reg_01;
1644 int i8259_apic, i8259_pin;
1646 unsigned long flags;
1648 for (i = 0; i < PIN_MAP_SIZE; i++) {
1649 irq_2_pin[i].pin = -1;
1650 irq_2_pin[i].next = 0;
1653 for (i = 0; i < MAX_PIRQS; i++)
1654 pirq_entries[i] = -1;
1657 * The number of IO-APIC IRQ registers (== #pins):
1659 for (apic = 0; apic < nr_ioapics; apic++) {
1660 spin_lock_irqsave(&ioapic_lock, flags);
1661 reg_01.raw = io_apic_read(apic, 1);
1662 spin_unlock_irqrestore(&ioapic_lock, flags);
1663 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1665 for(apic = 0; apic < nr_ioapics; apic++) {
1667 /* See if any of the pins is in ExtINT mode */
1668 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1669 struct IO_APIC_route_entry entry;
1670 entry = ioapic_read_entry(apic, pin);
1673 /* If the interrupt line is enabled and in ExtInt mode
1674 * I have found the pin where the i8259 is connected.
1676 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1677 ioapic_i8259.apic = apic;
1678 ioapic_i8259.pin = pin;
1684 /* Look to see what if the MP table has reported the ExtINT */
1685 /* If we could not find the appropriate pin by looking at the ioapic
1686 * the i8259 probably is not connected the ioapic but give the
1687 * mptable a chance anyway.
1689 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1690 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1691 /* Trust the MP table if nothing is setup in the hardware */
1692 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1693 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1694 ioapic_i8259.pin = i8259_pin;
1695 ioapic_i8259.apic = i8259_apic;
1697 /* Complain if the MP table and the hardware disagree */
1698 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1699 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1701 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1705 * Do not trust the IO-APIC being empty at bootup
1711 * Not an __init, needed by the reboot code
1713 void disable_IO_APIC(void)
1716 * Clear the IO-APIC before rebooting:
1721 * If the i8259 is routed through an IOAPIC
1722 * Put that IOAPIC in virtual wire mode
1723 * so legacy interrupts can be delivered.
1725 if (ioapic_i8259.pin != -1) {
1726 struct IO_APIC_route_entry entry;
1728 memset(&entry, 0, sizeof(entry));
1729 entry.mask = 0; /* Enabled */
1730 entry.trigger = 0; /* Edge */
1732 entry.polarity = 0; /* High */
1733 entry.delivery_status = 0;
1734 entry.dest_mode = 0; /* Physical */
1735 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1737 entry.dest.physical.physical_dest =
1738 GET_APIC_ID(apic_read(APIC_ID));
1741 * Add it to the IO-APIC irq-routing table:
1743 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1745 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1749 * function to set the IO-APIC physical IDs based on the
1750 * values stored in the MPC table.
1752 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1755 #ifndef CONFIG_X86_NUMAQ
1756 static void __init setup_ioapic_ids_from_mpc(void)
1758 union IO_APIC_reg_00 reg_00;
1759 physid_mask_t phys_id_present_map;
1762 unsigned char old_id;
1763 unsigned long flags;
1766 * Don't check I/O APIC IDs for xAPIC systems. They have
1767 * no meaning without the serial APIC bus.
1769 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1770 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1773 * This is broken; anything with a real cpu count has to
1774 * circumvent this idiocy regardless.
1776 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1779 * Set the IOAPIC ID to the value stored in the MPC table.
1781 for (apic = 0; apic < nr_ioapics; apic++) {
1783 /* Read the register 0 value */
1784 spin_lock_irqsave(&ioapic_lock, flags);
1785 reg_00.raw = io_apic_read(apic, 0);
1786 spin_unlock_irqrestore(&ioapic_lock, flags);
1788 old_id = mp_ioapics[apic].mpc_apicid;
1790 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1791 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1792 apic, mp_ioapics[apic].mpc_apicid);
1793 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1795 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1799 * Sanity check, is the ID really free? Every APIC in a
1800 * system must have a unique ID or we get lots of nice
1801 * 'stuck on smp_invalidate_needed IPI wait' messages.
1803 if (check_apicid_used(phys_id_present_map,
1804 mp_ioapics[apic].mpc_apicid)) {
1805 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1806 apic, mp_ioapics[apic].mpc_apicid);
1807 for (i = 0; i < get_physical_broadcast(); i++)
1808 if (!physid_isset(i, phys_id_present_map))
1810 if (i >= get_physical_broadcast())
1811 panic("Max APIC ID exceeded!\n");
1812 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1814 physid_set(i, phys_id_present_map);
1815 mp_ioapics[apic].mpc_apicid = i;
1818 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1819 apic_printk(APIC_VERBOSE, "Setting %d in the "
1820 "phys_id_present_map\n",
1821 mp_ioapics[apic].mpc_apicid);
1822 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1827 * We need to adjust the IRQ routing table
1828 * if the ID changed.
1830 if (old_id != mp_ioapics[apic].mpc_apicid)
1831 for (i = 0; i < mp_irq_entries; i++)
1832 if (mp_irqs[i].mpc_dstapic == old_id)
1833 mp_irqs[i].mpc_dstapic
1834 = mp_ioapics[apic].mpc_apicid;
1837 * Read the right value from the MPC table and
1838 * write it into the ID register.
1840 apic_printk(APIC_VERBOSE, KERN_INFO
1841 "...changing IO-APIC physical APIC ID to %d ...",
1842 mp_ioapics[apic].mpc_apicid);
1844 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1845 spin_lock_irqsave(&ioapic_lock, flags);
1846 io_apic_write(apic, 0, reg_00.raw);
1847 spin_unlock_irqrestore(&ioapic_lock, flags);
1852 spin_lock_irqsave(&ioapic_lock, flags);
1853 reg_00.raw = io_apic_read(apic, 0);
1854 spin_unlock_irqrestore(&ioapic_lock, flags);
1855 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1856 printk("could not set ID!\n");
1858 apic_printk(APIC_VERBOSE, " ok.\n");
1862 static void __init setup_ioapic_ids_from_mpc(void) { }
1866 * There is a nasty bug in some older SMP boards, their mptable lies
1867 * about the timer IRQ. We do the following to work around the situation:
1869 * - timer IRQ defaults to IO-APIC IRQ
1870 * - if this function detects that timer IRQs are defunct, then we fall
1871 * back to ISA timer IRQs
1873 static int __init timer_irq_works(void)
1875 unsigned long t1 = jiffies;
1878 /* Let ten ticks pass... */
1879 mdelay((10 * 1000) / HZ);
1882 * Expect a few ticks at least, to be sure some possible
1883 * glue logic does not lock up after one or two first
1884 * ticks in a non-ExtINT mode. Also the local APIC
1885 * might have cached one ExtINT interrupt. Finally, at
1886 * least one tick may be lost due to delays.
1888 if (jiffies - t1 > 4)
1895 * In the SMP+IOAPIC case it might happen that there are an unspecified
1896 * number of pending IRQ events unhandled. These cases are very rare,
1897 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1898 * better to do it this way as thus we do not have to be aware of
1899 * 'pending' interrupts in the IRQ path, except at this point.
1902 * Edge triggered needs to resend any interrupt
1903 * that was delayed but this is now handled in the device
1910 * Starting up a edge-triggered IO-APIC interrupt is
1911 * nasty - we need to make sure that we get the edge.
1912 * If it is already asserted for some reason, we need
1913 * return 1 to indicate that is was pending.
1915 * This is not complete - we should be able to fake
1916 * an edge even if it isn't on the 8259A...
1918 * (We do this for level-triggered IRQs too - it cannot hurt.)
1920 static unsigned int startup_ioapic_irq(unsigned int irq)
1922 int was_pending = 0;
1923 unsigned long flags;
1925 spin_lock_irqsave(&ioapic_lock, flags);
1927 disable_8259A_irq(irq);
1928 if (i8259A_irq_pending(irq))
1931 __unmask_IO_APIC_irq(irq);
1932 spin_unlock_irqrestore(&ioapic_lock, flags);
1937 static void ack_ioapic_irq(unsigned int irq)
1939 move_native_irq(irq);
1943 static void ack_ioapic_quirk_irq(unsigned int irq)
1948 move_native_irq(irq);
1950 * It appears there is an erratum which affects at least version 0x11
1951 * of I/O APIC (that's the 82093AA and cores integrated into various
1952 * chipsets). Under certain conditions a level-triggered interrupt is
1953 * erroneously delivered as edge-triggered one but the respective IRR
1954 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1955 * message but it will never arrive and further interrupts are blocked
1956 * from the source. The exact reason is so far unknown, but the
1957 * phenomenon was observed when two consecutive interrupt requests
1958 * from a given source get delivered to the same CPU and the source is
1959 * temporarily disabled in between.
1961 * A workaround is to simulate an EOI message manually. We achieve it
1962 * by setting the trigger mode to edge and then to level when the edge
1963 * trigger mode gets detected in the TMR of a local APIC for a
1964 * level-triggered interrupt. We mask the source for the time of the
1965 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1966 * The idea is from Manfred Spraul. --macro
1968 i = IO_APIC_VECTOR(irq);
1970 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1974 if (!(v & (1 << (i & 0x1f)))) {
1975 atomic_inc(&irq_mis_count);
1976 spin_lock(&ioapic_lock);
1977 __mask_and_edge_IO_APIC_irq(irq);
1978 __unmask_and_level_IO_APIC_irq(irq);
1979 spin_unlock(&ioapic_lock);
1983 static int ioapic_retrigger_irq(unsigned int irq)
1985 send_IPI_self(IO_APIC_VECTOR(irq));
1990 static struct irq_chip ioapic_chip __read_mostly = {
1992 .startup = startup_ioapic_irq,
1993 .mask = mask_IO_APIC_irq,
1994 .unmask = unmask_IO_APIC_irq,
1995 .ack = ack_ioapic_irq,
1996 .eoi = ack_ioapic_quirk_irq,
1998 .set_affinity = set_ioapic_affinity_irq,
2000 .retrigger = ioapic_retrigger_irq,
2004 static inline void init_IO_APIC_traps(void)
2009 * NOTE! The local APIC isn't very good at handling
2010 * multiple interrupts at the same interrupt level.
2011 * As the interrupt level is determined by taking the
2012 * vector number and shifting that right by 4, we
2013 * want to spread these out a bit so that they don't
2014 * all fall in the same interrupt level.
2016 * Also, we've got to be careful not to trash gate
2017 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2019 for (irq = 0; irq < NR_IRQS ; irq++) {
2021 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2023 * Hmm.. We don't have an entry for this,
2024 * so default to an old-fashioned 8259
2025 * interrupt if we can..
2028 make_8259A_irq(irq);
2030 /* Strange. Oh, well.. */
2031 irq_desc[irq].chip = &no_irq_chip;
2037 * The local APIC irq-chip implementation:
2040 static void ack_apic(unsigned int irq)
2045 static void mask_lapic_irq (unsigned int irq)
2049 v = apic_read(APIC_LVT0);
2050 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2053 static void unmask_lapic_irq (unsigned int irq)
2057 v = apic_read(APIC_LVT0);
2058 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2061 static struct irq_chip lapic_chip __read_mostly = {
2062 .name = "local-APIC-edge",
2063 .mask = mask_lapic_irq,
2064 .unmask = unmask_lapic_irq,
2068 static void setup_nmi (void)
2071 * Dirty trick to enable the NMI watchdog ...
2072 * We put the 8259A master into AEOI mode and
2073 * unmask on all local APICs LVT0 as NMI.
2075 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2076 * is from Maciej W. Rozycki - so we do not have to EOI from
2077 * the NMI handler or the timer interrupt.
2079 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2081 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2083 apic_printk(APIC_VERBOSE, " done.\n");
2087 * This looks a bit hackish but it's about the only one way of sending
2088 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2089 * not support the ExtINT mode, unfortunately. We need to send these
2090 * cycles as some i82489DX-based boards have glue logic that keeps the
2091 * 8259A interrupt line asserted until INTA. --macro
2093 static inline void unlock_ExtINT_logic(void)
2096 struct IO_APIC_route_entry entry0, entry1;
2097 unsigned char save_control, save_freq_select;
2099 pin = find_isa_irq_pin(8, mp_INT);
2100 apic = find_isa_irq_apic(8, mp_INT);
2104 entry0 = ioapic_read_entry(apic, pin);
2105 clear_IO_APIC_pin(apic, pin);
2107 memset(&entry1, 0, sizeof(entry1));
2109 entry1.dest_mode = 0; /* physical delivery */
2110 entry1.mask = 0; /* unmask IRQ now */
2111 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2112 entry1.delivery_mode = dest_ExtINT;
2113 entry1.polarity = entry0.polarity;
2117 ioapic_write_entry(apic, pin, entry1);
2119 save_control = CMOS_READ(RTC_CONTROL);
2120 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2121 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2123 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2128 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2132 CMOS_WRITE(save_control, RTC_CONTROL);
2133 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2134 clear_IO_APIC_pin(apic, pin);
2136 ioapic_write_entry(apic, pin, entry0);
2139 int timer_uses_ioapic_pin_0;
2142 * This code may look a bit paranoid, but it's supposed to cooperate with
2143 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2144 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2145 * fanatically on his truly buggy board.
2147 static inline void check_timer(void)
2149 int apic1, pin1, apic2, pin2;
2153 * get/set the timer IRQ vector:
2155 disable_8259A_irq(0);
2156 vector = assign_irq_vector(0);
2157 set_intr_gate(vector, interrupt[0]);
2160 * Subtle, code in do_timer_interrupt() expects an AEOI
2161 * mode for the 8259A whenever interrupts are routed
2162 * through I/O APICs. Also IRQ0 has to be enabled in
2163 * the 8259A which implies the virtual wire has to be
2164 * disabled in the local APIC.
2166 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2169 if (timer_over_8254 > 0)
2170 enable_8259A_irq(0);
2172 pin1 = find_isa_irq_pin(0, mp_INT);
2173 apic1 = find_isa_irq_apic(0, mp_INT);
2174 pin2 = ioapic_i8259.pin;
2175 apic2 = ioapic_i8259.apic;
2178 timer_uses_ioapic_pin_0 = 1;
2180 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2181 vector, apic1, pin1, apic2, pin2);
2185 * Ok, does IRQ0 through the IOAPIC work?
2187 unmask_IO_APIC_irq(0);
2188 if (timer_irq_works()) {
2189 if (nmi_watchdog == NMI_IO_APIC) {
2190 disable_8259A_irq(0);
2192 enable_8259A_irq(0);
2194 if (disable_timer_pin_1 > 0)
2195 clear_IO_APIC_pin(0, pin1);
2198 clear_IO_APIC_pin(apic1, pin1);
2199 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2203 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2205 printk("\n..... (found pin %d) ...", pin2);
2207 * legacy devices should be connected to IO APIC #0
2209 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2210 if (timer_irq_works()) {
2213 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2215 add_pin_to_irq(0, apic2, pin2);
2216 if (nmi_watchdog == NMI_IO_APIC) {
2222 * Cleanup, just in case ...
2224 clear_IO_APIC_pin(apic2, pin2);
2226 printk(" failed.\n");
2228 if (nmi_watchdog == NMI_IO_APIC) {
2229 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2233 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2235 disable_8259A_irq(0);
2236 set_irq_chip_and_handler(0, &lapic_chip, handle_fasteoi_irq);
2237 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2238 enable_8259A_irq(0);
2240 if (timer_irq_works()) {
2241 printk(" works.\n");
2244 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2245 printk(" failed.\n");
2247 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2252 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2254 unlock_ExtINT_logic();
2256 if (timer_irq_works()) {
2257 printk(" works.\n");
2260 printk(" failed :(.\n");
2261 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2262 "report. Then try booting with the 'noapic' option");
2267 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2268 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2269 * Linux doesn't really care, as it's not actually used
2270 * for any interrupt handling anyway.
2272 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2274 void __init setup_IO_APIC(void)
2279 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2281 io_apic_irqs = ~PIC_IRQS;
2283 printk("ENABLING IO-APIC IRQs\n");
2286 * Set up IO-APIC IRQ routing.
2289 setup_ioapic_ids_from_mpc();
2291 setup_IO_APIC_irqs();
2292 init_IO_APIC_traps();
2298 static int __init setup_disable_8254_timer(char *s)
2300 timer_over_8254 = -1;
2303 static int __init setup_enable_8254_timer(char *s)
2305 timer_over_8254 = 2;
2309 __setup("disable_8254_timer", setup_disable_8254_timer);
2310 __setup("enable_8254_timer", setup_enable_8254_timer);
2313 * Called after all the initialization is done. If we didnt find any
2314 * APIC bugs then we can allow the modify fast path
2317 static int __init io_apic_bug_finalize(void)
2319 if(sis_apic_bug == -1)
2324 late_initcall(io_apic_bug_finalize);
2326 struct sysfs_ioapic_data {
2327 struct sys_device dev;
2328 struct IO_APIC_route_entry entry[0];
2330 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2332 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2334 struct IO_APIC_route_entry *entry;
2335 struct sysfs_ioapic_data *data;
2338 data = container_of(dev, struct sysfs_ioapic_data, dev);
2339 entry = data->entry;
2340 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2341 entry[i] = ioapic_read_entry(dev->id, i);
2346 static int ioapic_resume(struct sys_device *dev)
2348 struct IO_APIC_route_entry *entry;
2349 struct sysfs_ioapic_data *data;
2350 unsigned long flags;
2351 union IO_APIC_reg_00 reg_00;
2354 data = container_of(dev, struct sysfs_ioapic_data, dev);
2355 entry = data->entry;
2357 spin_lock_irqsave(&ioapic_lock, flags);
2358 reg_00.raw = io_apic_read(dev->id, 0);
2359 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2360 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2361 io_apic_write(dev->id, 0, reg_00.raw);
2363 spin_unlock_irqrestore(&ioapic_lock, flags);
2364 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2365 ioapic_write_entry(dev->id, i, entry[i]);
2370 static struct sysdev_class ioapic_sysdev_class = {
2371 set_kset_name("ioapic"),
2372 .suspend = ioapic_suspend,
2373 .resume = ioapic_resume,
2376 static int __init ioapic_init_sysfs(void)
2378 struct sys_device * dev;
2379 int i, size, error = 0;
2381 error = sysdev_class_register(&ioapic_sysdev_class);
2385 for (i = 0; i < nr_ioapics; i++ ) {
2386 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2387 * sizeof(struct IO_APIC_route_entry);
2388 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2389 if (!mp_ioapic_data[i]) {
2390 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2393 memset(mp_ioapic_data[i], 0, size);
2394 dev = &mp_ioapic_data[i]->dev;
2396 dev->cls = &ioapic_sysdev_class;
2397 error = sysdev_register(dev);
2399 kfree(mp_ioapic_data[i]);
2400 mp_ioapic_data[i] = NULL;
2401 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2409 device_initcall(ioapic_init_sysfs);
2411 #ifdef CONFIG_PCI_MSI
2413 * Dynamic irq allocate and deallocation for MSI
2415 int create_irq(void)
2417 /* Allocate an unused irq */
2418 int irq, new, vector;
2419 unsigned long flags;
2422 spin_lock_irqsave(&vector_lock, flags);
2423 for (new = (NR_IRQS - 1); new >= 0; new--) {
2424 if (platform_legacy_irq(new))
2426 if (irq_vector[new] != 0)
2428 vector = __assign_irq_vector(new);
2429 if (likely(vector > 0))
2433 spin_unlock_irqrestore(&vector_lock, flags);
2436 set_intr_gate(vector, interrupt[irq]);
2437 dynamic_irq_init(irq);
2442 void destroy_irq(unsigned int irq)
2444 unsigned long flags;
2446 dynamic_irq_cleanup(irq);
2448 spin_lock_irqsave(&vector_lock, flags);
2449 irq_vector[irq] = 0;
2450 spin_unlock_irqrestore(&vector_lock, flags);
2452 #endif /* CONFIG_PCI_MSI */
2455 * MSI mesage composition
2457 #ifdef CONFIG_PCI_MSI
2458 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2460 /* For now always this code always uses physical delivery
2466 vector = assign_irq_vector(irq);
2468 dest = cpu_mask_to_apicid(TARGET_CPUS);
2470 msg->address_hi = MSI_ADDR_BASE_HI;
2473 ((INT_DEST_MODE == 0) ?
2474 MSI_ADDR_DEST_MODE_PHYSICAL:
2475 MSI_ADDR_DEST_MODE_LOGICAL) |
2476 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2477 MSI_ADDR_REDIRECTION_CPU:
2478 MSI_ADDR_REDIRECTION_LOWPRI) |
2479 MSI_ADDR_DEST_ID(dest);
2482 MSI_DATA_TRIGGER_EDGE |
2483 MSI_DATA_LEVEL_ASSERT |
2484 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2485 MSI_DATA_DELIVERY_FIXED:
2486 MSI_DATA_DELIVERY_LOWPRI) |
2487 MSI_DATA_VECTOR(vector);
2492 static void msi_msg_teardown(unsigned int irq)
2497 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
2502 vector = assign_irq_vector(irq);
2504 dest = cpu_mask_to_apicid(mask);
2506 msg->data &= ~MSI_DATA_VECTOR_MASK;
2507 msg->data |= MSI_DATA_VECTOR(vector);
2508 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2509 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
2513 struct msi_ops arch_msi_ops = {
2514 .needs_64bit_address = 0,
2515 .setup = msi_msg_setup,
2516 .teardown = msi_msg_teardown,
2517 .target = msi_msg_set_affinity,
2520 #endif /* CONFIG_PCI_MSI */
2523 * Hypertransport interrupt support
2525 #ifdef CONFIG_HT_IRQ
2529 static void target_ht_irq(unsigned int irq, unsigned int dest)
2532 low = read_ht_irq_low(irq);
2533 high = read_ht_irq_high(irq);
2535 low &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2536 high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2538 low |= HT_IRQ_LOW_DEST_ID(dest);
2539 high |= HT_IRQ_HIGH_DEST_ID(dest);
2541 write_ht_irq_low(irq, low);
2542 write_ht_irq_high(irq, high);
2545 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2550 cpus_and(tmp, mask, cpu_online_map);
2551 if (cpus_empty(tmp))
2554 cpus_and(mask, tmp, CPU_MASK_ALL);
2556 dest = cpu_mask_to_apicid(mask);
2558 target_ht_irq(irq, dest);
2559 set_native_irq_info(irq, mask);
2563 static struct hw_interrupt_type ht_irq_chip = {
2565 .mask = mask_ht_irq,
2566 .unmask = unmask_ht_irq,
2567 .ack = ack_ioapic_irq,
2569 .set_affinity = set_ht_irq_affinity,
2571 .retrigger = ioapic_retrigger_irq,
2574 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2578 vector = assign_irq_vector(irq);
2585 cpu_set(vector >> 8, tmp);
2586 dest = cpu_mask_to_apicid(tmp);
2588 high = HT_IRQ_HIGH_DEST_ID(dest);
2590 low = HT_IRQ_LOW_BASE |
2591 HT_IRQ_LOW_DEST_ID(dest) |
2592 HT_IRQ_LOW_VECTOR(vector) |
2593 ((INT_DEST_MODE == 0) ?
2594 HT_IRQ_LOW_DM_PHYSICAL :
2595 HT_IRQ_LOW_DM_LOGICAL) |
2596 HT_IRQ_LOW_RQEOI_EDGE |
2597 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2598 HT_IRQ_LOW_MT_FIXED :
2599 HT_IRQ_LOW_MT_ARBITRATED) |
2600 HT_IRQ_LOW_IRQ_MASKED;
2602 write_ht_irq_low(irq, low);
2603 write_ht_irq_high(irq, high);
2605 set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq);
2609 #endif /* CONFIG_HT_IRQ */
2611 /* --------------------------------------------------------------------------
2612 ACPI-based IOAPIC Configuration
2613 -------------------------------------------------------------------------- */
2617 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2619 union IO_APIC_reg_00 reg_00;
2620 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2622 unsigned long flags;
2626 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2627 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2628 * supports up to 16 on one shared APIC bus.
2630 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2631 * advantage of new APIC bus architecture.
2634 if (physids_empty(apic_id_map))
2635 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2637 spin_lock_irqsave(&ioapic_lock, flags);
2638 reg_00.raw = io_apic_read(ioapic, 0);
2639 spin_unlock_irqrestore(&ioapic_lock, flags);
2641 if (apic_id >= get_physical_broadcast()) {
2642 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2643 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2644 apic_id = reg_00.bits.ID;
2648 * Every APIC in a system must have a unique ID or we get lots of nice
2649 * 'stuck on smp_invalidate_needed IPI wait' messages.
2651 if (check_apicid_used(apic_id_map, apic_id)) {
2653 for (i = 0; i < get_physical_broadcast(); i++) {
2654 if (!check_apicid_used(apic_id_map, i))
2658 if (i == get_physical_broadcast())
2659 panic("Max apic_id exceeded!\n");
2661 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2662 "trying %d\n", ioapic, apic_id, i);
2667 tmp = apicid_to_cpu_present(apic_id);
2668 physids_or(apic_id_map, apic_id_map, tmp);
2670 if (reg_00.bits.ID != apic_id) {
2671 reg_00.bits.ID = apic_id;
2673 spin_lock_irqsave(&ioapic_lock, flags);
2674 io_apic_write(ioapic, 0, reg_00.raw);
2675 reg_00.raw = io_apic_read(ioapic, 0);
2676 spin_unlock_irqrestore(&ioapic_lock, flags);
2679 if (reg_00.bits.ID != apic_id) {
2680 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2685 apic_printk(APIC_VERBOSE, KERN_INFO
2686 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2692 int __init io_apic_get_version (int ioapic)
2694 union IO_APIC_reg_01 reg_01;
2695 unsigned long flags;
2697 spin_lock_irqsave(&ioapic_lock, flags);
2698 reg_01.raw = io_apic_read(ioapic, 1);
2699 spin_unlock_irqrestore(&ioapic_lock, flags);
2701 return reg_01.bits.version;
2705 int __init io_apic_get_redir_entries (int ioapic)
2707 union IO_APIC_reg_01 reg_01;
2708 unsigned long flags;
2710 spin_lock_irqsave(&ioapic_lock, flags);
2711 reg_01.raw = io_apic_read(ioapic, 1);
2712 spin_unlock_irqrestore(&ioapic_lock, flags);
2714 return reg_01.bits.entries;
2718 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2720 struct IO_APIC_route_entry entry;
2721 unsigned long flags;
2723 if (!IO_APIC_IRQ(irq)) {
2724 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2730 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2731 * Note that we mask (disable) IRQs now -- these get enabled when the
2732 * corresponding device driver registers for this IRQ.
2735 memset(&entry,0,sizeof(entry));
2737 entry.delivery_mode = INT_DELIVERY_MODE;
2738 entry.dest_mode = INT_DEST_MODE;
2739 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2740 entry.trigger = edge_level;
2741 entry.polarity = active_high_low;
2745 * IRQs < 16 are already in the irq_2_pin[] map
2748 add_pin_to_irq(irq, ioapic, pin);
2750 entry.vector = assign_irq_vector(irq);
2752 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2753 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2754 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2755 edge_level, active_high_low);
2757 ioapic_register_intr(irq, entry.vector, edge_level);
2759 if (!ioapic && (irq < 16))
2760 disable_8259A_irq(irq);
2762 ioapic_write_entry(ioapic, pin, entry);
2763 spin_lock_irqsave(&ioapic_lock, flags);
2764 set_native_irq_info(irq, TARGET_CPUS);
2765 spin_unlock_irqrestore(&ioapic_lock, flags);
2770 #endif /* CONFIG_ACPI */
2772 static int __init parse_disable_timer_pin_1(char *arg)
2774 disable_timer_pin_1 = 1;
2777 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2779 static int __init parse_enable_timer_pin_1(char *arg)
2781 disable_timer_pin_1 = -1;
2784 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2786 static int __init parse_noapic(char *arg)
2788 /* disable IO-APIC */
2789 disable_ioapic_setup();
2792 early_param("noapic", parse_noapic);