2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/compiler.h>
32 #include <linux/acpi.h>
33 #include <linux/module.h>
34 #include <linux/sysdev.h>
39 #include <asm/timer.h>
40 #include <asm/i8259.h>
43 #include <mach_apic.h>
47 int (*ioapic_renumber_irq)(int ioapic, int irq);
48 atomic_t irq_mis_count;
50 /* Where if anywhere is the i8259 connect in external int mode */
51 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
53 static DEFINE_SPINLOCK(ioapic_lock);
54 static DEFINE_SPINLOCK(vector_lock);
56 int timer_over_8254 __initdata = 1;
59 * Is the SiS APIC rmw bug present ?
60 * -1 = don't know, 0 = no, 1 = yes
62 int sis_apic_bug = -1;
65 * # of IRQ routing registers
67 int nr_ioapic_registers[MAX_IO_APICS];
69 int disable_timer_pin_1 __initdata;
72 * Rough estimation of how many shared IRQs there are, can
75 #define MAX_PLUS_SHARED_IRQS NR_IRQS
76 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
79 * This is performance-critical, we want to do it O(1)
81 * the indexing order of this array favors 1:1 mappings
82 * between pins and IRQs.
85 static struct irq_pin_list {
87 } irq_2_pin[PIN_MAP_SIZE];
89 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
91 #define vector_to_irq(vector) \
92 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
94 #define vector_to_irq(vector) (vector)
98 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
99 * shared ISA-space IRQs, so we have to support them. We are super
100 * fast in the common case, and fast for shared ISA-space IRQs.
102 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
104 static int first_free_entry = NR_IRQS;
105 struct irq_pin_list *entry = irq_2_pin + irq;
108 entry = irq_2_pin + entry->next;
110 if (entry->pin != -1) {
111 entry->next = first_free_entry;
112 entry = irq_2_pin + entry->next;
113 if (++first_free_entry >= PIN_MAP_SIZE)
114 panic("io_apic.c: whoops");
121 * Reroute an IRQ to a different pin.
123 static void __init replace_pin_at_irq(unsigned int irq,
124 int oldapic, int oldpin,
125 int newapic, int newpin)
127 struct irq_pin_list *entry = irq_2_pin + irq;
130 if (entry->apic == oldapic && entry->pin == oldpin) {
131 entry->apic = newapic;
136 entry = irq_2_pin + entry->next;
140 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
142 struct irq_pin_list *entry = irq_2_pin + irq;
143 unsigned int pin, reg;
149 reg = io_apic_read(entry->apic, 0x10 + pin*2);
152 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
155 entry = irq_2_pin + entry->next;
160 static void __mask_IO_APIC_irq (unsigned int irq)
162 __modify_IO_APIC_irq(irq, 0x00010000, 0);
166 static void __unmask_IO_APIC_irq (unsigned int irq)
168 __modify_IO_APIC_irq(irq, 0, 0x00010000);
171 /* mask = 1, trigger = 0 */
172 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
174 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
177 /* mask = 0, trigger = 1 */
178 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
180 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
183 static void mask_IO_APIC_irq (unsigned int irq)
187 spin_lock_irqsave(&ioapic_lock, flags);
188 __mask_IO_APIC_irq(irq);
189 spin_unlock_irqrestore(&ioapic_lock, flags);
192 static void unmask_IO_APIC_irq (unsigned int irq)
196 spin_lock_irqsave(&ioapic_lock, flags);
197 __unmask_IO_APIC_irq(irq);
198 spin_unlock_irqrestore(&ioapic_lock, flags);
201 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
203 struct IO_APIC_route_entry entry;
206 /* Check delivery_mode to be sure we're not clearing an SMI pin */
207 spin_lock_irqsave(&ioapic_lock, flags);
208 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
209 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
210 spin_unlock_irqrestore(&ioapic_lock, flags);
211 if (entry.delivery_mode == dest_SMI)
215 * Disable it in the IO-APIC irq-routing table:
217 memset(&entry, 0, sizeof(entry));
219 spin_lock_irqsave(&ioapic_lock, flags);
220 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
221 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
222 spin_unlock_irqrestore(&ioapic_lock, flags);
225 static void clear_IO_APIC (void)
229 for (apic = 0; apic < nr_ioapics; apic++)
230 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
231 clear_IO_APIC_pin(apic, pin);
235 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
239 struct irq_pin_list *entry = irq_2_pin + irq;
240 unsigned int apicid_value;
243 cpus_and(tmp, cpumask, cpu_online_map);
247 cpus_and(cpumask, tmp, CPU_MASK_ALL);
249 apicid_value = cpu_mask_to_apicid(cpumask);
250 /* Prepare to do the io_apic_write */
251 apicid_value = apicid_value << 24;
252 spin_lock_irqsave(&ioapic_lock, flags);
257 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
260 entry = irq_2_pin + entry->next;
262 set_irq_info(irq, cpumask);
263 spin_unlock_irqrestore(&ioapic_lock, flags);
266 #if defined(CONFIG_IRQBALANCE)
267 # include <asm/processor.h> /* kernel_thread() */
268 # include <linux/kernel_stat.h> /* kstat */
269 # include <linux/slab.h> /* kmalloc() */
270 # include <linux/timer.h> /* time_after() */
272 #ifdef CONFIG_BALANCED_IRQ_DEBUG
273 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
274 # define Dprintk(x...) do { TDprintk(x); } while (0)
276 # define TDprintk(x...)
277 # define Dprintk(x...)
280 #define IRQBALANCE_CHECK_ARCH -999
281 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
282 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
283 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
284 #define BALANCED_IRQ_LESS_DELTA (HZ)
286 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
287 static int physical_balance __read_mostly;
288 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
290 static struct irq_cpu_info {
291 unsigned long * last_irq;
292 unsigned long * irq_delta;
294 } irq_cpu_data[NR_CPUS];
296 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
297 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
298 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
300 #define IDLE_ENOUGH(cpu,now) \
301 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
303 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
305 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
307 static cpumask_t balance_irq_affinity[NR_IRQS] = {
308 [0 ... NR_IRQS-1] = CPU_MASK_ALL
311 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
313 balance_irq_affinity[irq] = mask;
316 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
317 unsigned long now, int direction)
325 if (unlikely(cpu == curr_cpu))
328 if (direction == 1) {
337 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
338 (search_idle && !IDLE_ENOUGH(cpu,now)));
343 static inline void balance_irq(int cpu, int irq)
345 unsigned long now = jiffies;
346 cpumask_t allowed_mask;
347 unsigned int new_cpu;
349 if (irqbalance_disabled)
352 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
353 new_cpu = move(cpu, allowed_mask, now, 1);
354 if (cpu != new_cpu) {
355 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
359 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
362 Dprintk("Rotating IRQs among CPUs.\n");
363 for_each_online_cpu(i) {
364 for (j = 0; j < NR_IRQS; j++) {
365 if (!irq_desc[j].action)
367 /* Is it a significant load ? */
368 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
369 useful_load_threshold)
374 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
375 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
379 static void do_irq_balance(void)
382 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
383 unsigned long move_this_load = 0;
384 int max_loaded = 0, min_loaded = 0;
386 unsigned long useful_load_threshold = balanced_irq_interval + 10;
388 int tmp_loaded, first_attempt = 1;
389 unsigned long tmp_cpu_irq;
390 unsigned long imbalance = 0;
391 cpumask_t allowed_mask, target_cpu_mask, tmp;
393 for_each_possible_cpu(i) {
398 package_index = CPU_TO_PACKAGEINDEX(i);
399 for (j = 0; j < NR_IRQS; j++) {
400 unsigned long value_now, delta;
401 /* Is this an active IRQ? */
402 if (!irq_desc[j].action)
404 if ( package_index == i )
405 IRQ_DELTA(package_index,j) = 0;
406 /* Determine the total count per processor per IRQ */
407 value_now = (unsigned long) kstat_cpu(i).irqs[j];
409 /* Determine the activity per processor per IRQ */
410 delta = value_now - LAST_CPU_IRQ(i,j);
412 /* Update last_cpu_irq[][] for the next time */
413 LAST_CPU_IRQ(i,j) = value_now;
415 /* Ignore IRQs whose rate is less than the clock */
416 if (delta < useful_load_threshold)
418 /* update the load for the processor or package total */
419 IRQ_DELTA(package_index,j) += delta;
421 /* Keep track of the higher numbered sibling as well */
422 if (i != package_index)
425 * We have sibling A and sibling B in the package
427 * cpu_irq[A] = load for cpu A + load for cpu B
428 * cpu_irq[B] = load for cpu B
430 CPU_IRQ(package_index) += delta;
433 /* Find the least loaded processor package */
434 for_each_online_cpu(i) {
435 if (i != CPU_TO_PACKAGEINDEX(i))
437 if (min_cpu_irq > CPU_IRQ(i)) {
438 min_cpu_irq = CPU_IRQ(i);
442 max_cpu_irq = ULONG_MAX;
445 /* Look for heaviest loaded processor.
446 * We may come back to get the next heaviest loaded processor.
447 * Skip processors with trivial loads.
451 for_each_online_cpu(i) {
452 if (i != CPU_TO_PACKAGEINDEX(i))
454 if (max_cpu_irq <= CPU_IRQ(i))
456 if (tmp_cpu_irq < CPU_IRQ(i)) {
457 tmp_cpu_irq = CPU_IRQ(i);
462 if (tmp_loaded == -1) {
463 /* In the case of small number of heavy interrupt sources,
464 * loading some of the cpus too much. We use Ingo's original
465 * approach to rotate them around.
467 if (!first_attempt && imbalance >= useful_load_threshold) {
468 rotate_irqs_among_cpus(useful_load_threshold);
471 goto not_worth_the_effort;
474 first_attempt = 0; /* heaviest search */
475 max_cpu_irq = tmp_cpu_irq; /* load */
476 max_loaded = tmp_loaded; /* processor */
477 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
479 Dprintk("max_loaded cpu = %d\n", max_loaded);
480 Dprintk("min_loaded cpu = %d\n", min_loaded);
481 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
482 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
483 Dprintk("load imbalance = %lu\n", imbalance);
485 /* if imbalance is less than approx 10% of max load, then
486 * observe diminishing returns action. - quit
488 if (imbalance < (max_cpu_irq >> 3)) {
489 Dprintk("Imbalance too trivial\n");
490 goto not_worth_the_effort;
494 /* if we select an IRQ to move that can't go where we want, then
495 * see if there is another one to try.
499 for (j = 0; j < NR_IRQS; j++) {
500 /* Is this an active IRQ? */
501 if (!irq_desc[j].action)
503 if (imbalance <= IRQ_DELTA(max_loaded,j))
505 /* Try to find the IRQ that is closest to the imbalance
506 * without going over.
508 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
509 move_this_load = IRQ_DELTA(max_loaded,j);
513 if (selected_irq == -1) {
517 imbalance = move_this_load;
519 /* For physical_balance case, we accumlated both load
520 * values in the one of the siblings cpu_irq[],
521 * to use the same code for physical and logical processors
522 * as much as possible.
524 * NOTE: the cpu_irq[] array holds the sum of the load for
525 * sibling A and sibling B in the slot for the lowest numbered
526 * sibling (A), _AND_ the load for sibling B in the slot for
527 * the higher numbered sibling.
529 * We seek the least loaded sibling by making the comparison
532 load = CPU_IRQ(min_loaded) >> 1;
533 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
534 if (load > CPU_IRQ(j)) {
535 /* This won't change cpu_sibling_map[min_loaded] */
541 cpus_and(allowed_mask,
543 balance_irq_affinity[selected_irq]);
544 target_cpu_mask = cpumask_of_cpu(min_loaded);
545 cpus_and(tmp, target_cpu_mask, allowed_mask);
547 if (!cpus_empty(tmp)) {
549 Dprintk("irq = %d moved to cpu = %d\n",
550 selected_irq, min_loaded);
551 /* mark for change destination */
552 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
554 /* Since we made a change, come back sooner to
555 * check for more variation.
557 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
558 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
563 not_worth_the_effort:
565 * if we did not find an IRQ to move, then adjust the time interval
568 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
569 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
570 Dprintk("IRQ worth rotating not found\n");
574 static int balanced_irq(void *unused)
577 unsigned long prev_balance_time = jiffies;
578 long time_remaining = balanced_irq_interval;
582 /* push everything to CPU 0 to give us a starting point. */
583 for (i = 0 ; i < NR_IRQS ; i++) {
584 pending_irq_cpumask[i] = cpumask_of_cpu(0);
585 set_pending_irq(i, cpumask_of_cpu(0));
589 time_remaining = schedule_timeout_interruptible(time_remaining);
591 if (time_after(jiffies,
592 prev_balance_time+balanced_irq_interval)) {
595 prev_balance_time = jiffies;
596 time_remaining = balanced_irq_interval;
603 static int __init balanced_irq_init(void)
606 struct cpuinfo_x86 *c;
609 cpus_shift_right(tmp, cpu_online_map, 2);
611 /* When not overwritten by the command line ask subarchitecture. */
612 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
613 irqbalance_disabled = NO_BALANCE_IRQ;
614 if (irqbalance_disabled)
617 /* disable irqbalance completely if there is only one processor online */
618 if (num_online_cpus() < 2) {
619 irqbalance_disabled = 1;
623 * Enable physical balance only if more than 1 physical processor
626 if (smp_num_siblings > 1 && !cpus_empty(tmp))
627 physical_balance = 1;
629 for_each_online_cpu(i) {
630 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
631 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
632 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
633 printk(KERN_ERR "balanced_irq_init: out of memory");
636 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
637 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
640 printk(KERN_INFO "Starting balanced_irq\n");
641 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
644 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
646 for_each_possible_cpu(i) {
647 kfree(irq_cpu_data[i].irq_delta);
648 irq_cpu_data[i].irq_delta = NULL;
649 kfree(irq_cpu_data[i].last_irq);
650 irq_cpu_data[i].last_irq = NULL;
655 int __init irqbalance_disable(char *str)
657 irqbalance_disabled = 1;
661 __setup("noirqbalance", irqbalance_disable);
663 late_initcall(balanced_irq_init);
664 #endif /* CONFIG_IRQBALANCE */
665 #endif /* CONFIG_SMP */
668 void fastcall send_IPI_self(int vector)
675 apic_wait_icr_idle();
676 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
678 * Send the IPI. The write to APIC_ICR fires this off.
680 apic_write_around(APIC_ICR, cfg);
682 #endif /* !CONFIG_SMP */
686 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
687 * specific CPU-side IRQs.
691 static int pirq_entries [MAX_PIRQS];
692 static int pirqs_enabled;
693 int skip_ioapic_setup;
695 static int __init ioapic_setup(char *str)
697 skip_ioapic_setup = 1;
701 __setup("noapic", ioapic_setup);
703 static int __init ioapic_pirq_setup(char *str)
706 int ints[MAX_PIRQS+1];
708 get_options(str, ARRAY_SIZE(ints), ints);
710 for (i = 0; i < MAX_PIRQS; i++)
711 pirq_entries[i] = -1;
714 apic_printk(APIC_VERBOSE, KERN_INFO
715 "PIRQ redirection, working around broken MP-BIOS.\n");
717 if (ints[0] < MAX_PIRQS)
720 for (i = 0; i < max; i++) {
721 apic_printk(APIC_VERBOSE, KERN_DEBUG
722 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
724 * PIRQs are mapped upside down, usually.
726 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
731 __setup("pirq=", ioapic_pirq_setup);
734 * Find the IRQ entry number of a certain pin.
736 static int find_irq_entry(int apic, int pin, int type)
740 for (i = 0; i < mp_irq_entries; i++)
741 if (mp_irqs[i].mpc_irqtype == type &&
742 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
743 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
744 mp_irqs[i].mpc_dstirq == pin)
751 * Find the pin to which IRQ[irq] (ISA) is connected
753 static int __init find_isa_irq_pin(int irq, int type)
757 for (i = 0; i < mp_irq_entries; i++) {
758 int lbus = mp_irqs[i].mpc_srcbus;
760 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
761 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
762 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
763 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
765 (mp_irqs[i].mpc_irqtype == type) &&
766 (mp_irqs[i].mpc_srcbusirq == irq))
768 return mp_irqs[i].mpc_dstirq;
773 static int __init find_isa_irq_apic(int irq, int type)
777 for (i = 0; i < mp_irq_entries; i++) {
778 int lbus = mp_irqs[i].mpc_srcbus;
780 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
781 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
782 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
783 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
785 (mp_irqs[i].mpc_irqtype == type) &&
786 (mp_irqs[i].mpc_srcbusirq == irq))
789 if (i < mp_irq_entries) {
791 for(apic = 0; apic < nr_ioapics; apic++) {
792 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
801 * Find a specific PCI IRQ entry.
802 * Not an __init, possibly needed by modules
804 static int pin_2_irq(int idx, int apic, int pin);
806 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
808 int apic, i, best_guess = -1;
810 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
811 "slot:%d, pin:%d.\n", bus, slot, pin);
812 if (mp_bus_id_to_pci_bus[bus] == -1) {
813 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
816 for (i = 0; i < mp_irq_entries; i++) {
817 int lbus = mp_irqs[i].mpc_srcbus;
819 for (apic = 0; apic < nr_ioapics; apic++)
820 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
821 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
824 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
825 !mp_irqs[i].mpc_irqtype &&
827 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
828 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
830 if (!(apic || IO_APIC_IRQ(irq)))
833 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
836 * Use the first all-but-pin matching entry as a
837 * best-guess fuzzy result for broken mptables.
845 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
848 * This function currently is only a helper for the i386 smp boot process where
849 * we need to reprogram the ioredtbls to cater for the cpus which have come online
850 * so mask in all cases should simply be TARGET_CPUS
853 void __init setup_ioapic_dest(void)
855 int pin, ioapic, irq, irq_entry;
857 if (skip_ioapic_setup == 1)
860 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
861 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
862 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
865 irq = pin_2_irq(irq_entry, ioapic, pin);
866 set_ioapic_affinity_irq(irq, TARGET_CPUS);
874 * EISA Edge/Level control register, ELCR
876 static int EISA_ELCR(unsigned int irq)
879 unsigned int port = 0x4d0 + (irq >> 3);
880 return (inb(port) >> (irq & 7)) & 1;
882 apic_printk(APIC_VERBOSE, KERN_INFO
883 "Broken MPtable reports ISA irq %d\n", irq);
887 /* EISA interrupts are always polarity zero and can be edge or level
888 * trigger depending on the ELCR value. If an interrupt is listed as
889 * EISA conforming in the MP table, that means its trigger type must
890 * be read in from the ELCR */
892 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
893 #define default_EISA_polarity(idx) (0)
895 /* ISA interrupts are always polarity zero edge triggered,
896 * when listed as conforming in the MP table. */
898 #define default_ISA_trigger(idx) (0)
899 #define default_ISA_polarity(idx) (0)
901 /* PCI interrupts are always polarity one level triggered,
902 * when listed as conforming in the MP table. */
904 #define default_PCI_trigger(idx) (1)
905 #define default_PCI_polarity(idx) (1)
907 /* MCA interrupts are always polarity zero level triggered,
908 * when listed as conforming in the MP table. */
910 #define default_MCA_trigger(idx) (1)
911 #define default_MCA_polarity(idx) (0)
913 /* NEC98 interrupts are always polarity zero edge triggered,
914 * when listed as conforming in the MP table. */
916 #define default_NEC98_trigger(idx) (0)
917 #define default_NEC98_polarity(idx) (0)
919 static int __init MPBIOS_polarity(int idx)
921 int bus = mp_irqs[idx].mpc_srcbus;
925 * Determine IRQ line polarity (high active or low active):
927 switch (mp_irqs[idx].mpc_irqflag & 3)
929 case 0: /* conforms, ie. bus-type dependent polarity */
931 switch (mp_bus_id_to_type[bus])
933 case MP_BUS_ISA: /* ISA pin */
935 polarity = default_ISA_polarity(idx);
938 case MP_BUS_EISA: /* EISA pin */
940 polarity = default_EISA_polarity(idx);
943 case MP_BUS_PCI: /* PCI pin */
945 polarity = default_PCI_polarity(idx);
948 case MP_BUS_MCA: /* MCA pin */
950 polarity = default_MCA_polarity(idx);
953 case MP_BUS_NEC98: /* NEC 98 pin */
955 polarity = default_NEC98_polarity(idx);
960 printk(KERN_WARNING "broken BIOS!!\n");
967 case 1: /* high active */
972 case 2: /* reserved */
974 printk(KERN_WARNING "broken BIOS!!\n");
978 case 3: /* low active */
983 default: /* invalid */
985 printk(KERN_WARNING "broken BIOS!!\n");
993 static int MPBIOS_trigger(int idx)
995 int bus = mp_irqs[idx].mpc_srcbus;
999 * Determine IRQ trigger mode (edge or level sensitive):
1001 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1003 case 0: /* conforms, ie. bus-type dependent */
1005 switch (mp_bus_id_to_type[bus])
1007 case MP_BUS_ISA: /* ISA pin */
1009 trigger = default_ISA_trigger(idx);
1012 case MP_BUS_EISA: /* EISA pin */
1014 trigger = default_EISA_trigger(idx);
1017 case MP_BUS_PCI: /* PCI pin */
1019 trigger = default_PCI_trigger(idx);
1022 case MP_BUS_MCA: /* MCA pin */
1024 trigger = default_MCA_trigger(idx);
1027 case MP_BUS_NEC98: /* NEC 98 pin */
1029 trigger = default_NEC98_trigger(idx);
1034 printk(KERN_WARNING "broken BIOS!!\n");
1046 case 2: /* reserved */
1048 printk(KERN_WARNING "broken BIOS!!\n");
1057 default: /* invalid */
1059 printk(KERN_WARNING "broken BIOS!!\n");
1067 static inline int irq_polarity(int idx)
1069 return MPBIOS_polarity(idx);
1072 static inline int irq_trigger(int idx)
1074 return MPBIOS_trigger(idx);
1077 static int pin_2_irq(int idx, int apic, int pin)
1080 int bus = mp_irqs[idx].mpc_srcbus;
1083 * Debugging check, we are in big trouble if this message pops up!
1085 if (mp_irqs[idx].mpc_dstirq != pin)
1086 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1088 switch (mp_bus_id_to_type[bus])
1090 case MP_BUS_ISA: /* ISA pin */
1095 irq = mp_irqs[idx].mpc_srcbusirq;
1098 case MP_BUS_PCI: /* PCI pin */
1101 * PCI IRQs are mapped in order
1105 irq += nr_ioapic_registers[i++];
1109 * For MPS mode, so far only needed by ES7000 platform
1111 if (ioapic_renumber_irq)
1112 irq = ioapic_renumber_irq(apic, irq);
1118 printk(KERN_ERR "unknown bus type %d.\n",bus);
1125 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1127 if ((pin >= 16) && (pin <= 23)) {
1128 if (pirq_entries[pin-16] != -1) {
1129 if (!pirq_entries[pin-16]) {
1130 apic_printk(APIC_VERBOSE, KERN_DEBUG
1131 "disabling PIRQ%d\n", pin-16);
1133 irq = pirq_entries[pin-16];
1134 apic_printk(APIC_VERBOSE, KERN_DEBUG
1135 "using PIRQ%d -> IRQ %d\n",
1143 static inline int IO_APIC_irq_trigger(int irq)
1147 for (apic = 0; apic < nr_ioapics; apic++) {
1148 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1149 idx = find_irq_entry(apic,pin,mp_INT);
1150 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1151 return irq_trigger(idx);
1155 * nonexistent IRQs are edge default
1160 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1161 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1163 int assign_irq_vector(int irq)
1165 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1166 unsigned long flags;
1169 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1171 spin_lock_irqsave(&vector_lock, flags);
1173 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1174 spin_unlock_irqrestore(&vector_lock, flags);
1175 return IO_APIC_VECTOR(irq);
1178 current_vector += 8;
1179 if (current_vector == SYSCALL_VECTOR)
1182 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1185 spin_unlock_irqrestore(&vector_lock, flags);
1188 current_vector = FIRST_DEVICE_VECTOR + offset;
1191 vector = current_vector;
1192 vector_irq[vector] = irq;
1193 if (irq != AUTO_ASSIGN)
1194 IO_APIC_VECTOR(irq) = vector;
1196 spin_unlock_irqrestore(&vector_lock, flags);
1201 static struct hw_interrupt_type ioapic_level_type;
1202 static struct hw_interrupt_type ioapic_edge_type;
1204 #define IOAPIC_AUTO -1
1205 #define IOAPIC_EDGE 0
1206 #define IOAPIC_LEVEL 1
1208 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1210 unsigned idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1212 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1213 trigger == IOAPIC_LEVEL)
1214 irq_desc[idx].handler = &ioapic_level_type;
1216 irq_desc[idx].handler = &ioapic_edge_type;
1217 set_intr_gate(vector, interrupt[idx]);
1220 static void __init setup_IO_APIC_irqs(void)
1222 struct IO_APIC_route_entry entry;
1223 int apic, pin, idx, irq, first_notcon = 1, vector;
1224 unsigned long flags;
1226 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1228 for (apic = 0; apic < nr_ioapics; apic++) {
1229 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1232 * add it to the IO-APIC irq-routing table:
1234 memset(&entry,0,sizeof(entry));
1236 entry.delivery_mode = INT_DELIVERY_MODE;
1237 entry.dest_mode = INT_DEST_MODE;
1238 entry.mask = 0; /* enable IRQ */
1239 entry.dest.logical.logical_dest =
1240 cpu_mask_to_apicid(TARGET_CPUS);
1242 idx = find_irq_entry(apic,pin,mp_INT);
1245 apic_printk(APIC_VERBOSE, KERN_DEBUG
1246 " IO-APIC (apicid-pin) %d-%d",
1247 mp_ioapics[apic].mpc_apicid,
1251 apic_printk(APIC_VERBOSE, ", %d-%d",
1252 mp_ioapics[apic].mpc_apicid, pin);
1256 entry.trigger = irq_trigger(idx);
1257 entry.polarity = irq_polarity(idx);
1259 if (irq_trigger(idx)) {
1264 irq = pin_2_irq(idx, apic, pin);
1266 * skip adding the timer int on secondary nodes, which causes
1267 * a small but painful rift in the time-space continuum
1269 if (multi_timer_check(apic, irq))
1272 add_pin_to_irq(irq, apic, pin);
1274 if (!apic && !IO_APIC_IRQ(irq))
1277 if (IO_APIC_IRQ(irq)) {
1278 vector = assign_irq_vector(irq);
1279 entry.vector = vector;
1280 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1282 if (!apic && (irq < 16))
1283 disable_8259A_irq(irq);
1285 spin_lock_irqsave(&ioapic_lock, flags);
1286 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1287 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1288 set_native_irq_info(irq, TARGET_CPUS);
1289 spin_unlock_irqrestore(&ioapic_lock, flags);
1294 apic_printk(APIC_VERBOSE, " not connected.\n");
1298 * Set up the 8259A-master output pin:
1300 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1302 struct IO_APIC_route_entry entry;
1303 unsigned long flags;
1305 memset(&entry,0,sizeof(entry));
1307 disable_8259A_irq(0);
1310 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1313 * We use logical delivery to get the timer IRQ
1316 entry.dest_mode = INT_DEST_MODE;
1317 entry.mask = 0; /* unmask IRQ now */
1318 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1319 entry.delivery_mode = INT_DELIVERY_MODE;
1322 entry.vector = vector;
1325 * The timer IRQ doesn't have to know that behind the
1326 * scene we have a 8259A-master in AEOI mode ...
1328 irq_desc[0].handler = &ioapic_edge_type;
1331 * Add it to the IO-APIC irq-routing table:
1333 spin_lock_irqsave(&ioapic_lock, flags);
1334 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1335 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1336 spin_unlock_irqrestore(&ioapic_lock, flags);
1338 enable_8259A_irq(0);
1341 static inline void UNEXPECTED_IO_APIC(void)
1345 void __init print_IO_APIC(void)
1348 union IO_APIC_reg_00 reg_00;
1349 union IO_APIC_reg_01 reg_01;
1350 union IO_APIC_reg_02 reg_02;
1351 union IO_APIC_reg_03 reg_03;
1352 unsigned long flags;
1354 if (apic_verbosity == APIC_QUIET)
1357 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1358 for (i = 0; i < nr_ioapics; i++)
1359 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1360 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1363 * We are a bit conservative about what we expect. We have to
1364 * know about every hardware change ASAP.
1366 printk(KERN_INFO "testing the IO APIC.......................\n");
1368 for (apic = 0; apic < nr_ioapics; apic++) {
1370 spin_lock_irqsave(&ioapic_lock, flags);
1371 reg_00.raw = io_apic_read(apic, 0);
1372 reg_01.raw = io_apic_read(apic, 1);
1373 if (reg_01.bits.version >= 0x10)
1374 reg_02.raw = io_apic_read(apic, 2);
1375 if (reg_01.bits.version >= 0x20)
1376 reg_03.raw = io_apic_read(apic, 3);
1377 spin_unlock_irqrestore(&ioapic_lock, flags);
1379 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1380 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1381 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1382 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1383 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1384 if (reg_00.bits.ID >= get_physical_broadcast())
1385 UNEXPECTED_IO_APIC();
1386 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1387 UNEXPECTED_IO_APIC();
1389 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1390 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1391 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1392 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1393 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1394 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1395 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1396 (reg_01.bits.entries != 0x2E) &&
1397 (reg_01.bits.entries != 0x3F)
1399 UNEXPECTED_IO_APIC();
1401 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1402 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1403 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1404 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1405 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1406 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1407 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1409 UNEXPECTED_IO_APIC();
1410 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1411 UNEXPECTED_IO_APIC();
1414 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1415 * but the value of reg_02 is read as the previous read register
1416 * value, so ignore it if reg_02 == reg_01.
1418 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1419 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1420 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1421 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1422 UNEXPECTED_IO_APIC();
1426 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1427 * or reg_03, but the value of reg_0[23] is read as the previous read
1428 * register value, so ignore it if reg_03 == reg_0[12].
1430 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1431 reg_03.raw != reg_01.raw) {
1432 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1433 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1434 if (reg_03.bits.__reserved_1)
1435 UNEXPECTED_IO_APIC();
1438 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1440 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1441 " Stat Dest Deli Vect: \n");
1443 for (i = 0; i <= reg_01.bits.entries; i++) {
1444 struct IO_APIC_route_entry entry;
1446 spin_lock_irqsave(&ioapic_lock, flags);
1447 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1448 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1449 spin_unlock_irqrestore(&ioapic_lock, flags);
1451 printk(KERN_DEBUG " %02x %03X %02X ",
1453 entry.dest.logical.logical_dest,
1454 entry.dest.physical.physical_dest
1457 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1462 entry.delivery_status,
1464 entry.delivery_mode,
1469 if (use_pci_vector())
1470 printk(KERN_INFO "Using vector-based indexing\n");
1471 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1472 for (i = 0; i < NR_IRQS; i++) {
1473 struct irq_pin_list *entry = irq_2_pin + i;
1476 if (use_pci_vector() && !platform_legacy_irq(i))
1477 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1479 printk(KERN_DEBUG "IRQ%d ", i);
1481 printk("-> %d:%d", entry->apic, entry->pin);
1484 entry = irq_2_pin + entry->next;
1489 printk(KERN_INFO ".................................... done.\n");
1496 static void print_APIC_bitfield (int base)
1501 if (apic_verbosity == APIC_QUIET)
1504 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1505 for (i = 0; i < 8; i++) {
1506 v = apic_read(base + i*0x10);
1507 for (j = 0; j < 32; j++) {
1517 void /*__init*/ print_local_APIC(void * dummy)
1519 unsigned int v, ver, maxlvt;
1521 if (apic_verbosity == APIC_QUIET)
1524 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1525 smp_processor_id(), hard_smp_processor_id());
1526 v = apic_read(APIC_ID);
1527 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1528 v = apic_read(APIC_LVR);
1529 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1530 ver = GET_APIC_VERSION(v);
1531 maxlvt = get_maxlvt();
1533 v = apic_read(APIC_TASKPRI);
1534 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1536 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1537 v = apic_read(APIC_ARBPRI);
1538 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1539 v & APIC_ARBPRI_MASK);
1540 v = apic_read(APIC_PROCPRI);
1541 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1544 v = apic_read(APIC_EOI);
1545 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1546 v = apic_read(APIC_RRR);
1547 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1548 v = apic_read(APIC_LDR);
1549 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1550 v = apic_read(APIC_DFR);
1551 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1552 v = apic_read(APIC_SPIV);
1553 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1555 printk(KERN_DEBUG "... APIC ISR field:\n");
1556 print_APIC_bitfield(APIC_ISR);
1557 printk(KERN_DEBUG "... APIC TMR field:\n");
1558 print_APIC_bitfield(APIC_TMR);
1559 printk(KERN_DEBUG "... APIC IRR field:\n");
1560 print_APIC_bitfield(APIC_IRR);
1562 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1563 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1564 apic_write(APIC_ESR, 0);
1565 v = apic_read(APIC_ESR);
1566 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1569 v = apic_read(APIC_ICR);
1570 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1571 v = apic_read(APIC_ICR2);
1572 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1574 v = apic_read(APIC_LVTT);
1575 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1577 if (maxlvt > 3) { /* PC is LVT#4. */
1578 v = apic_read(APIC_LVTPC);
1579 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1581 v = apic_read(APIC_LVT0);
1582 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1583 v = apic_read(APIC_LVT1);
1584 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1586 if (maxlvt > 2) { /* ERR is LVT#3. */
1587 v = apic_read(APIC_LVTERR);
1588 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1591 v = apic_read(APIC_TMICT);
1592 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1593 v = apic_read(APIC_TMCCT);
1594 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1595 v = apic_read(APIC_TDCR);
1596 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1600 void print_all_local_APICs (void)
1602 on_each_cpu(print_local_APIC, NULL, 1, 1);
1605 void /*__init*/ print_PIC(void)
1608 unsigned long flags;
1610 if (apic_verbosity == APIC_QUIET)
1613 printk(KERN_DEBUG "\nprinting PIC contents\n");
1615 spin_lock_irqsave(&i8259A_lock, flags);
1617 v = inb(0xa1) << 8 | inb(0x21);
1618 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1620 v = inb(0xa0) << 8 | inb(0x20);
1621 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1625 v = inb(0xa0) << 8 | inb(0x20);
1629 spin_unlock_irqrestore(&i8259A_lock, flags);
1631 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1633 v = inb(0x4d1) << 8 | inb(0x4d0);
1634 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1639 static void __init enable_IO_APIC(void)
1641 union IO_APIC_reg_01 reg_01;
1642 int i8259_apic, i8259_pin;
1644 unsigned long flags;
1646 for (i = 0; i < PIN_MAP_SIZE; i++) {
1647 irq_2_pin[i].pin = -1;
1648 irq_2_pin[i].next = 0;
1651 for (i = 0; i < MAX_PIRQS; i++)
1652 pirq_entries[i] = -1;
1655 * The number of IO-APIC IRQ registers (== #pins):
1657 for (apic = 0; apic < nr_ioapics; apic++) {
1658 spin_lock_irqsave(&ioapic_lock, flags);
1659 reg_01.raw = io_apic_read(apic, 1);
1660 spin_unlock_irqrestore(&ioapic_lock, flags);
1661 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1663 for(apic = 0; apic < nr_ioapics; apic++) {
1665 /* See if any of the pins is in ExtINT mode */
1666 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1667 struct IO_APIC_route_entry entry;
1668 spin_lock_irqsave(&ioapic_lock, flags);
1669 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1670 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1671 spin_unlock_irqrestore(&ioapic_lock, flags);
1674 /* If the interrupt line is enabled and in ExtInt mode
1675 * I have found the pin where the i8259 is connected.
1677 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1678 ioapic_i8259.apic = apic;
1679 ioapic_i8259.pin = pin;
1685 /* Look to see what if the MP table has reported the ExtINT */
1686 /* If we could not find the appropriate pin by looking at the ioapic
1687 * the i8259 probably is not connected the ioapic but give the
1688 * mptable a chance anyway.
1690 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1691 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1692 /* Trust the MP table if nothing is setup in the hardware */
1693 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1694 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1695 ioapic_i8259.pin = i8259_pin;
1696 ioapic_i8259.apic = i8259_apic;
1698 /* Complain if the MP table and the hardware disagree */
1699 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1700 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1702 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1706 * Do not trust the IO-APIC being empty at bootup
1712 * Not an __init, needed by the reboot code
1714 void disable_IO_APIC(void)
1717 * Clear the IO-APIC before rebooting:
1722 * If the i8259 is routed through an IOAPIC
1723 * Put that IOAPIC in virtual wire mode
1724 * so legacy interrupts can be delivered.
1726 if (ioapic_i8259.pin != -1) {
1727 struct IO_APIC_route_entry entry;
1728 unsigned long flags;
1730 memset(&entry, 0, sizeof(entry));
1731 entry.mask = 0; /* Enabled */
1732 entry.trigger = 0; /* Edge */
1734 entry.polarity = 0; /* High */
1735 entry.delivery_status = 0;
1736 entry.dest_mode = 0; /* Physical */
1737 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1739 entry.dest.physical.physical_dest =
1740 GET_APIC_ID(apic_read(APIC_ID));
1743 * Add it to the IO-APIC irq-routing table:
1745 spin_lock_irqsave(&ioapic_lock, flags);
1746 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1747 *(((int *)&entry)+1));
1748 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1749 *(((int *)&entry)+0));
1750 spin_unlock_irqrestore(&ioapic_lock, flags);
1752 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1756 * function to set the IO-APIC physical IDs based on the
1757 * values stored in the MPC table.
1759 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1762 #ifndef CONFIG_X86_NUMAQ
1763 static void __init setup_ioapic_ids_from_mpc(void)
1765 union IO_APIC_reg_00 reg_00;
1766 physid_mask_t phys_id_present_map;
1769 unsigned char old_id;
1770 unsigned long flags;
1773 * Don't check I/O APIC IDs for xAPIC systems. They have
1774 * no meaning without the serial APIC bus.
1776 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1777 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1780 * This is broken; anything with a real cpu count has to
1781 * circumvent this idiocy regardless.
1783 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1786 * Set the IOAPIC ID to the value stored in the MPC table.
1788 for (apic = 0; apic < nr_ioapics; apic++) {
1790 /* Read the register 0 value */
1791 spin_lock_irqsave(&ioapic_lock, flags);
1792 reg_00.raw = io_apic_read(apic, 0);
1793 spin_unlock_irqrestore(&ioapic_lock, flags);
1795 old_id = mp_ioapics[apic].mpc_apicid;
1797 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1798 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1799 apic, mp_ioapics[apic].mpc_apicid);
1800 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1802 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1806 * Sanity check, is the ID really free? Every APIC in a
1807 * system must have a unique ID or we get lots of nice
1808 * 'stuck on smp_invalidate_needed IPI wait' messages.
1810 if (check_apicid_used(phys_id_present_map,
1811 mp_ioapics[apic].mpc_apicid)) {
1812 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1813 apic, mp_ioapics[apic].mpc_apicid);
1814 for (i = 0; i < get_physical_broadcast(); i++)
1815 if (!physid_isset(i, phys_id_present_map))
1817 if (i >= get_physical_broadcast())
1818 panic("Max APIC ID exceeded!\n");
1819 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1821 physid_set(i, phys_id_present_map);
1822 mp_ioapics[apic].mpc_apicid = i;
1825 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1826 apic_printk(APIC_VERBOSE, "Setting %d in the "
1827 "phys_id_present_map\n",
1828 mp_ioapics[apic].mpc_apicid);
1829 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1834 * We need to adjust the IRQ routing table
1835 * if the ID changed.
1837 if (old_id != mp_ioapics[apic].mpc_apicid)
1838 for (i = 0; i < mp_irq_entries; i++)
1839 if (mp_irqs[i].mpc_dstapic == old_id)
1840 mp_irqs[i].mpc_dstapic
1841 = mp_ioapics[apic].mpc_apicid;
1844 * Read the right value from the MPC table and
1845 * write it into the ID register.
1847 apic_printk(APIC_VERBOSE, KERN_INFO
1848 "...changing IO-APIC physical APIC ID to %d ...",
1849 mp_ioapics[apic].mpc_apicid);
1851 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1852 spin_lock_irqsave(&ioapic_lock, flags);
1853 io_apic_write(apic, 0, reg_00.raw);
1854 spin_unlock_irqrestore(&ioapic_lock, flags);
1859 spin_lock_irqsave(&ioapic_lock, flags);
1860 reg_00.raw = io_apic_read(apic, 0);
1861 spin_unlock_irqrestore(&ioapic_lock, flags);
1862 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1863 printk("could not set ID!\n");
1865 apic_printk(APIC_VERBOSE, " ok.\n");
1869 static void __init setup_ioapic_ids_from_mpc(void) { }
1873 * There is a nasty bug in some older SMP boards, their mptable lies
1874 * about the timer IRQ. We do the following to work around the situation:
1876 * - timer IRQ defaults to IO-APIC IRQ
1877 * - if this function detects that timer IRQs are defunct, then we fall
1878 * back to ISA timer IRQs
1880 static int __init timer_irq_works(void)
1882 unsigned long t1 = jiffies;
1885 /* Let ten ticks pass... */
1886 mdelay((10 * 1000) / HZ);
1889 * Expect a few ticks at least, to be sure some possible
1890 * glue logic does not lock up after one or two first
1891 * ticks in a non-ExtINT mode. Also the local APIC
1892 * might have cached one ExtINT interrupt. Finally, at
1893 * least one tick may be lost due to delays.
1895 if (jiffies - t1 > 4)
1902 * In the SMP+IOAPIC case it might happen that there are an unspecified
1903 * number of pending IRQ events unhandled. These cases are very rare,
1904 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1905 * better to do it this way as thus we do not have to be aware of
1906 * 'pending' interrupts in the IRQ path, except at this point.
1909 * Edge triggered needs to resend any interrupt
1910 * that was delayed but this is now handled in the device
1915 * Starting up a edge-triggered IO-APIC interrupt is
1916 * nasty - we need to make sure that we get the edge.
1917 * If it is already asserted for some reason, we need
1918 * return 1 to indicate that is was pending.
1920 * This is not complete - we should be able to fake
1921 * an edge even if it isn't on the 8259A...
1923 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1925 int was_pending = 0;
1926 unsigned long flags;
1928 spin_lock_irqsave(&ioapic_lock, flags);
1930 disable_8259A_irq(irq);
1931 if (i8259A_irq_pending(irq))
1934 __unmask_IO_APIC_irq(irq);
1935 spin_unlock_irqrestore(&ioapic_lock, flags);
1941 * Once we have recorded IRQ_PENDING already, we can mask the
1942 * interrupt for real. This prevents IRQ storms from unhandled
1945 static void ack_edge_ioapic_irq(unsigned int irq)
1948 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1949 == (IRQ_PENDING | IRQ_DISABLED))
1950 mask_IO_APIC_irq(irq);
1955 * Level triggered interrupts can just be masked,
1956 * and shutting down and starting up the interrupt
1957 * is the same as enabling and disabling them -- except
1958 * with a startup need to return a "was pending" value.
1960 * Level triggered interrupts are special because we
1961 * do not touch any IO-APIC register while handling
1962 * them. We ack the APIC in the end-IRQ handler, not
1963 * in the start-IRQ-handler. Protection against reentrance
1964 * from the same interrupt is still provided, both by the
1965 * generic IRQ layer and by the fact that an unacked local
1966 * APIC does not accept IRQs.
1968 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1970 unmask_IO_APIC_irq(irq);
1972 return 0; /* don't check for pending */
1975 static void end_level_ioapic_irq (unsigned int irq)
1982 * It appears there is an erratum which affects at least version 0x11
1983 * of I/O APIC (that's the 82093AA and cores integrated into various
1984 * chipsets). Under certain conditions a level-triggered interrupt is
1985 * erroneously delivered as edge-triggered one but the respective IRR
1986 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1987 * message but it will never arrive and further interrupts are blocked
1988 * from the source. The exact reason is so far unknown, but the
1989 * phenomenon was observed when two consecutive interrupt requests
1990 * from a given source get delivered to the same CPU and the source is
1991 * temporarily disabled in between.
1993 * A workaround is to simulate an EOI message manually. We achieve it
1994 * by setting the trigger mode to edge and then to level when the edge
1995 * trigger mode gets detected in the TMR of a local APIC for a
1996 * level-triggered interrupt. We mask the source for the time of the
1997 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1998 * The idea is from Manfred Spraul. --macro
2000 i = IO_APIC_VECTOR(irq);
2002 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2006 if (!(v & (1 << (i & 0x1f)))) {
2007 atomic_inc(&irq_mis_count);
2008 spin_lock(&ioapic_lock);
2009 __mask_and_edge_IO_APIC_irq(irq);
2010 __unmask_and_level_IO_APIC_irq(irq);
2011 spin_unlock(&ioapic_lock);
2015 #ifdef CONFIG_PCI_MSI
2016 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2018 int irq = vector_to_irq(vector);
2020 return startup_edge_ioapic_irq(irq);
2023 static void ack_edge_ioapic_vector(unsigned int vector)
2025 int irq = vector_to_irq(vector);
2027 move_native_irq(vector);
2028 ack_edge_ioapic_irq(irq);
2031 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2033 int irq = vector_to_irq(vector);
2035 return startup_level_ioapic_irq (irq);
2038 static void end_level_ioapic_vector (unsigned int vector)
2040 int irq = vector_to_irq(vector);
2042 move_native_irq(vector);
2043 end_level_ioapic_irq(irq);
2046 static void mask_IO_APIC_vector (unsigned int vector)
2048 int irq = vector_to_irq(vector);
2050 mask_IO_APIC_irq(irq);
2053 static void unmask_IO_APIC_vector (unsigned int vector)
2055 int irq = vector_to_irq(vector);
2057 unmask_IO_APIC_irq(irq);
2061 static void set_ioapic_affinity_vector (unsigned int vector,
2064 int irq = vector_to_irq(vector);
2066 set_native_irq_info(vector, cpu_mask);
2067 set_ioapic_affinity_irq(irq, cpu_mask);
2073 * Level and edge triggered IO-APIC interrupts need different handling,
2074 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2075 * handled with the level-triggered descriptor, but that one has slightly
2076 * more overhead. Level-triggered interrupts cannot be handled with the
2077 * edge-triggered handler, without risking IRQ storms and other ugly
2080 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2081 .typename = "IO-APIC-edge",
2082 .startup = startup_edge_ioapic,
2083 .shutdown = shutdown_edge_ioapic,
2084 .enable = enable_edge_ioapic,
2085 .disable = disable_edge_ioapic,
2086 .ack = ack_edge_ioapic,
2087 .end = end_edge_ioapic,
2089 .set_affinity = set_ioapic_affinity,
2093 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2094 .typename = "IO-APIC-level",
2095 .startup = startup_level_ioapic,
2096 .shutdown = shutdown_level_ioapic,
2097 .enable = enable_level_ioapic,
2098 .disable = disable_level_ioapic,
2099 .ack = mask_and_ack_level_ioapic,
2100 .end = end_level_ioapic,
2102 .set_affinity = set_ioapic_affinity,
2106 static inline void init_IO_APIC_traps(void)
2111 * NOTE! The local APIC isn't very good at handling
2112 * multiple interrupts at the same interrupt level.
2113 * As the interrupt level is determined by taking the
2114 * vector number and shifting that right by 4, we
2115 * want to spread these out a bit so that they don't
2116 * all fall in the same interrupt level.
2118 * Also, we've got to be careful not to trash gate
2119 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2121 for (irq = 0; irq < NR_IRQS ; irq++) {
2123 if (use_pci_vector()) {
2124 if (!platform_legacy_irq(tmp))
2125 if ((tmp = vector_to_irq(tmp)) == -1)
2128 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2130 * Hmm.. We don't have an entry for this,
2131 * so default to an old-fashioned 8259
2132 * interrupt if we can..
2135 make_8259A_irq(irq);
2137 /* Strange. Oh, well.. */
2138 irq_desc[irq].handler = &no_irq_type;
2143 static void enable_lapic_irq (unsigned int irq)
2147 v = apic_read(APIC_LVT0);
2148 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2151 static void disable_lapic_irq (unsigned int irq)
2155 v = apic_read(APIC_LVT0);
2156 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2159 static void ack_lapic_irq (unsigned int irq)
2164 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2166 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2167 .typename = "local-APIC-edge",
2168 .startup = NULL, /* startup_irq() not used for IRQ0 */
2169 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2170 .enable = enable_lapic_irq,
2171 .disable = disable_lapic_irq,
2172 .ack = ack_lapic_irq,
2173 .end = end_lapic_irq
2176 static void setup_nmi (void)
2179 * Dirty trick to enable the NMI watchdog ...
2180 * We put the 8259A master into AEOI mode and
2181 * unmask on all local APICs LVT0 as NMI.
2183 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2184 * is from Maciej W. Rozycki - so we do not have to EOI from
2185 * the NMI handler or the timer interrupt.
2187 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2189 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2191 apic_printk(APIC_VERBOSE, " done.\n");
2195 * This looks a bit hackish but it's about the only one way of sending
2196 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2197 * not support the ExtINT mode, unfortunately. We need to send these
2198 * cycles as some i82489DX-based boards have glue logic that keeps the
2199 * 8259A interrupt line asserted until INTA. --macro
2201 static inline void unlock_ExtINT_logic(void)
2204 struct IO_APIC_route_entry entry0, entry1;
2205 unsigned char save_control, save_freq_select;
2206 unsigned long flags;
2208 pin = find_isa_irq_pin(8, mp_INT);
2209 apic = find_isa_irq_apic(8, mp_INT);
2213 spin_lock_irqsave(&ioapic_lock, flags);
2214 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2215 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2216 spin_unlock_irqrestore(&ioapic_lock, flags);
2217 clear_IO_APIC_pin(apic, pin);
2219 memset(&entry1, 0, sizeof(entry1));
2221 entry1.dest_mode = 0; /* physical delivery */
2222 entry1.mask = 0; /* unmask IRQ now */
2223 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2224 entry1.delivery_mode = dest_ExtINT;
2225 entry1.polarity = entry0.polarity;
2229 spin_lock_irqsave(&ioapic_lock, flags);
2230 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2231 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2232 spin_unlock_irqrestore(&ioapic_lock, flags);
2234 save_control = CMOS_READ(RTC_CONTROL);
2235 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2236 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2238 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2243 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2247 CMOS_WRITE(save_control, RTC_CONTROL);
2248 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2249 clear_IO_APIC_pin(apic, pin);
2251 spin_lock_irqsave(&ioapic_lock, flags);
2252 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2253 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2254 spin_unlock_irqrestore(&ioapic_lock, flags);
2257 int timer_uses_ioapic_pin_0;
2260 * This code may look a bit paranoid, but it's supposed to cooperate with
2261 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2262 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2263 * fanatically on his truly buggy board.
2265 static inline void check_timer(void)
2267 int apic1, pin1, apic2, pin2;
2271 * get/set the timer IRQ vector:
2273 disable_8259A_irq(0);
2274 vector = assign_irq_vector(0);
2275 set_intr_gate(vector, interrupt[0]);
2278 * Subtle, code in do_timer_interrupt() expects an AEOI
2279 * mode for the 8259A whenever interrupts are routed
2280 * through I/O APICs. Also IRQ0 has to be enabled in
2281 * the 8259A which implies the virtual wire has to be
2282 * disabled in the local APIC.
2284 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2287 if (timer_over_8254 > 0)
2288 enable_8259A_irq(0);
2290 pin1 = find_isa_irq_pin(0, mp_INT);
2291 apic1 = find_isa_irq_apic(0, mp_INT);
2292 pin2 = ioapic_i8259.pin;
2293 apic2 = ioapic_i8259.apic;
2296 timer_uses_ioapic_pin_0 = 1;
2298 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2299 vector, apic1, pin1, apic2, pin2);
2303 * Ok, does IRQ0 through the IOAPIC work?
2305 unmask_IO_APIC_irq(0);
2306 if (timer_irq_works()) {
2307 if (nmi_watchdog == NMI_IO_APIC) {
2308 disable_8259A_irq(0);
2310 enable_8259A_irq(0);
2312 if (disable_timer_pin_1 > 0)
2313 clear_IO_APIC_pin(0, pin1);
2316 clear_IO_APIC_pin(apic1, pin1);
2317 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2321 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2323 printk("\n..... (found pin %d) ...", pin2);
2325 * legacy devices should be connected to IO APIC #0
2327 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2328 if (timer_irq_works()) {
2331 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2333 add_pin_to_irq(0, apic2, pin2);
2334 if (nmi_watchdog == NMI_IO_APIC) {
2340 * Cleanup, just in case ...
2342 clear_IO_APIC_pin(apic2, pin2);
2344 printk(" failed.\n");
2346 if (nmi_watchdog == NMI_IO_APIC) {
2347 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2351 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2353 disable_8259A_irq(0);
2354 irq_desc[0].handler = &lapic_irq_type;
2355 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2356 enable_8259A_irq(0);
2358 if (timer_irq_works()) {
2359 printk(" works.\n");
2362 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2363 printk(" failed.\n");
2365 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2370 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2372 unlock_ExtINT_logic();
2374 if (timer_irq_works()) {
2375 printk(" works.\n");
2378 printk(" failed :(.\n");
2379 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2380 "report. Then try booting with the 'noapic' option");
2385 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2386 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2387 * Linux doesn't really care, as it's not actually used
2388 * for any interrupt handling anyway.
2390 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2392 void __init setup_IO_APIC(void)
2397 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2399 io_apic_irqs = ~PIC_IRQS;
2401 printk("ENABLING IO-APIC IRQs\n");
2404 * Set up IO-APIC IRQ routing.
2407 setup_ioapic_ids_from_mpc();
2409 setup_IO_APIC_irqs();
2410 init_IO_APIC_traps();
2416 static int __init setup_disable_8254_timer(char *s)
2418 timer_over_8254 = -1;
2421 static int __init setup_enable_8254_timer(char *s)
2423 timer_over_8254 = 2;
2427 __setup("disable_8254_timer", setup_disable_8254_timer);
2428 __setup("enable_8254_timer", setup_enable_8254_timer);
2431 * Called after all the initialization is done. If we didnt find any
2432 * APIC bugs then we can allow the modify fast path
2435 static int __init io_apic_bug_finalize(void)
2437 if(sis_apic_bug == -1)
2442 late_initcall(io_apic_bug_finalize);
2444 struct sysfs_ioapic_data {
2445 struct sys_device dev;
2446 struct IO_APIC_route_entry entry[0];
2448 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2450 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2452 struct IO_APIC_route_entry *entry;
2453 struct sysfs_ioapic_data *data;
2454 unsigned long flags;
2457 data = container_of(dev, struct sysfs_ioapic_data, dev);
2458 entry = data->entry;
2459 spin_lock_irqsave(&ioapic_lock, flags);
2460 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2461 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2462 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2464 spin_unlock_irqrestore(&ioapic_lock, flags);
2469 static int ioapic_resume(struct sys_device *dev)
2471 struct IO_APIC_route_entry *entry;
2472 struct sysfs_ioapic_data *data;
2473 unsigned long flags;
2474 union IO_APIC_reg_00 reg_00;
2477 data = container_of(dev, struct sysfs_ioapic_data, dev);
2478 entry = data->entry;
2480 spin_lock_irqsave(&ioapic_lock, flags);
2481 reg_00.raw = io_apic_read(dev->id, 0);
2482 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2483 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2484 io_apic_write(dev->id, 0, reg_00.raw);
2486 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2487 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2488 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2490 spin_unlock_irqrestore(&ioapic_lock, flags);
2495 static struct sysdev_class ioapic_sysdev_class = {
2496 set_kset_name("ioapic"),
2497 .suspend = ioapic_suspend,
2498 .resume = ioapic_resume,
2501 static int __init ioapic_init_sysfs(void)
2503 struct sys_device * dev;
2504 int i, size, error = 0;
2506 error = sysdev_class_register(&ioapic_sysdev_class);
2510 for (i = 0; i < nr_ioapics; i++ ) {
2511 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2512 * sizeof(struct IO_APIC_route_entry);
2513 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2514 if (!mp_ioapic_data[i]) {
2515 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2518 memset(mp_ioapic_data[i], 0, size);
2519 dev = &mp_ioapic_data[i]->dev;
2521 dev->cls = &ioapic_sysdev_class;
2522 error = sysdev_register(dev);
2524 kfree(mp_ioapic_data[i]);
2525 mp_ioapic_data[i] = NULL;
2526 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2534 device_initcall(ioapic_init_sysfs);
2536 /* --------------------------------------------------------------------------
2537 ACPI-based IOAPIC Configuration
2538 -------------------------------------------------------------------------- */
2542 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2544 union IO_APIC_reg_00 reg_00;
2545 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2547 unsigned long flags;
2551 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2552 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2553 * supports up to 16 on one shared APIC bus.
2555 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2556 * advantage of new APIC bus architecture.
2559 if (physids_empty(apic_id_map))
2560 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2562 spin_lock_irqsave(&ioapic_lock, flags);
2563 reg_00.raw = io_apic_read(ioapic, 0);
2564 spin_unlock_irqrestore(&ioapic_lock, flags);
2566 if (apic_id >= get_physical_broadcast()) {
2567 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2568 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2569 apic_id = reg_00.bits.ID;
2573 * Every APIC in a system must have a unique ID or we get lots of nice
2574 * 'stuck on smp_invalidate_needed IPI wait' messages.
2576 if (check_apicid_used(apic_id_map, apic_id)) {
2578 for (i = 0; i < get_physical_broadcast(); i++) {
2579 if (!check_apicid_used(apic_id_map, i))
2583 if (i == get_physical_broadcast())
2584 panic("Max apic_id exceeded!\n");
2586 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2587 "trying %d\n", ioapic, apic_id, i);
2592 tmp = apicid_to_cpu_present(apic_id);
2593 physids_or(apic_id_map, apic_id_map, tmp);
2595 if (reg_00.bits.ID != apic_id) {
2596 reg_00.bits.ID = apic_id;
2598 spin_lock_irqsave(&ioapic_lock, flags);
2599 io_apic_write(ioapic, 0, reg_00.raw);
2600 reg_00.raw = io_apic_read(ioapic, 0);
2601 spin_unlock_irqrestore(&ioapic_lock, flags);
2604 if (reg_00.bits.ID != apic_id) {
2605 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2610 apic_printk(APIC_VERBOSE, KERN_INFO
2611 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2617 int __init io_apic_get_version (int ioapic)
2619 union IO_APIC_reg_01 reg_01;
2620 unsigned long flags;
2622 spin_lock_irqsave(&ioapic_lock, flags);
2623 reg_01.raw = io_apic_read(ioapic, 1);
2624 spin_unlock_irqrestore(&ioapic_lock, flags);
2626 return reg_01.bits.version;
2630 int __init io_apic_get_redir_entries (int ioapic)
2632 union IO_APIC_reg_01 reg_01;
2633 unsigned long flags;
2635 spin_lock_irqsave(&ioapic_lock, flags);
2636 reg_01.raw = io_apic_read(ioapic, 1);
2637 spin_unlock_irqrestore(&ioapic_lock, flags);
2639 return reg_01.bits.entries;
2643 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2645 struct IO_APIC_route_entry entry;
2646 unsigned long flags;
2648 if (!IO_APIC_IRQ(irq)) {
2649 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2655 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2656 * Note that we mask (disable) IRQs now -- these get enabled when the
2657 * corresponding device driver registers for this IRQ.
2660 memset(&entry,0,sizeof(entry));
2662 entry.delivery_mode = INT_DELIVERY_MODE;
2663 entry.dest_mode = INT_DEST_MODE;
2664 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2665 entry.trigger = edge_level;
2666 entry.polarity = active_high_low;
2670 * IRQs < 16 are already in the irq_2_pin[] map
2673 add_pin_to_irq(irq, ioapic, pin);
2675 entry.vector = assign_irq_vector(irq);
2677 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2678 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2679 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2680 edge_level, active_high_low);
2682 ioapic_register_intr(irq, entry.vector, edge_level);
2684 if (!ioapic && (irq < 16))
2685 disable_8259A_irq(irq);
2687 spin_lock_irqsave(&ioapic_lock, flags);
2688 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2689 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2690 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2691 spin_unlock_irqrestore(&ioapic_lock, flags);
2696 #endif /* CONFIG_ACPI */