err.no Git - linux-2.6/blob - arch/blackfin/mach-common/ints-priority-sc.c

   1 /*
   2  * File:         arch/blackfin/mach-common/ints-priority-sc.c
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:      ?
   7  * Description:  Set up the interrupt priorities
   8  *
   9  * Modified:
  10  *               1996 Roman Zippel
  11  *               1999 D. Jeff Dionne <jeff@uclinux.org>
  12  *               2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
  13  *               2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
  14  *               2003 Metrowerks/Motorola
  15  *               2003 Bas Vermeulen <bas@buyways.nl>
  16  *               Copyright 2004-2007 Analog Devices Inc.
  17  *
  18  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2 of the License, or
  23  * (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, see the file COPYING, or write
  32  * to the Free Software Foundation, Inc.,
  33  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/kernel_stat.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/irq.h>
  40 #ifdef CONFIG_KGDB
  41 #include <linux/kgdb.h>
  42 #endif
  43 #include <asm/traps.h>
  44 #include <asm/blackfin.h>
  45 #include <asm/gpio.h>
  46 #include <asm/irq_handler.h>
  47
  48 #ifdef BF537_FAMILY
  49 # define BF537_GENERIC_ERROR_INT_DEMUX
  50 #else
  51 # undef BF537_GENERIC_ERROR_INT_DEMUX
  52 #endif
  53
  54 /*
  55  * NOTES:
  56  * - we have separated the physical Hardware interrupt from the
  57  * levels that the LINUX kernel sees (see the description in irq.h)
  58  * -
  59  */
  60
  61 /* Initialize this to an actual value to force it into the .data
  62  * section so that we know it is properly initialized at entry into
  63  * the kernel but before bss is initialized to zero (which is where
  64  * it would live otherwise).  The 0x1f magic represents the IRQs we
  65  * cannot actually mask out in hardware.
  66  */
  67 unsigned long irq_flags = 0x1f;
  68
  69 /* The number of spurious interrupts */
  70 atomic_t num_spurious;
  71
  72 struct ivgx {
  73         /* irq number for request_irq, available in mach-bf533/irq.h */
  74         unsigned int irqno;
  75         /* corresponding bit in the SIC_ISR register */
  76         unsigned int isrflag;
  77 } ivg_table[NR_PERI_INTS];
  78
  79 struct ivg_slice {
  80         /* position of first irq in ivg_table for given ivg */
  81         struct ivgx *ifirst;
  82         struct ivgx *istop;
  83 } ivg7_13[IVG13 - IVG7 + 1];
  84
  85 static void search_IAR(void);
  86
  87 /*
  88  * Search SIC_IAR and fill tables with the irqvalues
  89  * and their positions in the SIC_ISR register.
  90  */
  91 static void __init search_IAR(void)
  92 {
  93         unsigned ivg, irq_pos = 0;
  94         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  95                 int irqn;
  96
  97                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  98
  99                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
 100                         int iar_shift = (irqn & 7) * 4;
 101                                 if (ivg ==
 102                             (0xf &
 103 #ifndef CONFIG_BF52x
 104                              bfin_read32((unsigned long *)SIC_IAR0 +
 105                                          (irqn >> 3)) >> iar_shift)) {
 106 #else
 107                              bfin_read32((unsigned long *)SIC_IAR0 +
 108                                          ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
 109 #endif
 110                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
 111                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 112                                 ivg7_13[ivg].istop++;
 113                                 irq_pos++;
 114                         }
 115                 }
 116         }
 117 }
 118
 119 /*
 120  * This is for BF533 internal IRQs
 121  */
 122
 123 static void ack_noop(unsigned int irq)
 124 {
 125         /* Dummy function.  */
 126 }
 127
 128 static void bfin_core_mask_irq(unsigned int irq)
 129 {
 130         irq_flags &= ~(1 << irq);
 131         if (!irqs_disabled())
 132                 local_irq_enable();
 133 }
 134
 135 static void bfin_core_unmask_irq(unsigned int irq)
 136 {
 137         irq_flags |= 1 << irq;
 138         /*
 139          * If interrupts are enabled, IMASK must contain the same value
 140          * as irq_flags.  Make sure that invariant holds.  If interrupts
 141          * are currently disabled we need not do anything; one of the
 142          * callers will take care of setting IMASK to the proper value
 143          * when reenabling interrupts.
 144          * local_irq_enable just does "STI irq_flags", so it's exactly
 145          * what we need.
 146          */
 147         if (!irqs_disabled())
 148                 local_irq_enable();
 149         return;
 150 }
 151
 152 static void bfin_internal_mask_irq(unsigned int irq)
 153 {
 154 #ifdef CONFIG_BF53x
 155         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 156                              ~(1 << (irq - (IRQ_CORETMR + 1))));
 157 #else
 158         unsigned mask_bank, mask_bit;
 159         mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
 160         mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
 161         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 162                              ~(1 << mask_bit));
 163 #endif
 164         SSYNC();
 165 }
 166
 167 static void bfin_internal_unmask_irq(unsigned int irq)
 168 {
 169 #ifdef CONFIG_BF53x
 170         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 171                              (1 << (irq - (IRQ_CORETMR + 1))));
 172 #else
 173         unsigned mask_bank, mask_bit;
 174         mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
 175         mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
 176         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
 177                              (1 << mask_bit));
 178 #endif
 179         SSYNC();
 180 }
 181
 182 static struct irq_chip bfin_core_irqchip = {
 183         .ack = ack_noop,
 184         .mask = bfin_core_mask_irq,
 185         .unmask = bfin_core_unmask_irq,
 186 };
 187
 188 static struct irq_chip bfin_internal_irqchip = {
 189         .ack = ack_noop,
 190         .mask = bfin_internal_mask_irq,
 191         .unmask = bfin_internal_unmask_irq,
 192 };
 193
 194 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 195 static int error_int_mask;
 196
 197 static void bfin_generic_error_ack_irq(unsigned int irq)
 198 {
 199
 200 }
 201
 202 static void bfin_generic_error_mask_irq(unsigned int irq)
 203 {
 204         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 205
 206         if (!error_int_mask) {
 207                 local_irq_disable();
 208                 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 209                                      ~(1 <<
 210                                        (IRQ_GENERIC_ERROR -
 211                                         (IRQ_CORETMR + 1))));
 212                 SSYNC();
 213                 local_irq_enable();
 214         }
 215 }
 216
 217 static void bfin_generic_error_unmask_irq(unsigned int irq)
 218 {
 219         local_irq_disable();
 220         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
 221                              (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
 222         SSYNC();
 223         local_irq_enable();
 224
 225         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 226 }
 227
 228 static struct irq_chip bfin_generic_error_irqchip = {
 229         .ack = bfin_generic_error_ack_irq,
 230         .mask = bfin_generic_error_mask_irq,
 231         .unmask = bfin_generic_error_unmask_irq,
 232 };
 233
 234 static void bfin_demux_error_irq(unsigned int int_err_irq,
 235                                  struct irq_desc *intb_desc)
 236 {
 237         int irq = 0;
 238
 239         SSYNC();
 240
 241 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 242         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 243                 irq = IRQ_MAC_ERROR;
 244         else
 245 #endif
 246         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 247                 irq = IRQ_SPORT0_ERROR;
 248         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 249                 irq = IRQ_SPORT1_ERROR;
 250         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 251                 irq = IRQ_PPI_ERROR;
 252         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 253                 irq = IRQ_CAN_ERROR;
 254         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 255                 irq = IRQ_SPI_ERROR;
 256         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
 257                  (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
 258                 irq = IRQ_UART0_ERROR;
 259         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
 260                  (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
 261                 irq = IRQ_UART1_ERROR;
 262
 263         if (irq) {
 264                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
 265                         struct irq_desc *desc = irq_desc + irq;
 266                         desc->handle_irq(irq, desc);
 267                 } else {
 268
 269                         switch (irq) {
 270                         case IRQ_PPI_ERROR:
 271                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 272                                 break;
 273 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 274                         case IRQ_MAC_ERROR:
 275                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 276                                 break;
 277 #endif
 278                         case IRQ_SPORT0_ERROR:
 279                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 280                                 break;
 281
 282                         case IRQ_SPORT1_ERROR:
 283                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 284                                 break;
 285
 286                         case IRQ_CAN_ERROR:
 287                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 288                                 break;
 289
 290                         case IRQ_SPI_ERROR:
 291                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 292                                 break;
 293
 294                         default:
 295                                 break;
 296                         }
 297
 298                         pr_debug("IRQ %d:"
 299                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 300                                  irq);
 301                 }
 302         } else
 303                 printk(KERN_ERR
 304                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 305                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 306                        __FUNCTION__, __FILE__, __LINE__);
 307
 308 }
 309 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 310
 311 #if !defined(CONFIG_BF54x)
 312
 313 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
 314 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
 315
 316
 317 static void bfin_gpio_ack_irq(unsigned int irq)
 318 {
 319         u16 gpionr = irq - IRQ_PF0;
 320
 321         if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
 322                 set_gpio_data(gpionr, 0);
 323                 SSYNC();
 324         }
 325 }
 326
 327 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 328 {
 329         u16 gpionr = irq - IRQ_PF0;
 330
 331         if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
 332                 set_gpio_data(gpionr, 0);
 333                 SSYNC();
 334         }
 335
 336         set_gpio_maska(gpionr, 0);
 337         SSYNC();
 338 }
 339
 340 static void bfin_gpio_mask_irq(unsigned int irq)
 341 {
 342         set_gpio_maska(irq - IRQ_PF0, 0);
 343         SSYNC();
 344 }
 345
 346 static void bfin_gpio_unmask_irq(unsigned int irq)
 347 {
 348         set_gpio_maska(irq - IRQ_PF0, 1);
 349         SSYNC();
 350 }
 351
 352 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 353 {
 354         unsigned int ret;
 355         u16 gpionr = irq - IRQ_PF0;
 356         char buf[8];
 357
 358         if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
 359                 snprintf(buf, sizeof buf, "IRQ %d", irq);
 360                 ret = gpio_request(gpionr, buf);
 361                 if (ret)
 362                         return ret;
 363         }
 364
 365         gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
 366         bfin_gpio_unmask_irq(irq);
 367
 368         return ret;
 369 }
 370
 371 static void bfin_gpio_irq_shutdown(unsigned int irq)
 372 {
 373         bfin_gpio_mask_irq(irq);
 374         gpio_free(irq - IRQ_PF0);
 375         gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
 376 }
 377
 378 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 379 {
 380
 381         unsigned int ret;
 382         char buf[8];
 383         u16 gpionr = irq - IRQ_PF0;
 384
 385         if (type == IRQ_TYPE_PROBE) {
 386                 /* only probe unenabled GPIO interrupt lines */
 387                 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
 388                         return 0;
 389                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 390         }
 391
 392         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 393                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 394                 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
 395                         snprintf(buf, sizeof buf, "IRQ %d", irq);
 396                         ret = gpio_request(gpionr, buf);
 397                         if (ret)
 398                                 return ret;
 399                 }
 400
 401                 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
 402         } else {
 403                 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
 404                 return 0;
 405         }
 406
 407         set_gpio_dir(gpionr, 0);
 408         set_gpio_inen(gpionr, 1);
 409
 410         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 411                 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
 412                 set_gpio_edge(gpionr, 1);
 413         } else {
 414                 set_gpio_edge(gpionr, 0);
 415                 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
 416         }
 417
 418         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 419             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 420                 set_gpio_both(gpionr, 1);
 421         else
 422                 set_gpio_both(gpionr, 0);
 423
 424         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 425                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 426         else
 427                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 428
 429         SSYNC();
 430
 431         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 432                 set_irq_handler(irq, handle_edge_irq);
 433         else
 434                 set_irq_handler(irq, handle_level_irq);
 435
 436         return 0;
 437 }
 438
 439 static struct irq_chip bfin_gpio_irqchip = {
 440         .ack = bfin_gpio_ack_irq,
 441         .mask = bfin_gpio_mask_irq,
 442         .mask_ack = bfin_gpio_mask_ack_irq,
 443         .unmask = bfin_gpio_unmask_irq,
 444         .set_type = bfin_gpio_irq_type,
 445         .startup = bfin_gpio_irq_startup,
 446         .shutdown = bfin_gpio_irq_shutdown
 447 };
 448
 449 static void bfin_demux_gpio_irq(unsigned int intb_irq,
 450                                 struct irq_desc *intb_desc)
 451 {
 452         u16 i;
 453         struct irq_desc *desc;
 454
 455         for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
 456                 int irq = IRQ_PF0 + i;
 457                 int flag_d = get_gpiop_data(i);
 458                 int mask =
 459                     flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
 460
 461                 while (mask) {
 462                         if (mask & 1) {
 463                                 desc = irq_desc + irq;
 464                                 desc->handle_irq(irq, desc);
 465                         }
 466                         irq++;
 467                         mask >>= 1;
 468                 }
 469         }
 470 }
 471
 472 #else                           /* CONFIG_BF54x */
 473
 474 #define NR_PINT_SYS_IRQS        4
 475 #define NR_PINT_BITS            32
 476 #define NR_PINTS                160
 477 #define IRQ_NOT_AVAIL           0xFF
 478
 479 #define PINT_2_BANK(x)          ((x) >> 5)
 480 #define PINT_2_BIT(x)           ((x) & 0x1F)
 481 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 482
 483 static unsigned char irq2pint_lut[NR_PINTS];
 484 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 485
 486 struct pin_int_t {
 487         unsigned int mask_set;
 488         unsigned int mask_clear;
 489         unsigned int request;
 490         unsigned int assign;
 491         unsigned int edge_set;
 492         unsigned int edge_clear;
 493         unsigned int invert_set;
 494         unsigned int invert_clear;
 495         unsigned int pinstate;
 496         unsigned int latch;
 497 };
 498
 499 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 500         (struct pin_int_t *)PINT0_MASK_SET,
 501         (struct pin_int_t *)PINT1_MASK_SET,
 502         (struct pin_int_t *)PINT2_MASK_SET,
 503         (struct pin_int_t *)PINT3_MASK_SET,
 504 };
 505
 506 unsigned short get_irq_base(u8 bank, u8 bmap)
 507 {
 508
 509         u16 irq_base;
 510
 511         if (bank < 2) {         /*PA-PB */
 512                 irq_base = IRQ_PA0 + bmap * 16;
 513         } else {                /*PC-PJ */
 514                 irq_base = IRQ_PC0 + bmap * 16;
 515         }
 516
 517         return irq_base;
 518
 519 }
 520
 521         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 522 void init_pint_lut(void)
 523 {
 524         u16 bank, bit, irq_base, bit_pos;
 525         u32 pint_assign;
 526         u8 bmap;
 527
 528         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 529
 530         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 531
 532                 pint_assign = pint[bank]->assign;
 533
 534                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 535
 536                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 537
 538                         irq_base = get_irq_base(bank, bmap);
 539
 540                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 541                         bit_pos = bit + bank * NR_PINT_BITS;
 542
 543                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 544                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 545
 546                 }
 547
 548         }
 549
 550 }
 551
 552 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
 553
 554 static void bfin_gpio_ack_irq(unsigned int irq)
 555 {
 556         u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
 557
 558         pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
 559         SSYNC();
 560 }
 561
 562 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 563 {
 564         u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
 565         u32 pintbit = PINT_BIT(pint_val);
 566         u8 bank = PINT_2_BANK(pint_val);
 567
 568         pint[bank]->request = pintbit;
 569         pint[bank]->mask_clear = pintbit;
 570         SSYNC();
 571 }
 572
 573 static void bfin_gpio_mask_irq(unsigned int irq)
 574 {
 575         u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
 576
 577         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 578         SSYNC();
 579 }
 580
 581 static void bfin_gpio_unmask_irq(unsigned int irq)
 582 {
 583         u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
 584         u32 pintbit = PINT_BIT(pint_val);
 585         u8 bank = PINT_2_BANK(pint_val);
 586
 587         pint[bank]->request = pintbit;
 588         pint[bank]->mask_set = pintbit;
 589         SSYNC();
 590 }
 591
 592 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 593 {
 594         unsigned int ret;
 595         char buf[8];
 596         u16 gpionr = irq - IRQ_PA0;
 597         u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
 598
 599         if (pint_val == IRQ_NOT_AVAIL) {
 600                 printk(KERN_ERR
 601                 "GPIO IRQ %d :Not in PINT Assign table "
 602                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 603                 return -ENODEV;
 604         }
 605
 606         if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
 607                 snprintf(buf, sizeof buf, "IRQ %d", irq);
 608                 ret = gpio_request(gpionr, buf);
 609                 if (ret)
 610                         return ret;
 611         }
 612
 613         gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
 614         bfin_gpio_unmask_irq(irq);
 615
 616         return ret;
 617 }
 618
 619 static void bfin_gpio_irq_shutdown(unsigned int irq)
 620 {
 621         bfin_gpio_mask_irq(irq);
 622         gpio_free(irq - IRQ_PA0);
 623         gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
 624 }
 625
 626 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 627 {
 628
 629         unsigned int ret;
 630         char buf[8];
 631         u16 gpionr = irq - IRQ_PA0;
 632         u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
 633         u32 pintbit = PINT_BIT(pint_val);
 634         u8 bank = PINT_2_BANK(pint_val);
 635
 636         if (pint_val == IRQ_NOT_AVAIL)
 637                 return -ENODEV;
 638
 639         if (type == IRQ_TYPE_PROBE) {
 640                 /* only probe unenabled GPIO interrupt lines */
 641                 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
 642                         return 0;
 643                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 644         }
 645
 646         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 647                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 648                 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
 649                         snprintf(buf, sizeof buf, "IRQ %d", irq);
 650                         ret = gpio_request(gpionr, buf);
 651                         if (ret)
 652                                 return ret;
 653                 }
 654
 655                 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
 656         } else {
 657                 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
 658                 return 0;
 659         }
 660
 661         gpio_direction_input(gpionr);
 662
 663         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 664                 pint[bank]->edge_set = pintbit;
 665         } else {
 666                 pint[bank]->edge_clear = pintbit;
 667         }
 668
 669         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 670                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 671         else
 672                 pint[bank]->invert_set = pintbit;       /* high or rising edge denoted by zero */
 673
 674         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 675                 pint[bank]->invert_set = pintbit;
 676         else
 677                 pint[bank]->invert_set = pintbit;
 678
 679         SSYNC();
 680
 681         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 682                 set_irq_handler(irq, handle_edge_irq);
 683         else
 684                 set_irq_handler(irq, handle_level_irq);
 685
 686         return 0;
 687 }
 688
 689 static struct irq_chip bfin_gpio_irqchip = {
 690         .ack = bfin_gpio_ack_irq,
 691         .mask = bfin_gpio_mask_irq,
 692         .mask_ack = bfin_gpio_mask_ack_irq,
 693         .unmask = bfin_gpio_unmask_irq,
 694         .set_type = bfin_gpio_irq_type,
 695         .startup = bfin_gpio_irq_startup,
 696         .shutdown = bfin_gpio_irq_shutdown
 697 };
 698
 699 static void bfin_demux_gpio_irq(unsigned int intb_irq,
 700                                 struct irq_desc *intb_desc)
 701 {
 702         u8 bank, pint_val;
 703         u32 request, irq;
 704         struct irq_desc *desc;
 705
 706         switch (intb_irq) {
 707         case IRQ_PINT0:
 708                 bank = 0;
 709                 break;
 710         case IRQ_PINT2:
 711                 bank = 2;
 712                 break;
 713         case IRQ_PINT3:
 714                 bank = 3;
 715                 break;
 716         case IRQ_PINT1:
 717                 bank = 1;
 718                 break;
 719         default:
 720                 return;
 721         }
 722
 723         pint_val = bank * NR_PINT_BITS;
 724
 725         request = pint[bank]->request;
 726
 727         while (request) {
 728                 if (request & 1) {
 729                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
 730                         desc = irq_desc + irq;
 731                         desc->handle_irq(irq, desc);
 732                 }
 733                 pint_val++;
 734                 request >>= 1;
 735         }
 736
 737 }
 738 #endif
 739
 740 void __init init_exception_vectors(void)
 741 {
 742         SSYNC();
 743
 744         /* cannot program in software:
 745          * evt0 - emulation (jtag)
 746          * evt1 - reset
 747          */
 748         bfin_write_EVT2(evt_nmi);
 749         bfin_write_EVT3(trap);
 750         bfin_write_EVT5(evt_ivhw);
 751         bfin_write_EVT6(evt_timer);
 752         bfin_write_EVT7(evt_evt7);
 753         bfin_write_EVT8(evt_evt8);
 754         bfin_write_EVT9(evt_evt9);
 755         bfin_write_EVT10(evt_evt10);
 756         bfin_write_EVT11(evt_evt11);
 757         bfin_write_EVT12(evt_evt12);
 758         bfin_write_EVT13(evt_evt13);
 759         bfin_write_EVT14(evt14_softirq);
 760         bfin_write_EVT15(evt_system_call);
 761         CSYNC();
 762 }
 763
 764 /*
 765  * This function should be called during kernel startup to initialize
 766  * the BFin IRQ handling routines.
 767  */
 768 int __init init_arch_irq(void)
 769 {
 770         int irq;
 771         unsigned long ilat = 0;
 772         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 773 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
 774         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
 775         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
 776         bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
 777         bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
 778 # ifdef CONFIG_BF54x
 779         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 780         bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
 781 # endif
 782 #else
 783         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 784         bfin_write_SIC_IWR(IWR_ENABLE_ALL);
 785 #endif
 786         SSYNC();
 787
 788         local_irq_disable();
 789
 790 #ifdef CONFIG_BF54x
 791 # ifdef CONFIG_PINTx_REASSIGN
 792         pint[0]->assign = CONFIG_PINT0_ASSIGN;
 793         pint[1]->assign = CONFIG_PINT1_ASSIGN;
 794         pint[2]->assign = CONFIG_PINT2_ASSIGN;
 795         pint[3]->assign = CONFIG_PINT3_ASSIGN;
 796 # endif
 797         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 798         init_pint_lut();
 799 #endif
 800
 801         for (irq = 0; irq <= SYS_IRQS; irq++) {
 802                 if (irq <= IRQ_CORETMR)
 803                         set_irq_chip(irq, &bfin_core_irqchip);
 804                 else
 805                         set_irq_chip(irq, &bfin_internal_irqchip);
 806 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 807                 if (irq != IRQ_GENERIC_ERROR) {
 808 #endif
 809
 810                         switch (irq) {
 811 #if defined(CONFIG_BF53x)
 812                         case IRQ_PROG_INTA:
 813                                 set_irq_chained_handler(irq,
 814                                                         bfin_demux_gpio_irq);
 815                                 break;
 816 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 817                         case IRQ_MAC_RX:
 818                                 set_irq_chained_handler(irq,
 819                                                         bfin_demux_gpio_irq);
 820                                 break;
 821 # endif
 822 #elif defined(CONFIG_BF54x)
 823                         case IRQ_PINT0:
 824                                 set_irq_chained_handler(irq,
 825                                                         bfin_demux_gpio_irq);
 826                                 break;
 827                         case IRQ_PINT1:
 828                                 set_irq_chained_handler(irq,
 829                                                         bfin_demux_gpio_irq);
 830                                 break;
 831                         case IRQ_PINT2:
 832                                 set_irq_chained_handler(irq,
 833                                                         bfin_demux_gpio_irq);
 834                                 break;
 835                         case IRQ_PINT3:
 836                                 set_irq_chained_handler(irq,
 837                                                         bfin_demux_gpio_irq);
 838                                 break;
 839 #elif defined(CONFIG_BF52x)
 840                         case IRQ_PORTF_INTA:
 841                                 set_irq_chained_handler(irq,
 842                                                         bfin_demux_gpio_irq);
 843                                 break;
 844                         case IRQ_PORTG_INTA:
 845                                 set_irq_chained_handler(irq,
 846                                                         bfin_demux_gpio_irq);
 847                                 break;
 848                         case IRQ_PORTH_INTA:
 849                                 set_irq_chained_handler(irq,
 850                                                         bfin_demux_gpio_irq);
 851                                 break;
 852 #endif
 853                         default:
 854                                 set_irq_handler(irq, handle_simple_irq);
 855                                 break;
 856                         }
 857
 858 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 859                 } else {
 860                         set_irq_handler(irq, bfin_demux_error_irq);
 861                 }
 862 #endif
 863         }
 864 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 865         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
 866                 set_irq_chip(irq, &bfin_generic_error_irqchip);
 867                 set_irq_handler(irq, handle_level_irq);
 868         }
 869 #endif
 870
 871 #ifndef CONFIG_BF54x
 872         for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
 873 #else
 874         for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
 875 #endif
 876                 set_irq_chip(irq, &bfin_gpio_irqchip);
 877                 /* if configured as edge, then will be changed to do_edge_IRQ */
 878                 set_irq_handler(irq, handle_level_irq);
 879         }
 880
 881         bfin_write_IMASK(0);
 882         CSYNC();
 883         ilat = bfin_read_ILAT();
 884         CSYNC();
 885         bfin_write_ILAT(ilat);
 886         CSYNC();
 887
 888         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
 889         /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
 890          * local_irq_enable()
 891          */
 892         program_IAR();
 893         /* Therefore it's better to setup IARs before interrupts enabled */
 894         search_IAR();
 895
 896         /* Enable interrupts IVG7-15 */
 897         irq_flags = irq_flags | IMASK_IVG15 |
 898             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
 899             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 900
 901         return 0;
 902 }
 903
 904 #ifdef CONFIG_DO_IRQ_L1
 905 __attribute__((l1_text))
 906 #endif
 907 void do_irq(int vec, struct pt_regs *fp)
 908 {
 909         if (vec == EVT_IVTMR_P) {
 910                 vec = IRQ_CORETMR;
 911         } else {
 912                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
 913                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
 914 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
 915                 unsigned long sic_status[3];
 916
 917                 SSYNC();
 918                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
 919                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
 920 #ifdef CONFIG_BF54x
 921                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
 922 #endif
 923                 for (;; ivg++) {
 924                         if (ivg >= ivg_stop) {
 925                                 atomic_inc(&num_spurious);
 926                                 return;
 927                         }
 928                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
 929                                 break;
 930                 }
 931 #else
 932                 unsigned long sic_status;
 933                 SSYNC();
 934                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
 935
 936                 for (;; ivg++) {
 937                         if (ivg >= ivg_stop) {
 938                                 atomic_inc(&num_spurious);
 939                                 return;
 940                         } else if (sic_status & ivg->isrflag)
 941                                 break;
 942                 }
 943 #endif
 944                 vec = ivg->irqno;
 945         }
 946         asm_do_IRQ(vec, fp);
 947
 948 #ifdef CONFIG_KGDB
 949         kgdb_process_breakpoint();
 950 #endif
 951 }