2 * File: arch/blackfin/mach-common/cplbmgtr.S
4 * Author: LG Soft India
7 * Description: CPLB replacement routine for CPLB mismatch
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 /* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
31 * is_data_miss==2 => Mark as Dirty, write to the clean data page
32 * is_data_miss==1 => Replace a data CPLB.
33 * is_data_miss==0 => Replace an instruction CPLB.
36 * CPLB_RELOADED => Successfully updated CPLB table.
37 * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.
38 * This indicates that the CPLBs in the configuration
39 * tablei are badly configured, as this should never
41 * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the
42 * exception, is not covered by any of the CPLBs in
43 * the configuration table. The application is
44 * presumably misbehaving.
45 * CPLB_PROT_VIOL => The address being accessed, that triggered the
46 * exception, was not a first-write to a clean Write
47 * Back Data page, and so presumably is a genuine
48 * violation of the page's protection attributes.
49 * The application is misbehaving.
52 #include <linux/linkage.h>
53 #include <asm/blackfin.h>
56 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
68 IF CC JUMP .Ldcplb_write;
71 IF !CC JUMP .Ldcplb_miss_compare;
73 /* ICPLB Miss Exception. We need to choose one of the
74 * currently-installed CPLBs, and replace it with one
75 * from the configuration table.
78 P4.L = LO(ICPLB_FAULT_ADDR);
79 P4.H = HI(ICPLB_FAULT_ADDR);
82 P5.L = _page_size_table;
83 P5.H = _page_size_table;
85 P0.L = LO(ICPLB_DATA0);
86 P0.H = HI(ICPLB_DATA0);
87 R4 = [P4]; /* Get faulting address*/
88 R6 = 64; /* Advance past the fault address, which*/
89 R6 = R6 + R4; /* we'll use if we find a match*/
90 R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/
95 R1 = [P0-0x100]; /* Address for this CPLB */
97 R0 = [P0++]; /* Info for this CPLB*/
98 CC = BITTST(R0,0); /* Is the CPLB valid?*/
99 IF !CC JUMP .Lnomatch; /* Skip it, if not.*/
100 CC = R4 < R1(IU); /* If fault address less than page start*/
101 IF CC JUMP .Lnomatch; /* then skip this one.*/
102 R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
104 P1 = P5 + (P1<<2); /* index into page-size table*/
105 R2 = [P1]; /* Get the page size*/
106 R1 = R1 + R2; /* and add to page start, to get page end*/
107 CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
108 IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
109 IF !CC JUMP .Lisearch_done;
113 CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
114 IF !CC JUMP .Lisearch;
117 I0 = R4; /* Fault address we'll search for*/
119 /* set up pointers */
120 P0.L = LO(ICPLB_DATA0);
121 P0.H = HI(ICPLB_DATA0);
123 /* The replacement procedure for ICPLBs */
125 P4.L = LO(IMEM_CONTROL);
126 P4.H = HI(IMEM_CONTROL);
129 R5 = [P4]; /* Control Register*/
130 BITCLR(R5,ENICPLB_P);
132 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
138 R1 = -1; /* end point comparison */
139 R3 = 16; /* counter */
141 /* Search through CPLBs for first non-locked entry */
142 /* Overwrite it by moving everyone else up by 1 */
147 IF CC JUMP .Lall_locked;
148 CC = BITTST(R0, 0); /* an invalid entry is good */
149 IF !CC JUMP .Lifound_victim;
150 CC = BITTST(R0,1); /* but a locked entry isn't */
151 IF CC JUMP .Licheck_lock;
154 #ifdef CONFIG_CPLB_INFO
158 P3.L = _ipdt_swapcount_table;
159 P3.H = _ipdt_swapcount_table;
162 R2 = [P2]; /* address from config table */
166 IF CC JUMP .Licount_done;
168 IF !CC JUMP .Licount;
176 LSETUP(.Lis_move,.Lie_move) LC0;
184 /* We've made space in the ICPLB table, so that ICPLB15
185 * is now free to be overwritten. Next, we have to determine
186 * which CPLB we need to install, from the configuration
187 * table. This is a matter of getting the start-of-page
188 * addresses and page-lengths from the config table, and
189 * determining whether the fault address falls within that
195 #ifdef CONFIG_CPLB_INFO
196 P3.L = _ipdt_swapcount_table;
197 P3.H = _ipdt_swapcount_table;
200 P0.L = _page_size_table;
201 P0.H = _page_size_table;
203 /* Retrieve our fault address (which may have been advanced
204 * because the faulting instruction crossed a page boundary).
209 /* An extraction pattern, to get the page-size bits from
210 * the CPLB data entry. Bits 16-17, so two bits at posn 16.
214 .Linext: R4 = [P2++]; /* address from config table */
215 R2 = [P2++]; /* data from config table */
216 #ifdef CONFIG_CPLB_INFO
220 CC = R4 == -1; /* End of config table*/
221 IF CC JUMP .Lno_page_in_table;
223 /* See if failed address > start address */
227 /* extract page size (17:16)*/
228 R3 = EXTRACT(R2, R1.L) (Z);
230 /* add page size to addr to get range */
233 P5 = P0 + (P5 << 2); /* scaled, for int access*/
237 /* See if failed address < (start address + page size) */
241 /* We've found a CPLB in the config table that covers
242 * the faulting address, so install this CPLB into the
243 * last entry of the table.
246 P1.L = LO(ICPLB_DATA15); /* ICPLB_DATA15 */
247 P1.H = HI(ICPLB_DATA15);
250 #ifdef CONFIG_CPLB_INFO
256 /* P4 points to IMEM_CONTROL, and R5 contains its old
257 * value, after we disabled ICPLBS. Re-enable them.
260 BITSET(R5,ENICPLB_P);
262 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
268 ( R7:4,P5:3 ) = [SP++];
274 R0 = CPLB_NO_ADDR_MATCH;
278 R0 = CPLB_NO_UNLOCKED;
285 /* Make sure we turn protection/cache back on, even in the failing case */
286 BITSET(R5,ENICPLB_P);
288 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
294 ( R7:4,P5:3 ) = [SP++];
299 /* if a DCPLB is marked as write-back (CPLB_WT==0), and
300 * it is clean (CPLB_DIRTY==0), then a write to the
301 * CPLB's page triggers a protection violation. We have to
302 * mark the CPLB as dirty, to indicate that there are
303 * pending writes associated with the CPLB.
306 P4.L = LO(DCPLB_STATUS);
307 P4.H = HI(DCPLB_STATUS);
308 P3.L = LO(DCPLB_DATA0);
309 P3.H = HI(DCPLB_DATA0);
312 /* A protection violation can be caused by more than just writes
313 * to a clean WB page, so we have to ensure that:
315 * - to a clean WB page
316 * - and is allowed in the mode the access occurred.
319 CC = BITTST(R5, 16); /* ensure it was a write*/
320 IF !CC JUMP .Lprot_violation;
322 /* to check the rest, we have to retrieve the DCPLB.*/
324 /* The low half of DCPLB_STATUS is a bit mask*/
326 R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
327 R3 = 30; /* so we can use this to determine the offset*/
329 R2 = R2.L (Z); /* into the DCPLB table.*/
333 R3 = [P3]; /* Retrieve the CPLB*/
335 /* Now we can check whether it's a clean WB page*/
337 CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
338 IF CC JUMP .Lprot_violation;
339 CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
340 IF CC JUMP .Lprot_violation;
342 /* Check whether the write is allowed in the mode that was active.*/
344 R2 = 1<<3; /* checking write in user mode*/
345 CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
347 R2 <<= R5; /* if was super, check write in super mode*/
350 IF CC JUMP .Lprot_violation;
352 /* It's a genuine write-to-clean-page.*/
354 BITSET(R3, 7); /* mark as dirty*/
355 [P3] = R3; /* and write back.*/
358 ( R7:4,P5:3 ) = [SP++];
362 .Ldcplb_miss_compare:
364 /* Data CPLB Miss event. We need to choose a CPLB to
365 * evict, and then locate a new CPLB to install from the
366 * config table, that covers the faulting address.
369 P1.L = LO(DCPLB_DATA15);
370 P1.H = HI(DCPLB_DATA15);
372 P4.L = LO(DCPLB_FAULT_ADDR);
373 P4.H = HI(DCPLB_FAULT_ADDR);
377 /* The replacement procedure for DCPLBs*/
379 R6 = R1; /* Save for later*/
381 /* Turn off CPLBs while we work.*/
382 P4.L = LO(DMEM_CONTROL);
383 P4.H = HI(DMEM_CONTROL);
385 BITCLR(R5,ENDCPLB_P);
387 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
393 /* Start looking for a CPLB to evict. Our order of preference
394 * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
398 I1.L = LO(DCPLB_DATA0);
399 I1.H = HI(DCPLB_DATA0);
402 I2.L = _dcplb_preference;
403 I2.H = _dcplb_preference;
404 LSETUP(.Lsdsearch1, .Ledsearch1) LC0 = P1;
406 R0 = [I2++]; /* Get the bits we're interested in*/
407 P0 = I1; /* Go back to start of table*/
408 LSETUP (.Lsdsearch2, .Ledsearch2) LC1 = P2;
410 R1 = [P0++]; /* Fetch each installed CPLB in turn*/
411 R2 = R1 & R0; /* and test for interesting bits.*/
412 CC = R2 == 0; /* If none are set, it'll do.*/
413 IF !CC JUMP .Lskip_stack_check;
415 R2 = [P0 - 0x104]; /* R2 - PageStart */
416 P3.L = _page_size_table; /* retrieve end address */
417 P3.H = _page_size_table; /* retrieve end address */
418 R3 = 0x1002; /* 16th - position, 2 bits -length */
420 nop; /* Anomaly 05000209 */
422 R7 = EXTRACT(R1,R3.l);
423 R7 = R7 << 2; /* Page size index offset */
426 R7 = [P3]; /* page size in bytes */
428 R7 = R2 + R7; /* R7 - PageEnd */
429 R4 = SP; /* Test SP is in range */
431 CC = R7 < R4; /* if PageEnd < SP */
432 IF CC JUMP .Ldfound_victim;
433 R3 = 0x284; /* stack length from start of trap till
435 * 20 stack locations for future modifications
438 CC = R4 < R2; /* if SP + stacklen < PageStart */
439 IF CC JUMP .Ldfound_victim;
445 /* If we got here, we didn't find a DCPLB we considered
446 * replacable, which means all of them were locked.
452 #ifdef CONFIG_CPLB_INFO
456 P3.L = _dpdt_swapcount_table;
457 P3.H = _dpdt_swapcount_table;
464 IF CC JUMP .Ldicount_done;
466 IF !CC JUMP .Ldicount;
473 /* Clean down the hardware loops*/
478 /* There's a suitable victim in [P0-4] (because we've
484 /* [P0-4] is a suitable victim CPLB, so we want to
485 * overwrite it by moving all the following CPLBs
486 * one space closer to the start.
489 R1.L = LO(DCPLB_DATA16); /* DCPLB_DATA15 + 4 */
490 R1.H = HI(DCPLB_DATA16);
493 /* If the victim happens to be in DCPLB15,
494 * we don't need to move anything.
498 IF CC JUMP .Lde_moved;
502 LSETUP(.Lds_move, .Lde_move) LC0=P1;
504 R0 = [P0++]; /* move data */
506 R0 = [P0-0x104] /* move address */
507 .Lde_move: [P0-0x108] = R0;
509 /* We've now made space in DCPLB15 for the new CPLB to be
510 * installed. The next stage is to locate a CPLB in the
511 * config table that covers the faulting address.
515 R0 = I0; /* Our faulting address */
519 #ifdef CONFIG_CPLB_INFO
520 P3.L = _dpdt_swapcount_table;
521 P3.H = _dpdt_swapcount_table;
525 P1.L = _page_size_table;
526 P1.H = _page_size_table;
528 /* An extraction pattern, to retrieve bits 17:16.*/
531 .Ldnext: R4 = [P2++]; /* address */
532 R2 = [P2++]; /* data */
533 #ifdef CONFIG_CPLB_INFO
538 IF CC JUMP .Lno_page_in_table;
540 /* See if failed address > start address */
544 /* extract page size (17:16)*/
545 R3 = EXTRACT(R2, R1.L) (Z);
547 /* add page size to addr to get range */
554 /* See if failed address < (start address + page size) */
558 /* We've found the CPLB that should be installed, so
559 * write it into CPLB15, masking off any caching bits
563 P1.L = LO(DCPLB_DATA15);
564 P1.H = HI(DCPLB_DATA15);
566 /* If the DCPLB has cache bits set, but caching hasn't
567 * been enabled, then we want to mask off the cache-in-L1
568 * bit before installing. Moreover, if caching is off, we
569 * also want to ensure that the DCPLB has WT mode set, rather
570 * than WB, since WB pages still trigger first-write exceptions
571 * even when not caching is off, and the page isn't marked as
572 * cachable. Finally, we could mark the page as clean, not dirty,
573 * but we choose to leave that decision to the user; if the user
574 * chooses to have a CPLB pre-defined as dirty, then they always
575 * pay the cost of flushing during eviction, but don't pay the
576 * cost of first-write exceptions to mark the page as dirty.
579 #ifdef CONFIG_BFIN_WT
580 BITSET(R6, 14); /* Set WT*/
585 #ifdef CONFIG_CPLB_INFO
591 /* We've installed the CPLB, so re-enable CPLBs. P4
592 * points to DMEM_CONTROL, and R5 is the value we
593 * last wrote to it, when we were disabling CPLBs.
596 BITSET(R5,ENDCPLB_P);
603 ( R7:4,P5:3 ) = [SP++];
611 .byte4 0x00000400; /* 1K */
612 .byte4 0x00001000; /* 4K */
613 .byte4 0x00100000; /* 1M */
614 .byte4 0x00400000; /* 4M */
618 .byte4 0x00000001; /* valid bit */
619 .byte4 0x00000002; /* lock bit */