2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: Startup code for Blackfin BF548
10 * Copyright 2004-2007 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <linux/init.h>
32 #include <asm/blackfin.h>
33 #ifdef CONFIG_BFIN_KERNEL_CLOCK
34 #include <asm/mach-common/clocks.h>
35 #include <asm/mach/mem_init.h>
38 .extern _bf53x_relocate_l1_mem
42 ENTRY(_mach_early_start)
44 ENDPROC(_mach_early_start)
49 #ifdef CONFIG_BFIN_KERNEL_CLOCK
50 ENTRY(_start_dma_code)
52 /* Enable PHY CLK buffer output */
69 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
70 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
71 * - [7] = output delay (add 200ps of delay to mem signals)
72 * - [6] = input delay (add 200ps of input delay to mem signals)
73 * - [5] = PDWN : 1=All Clocks off
74 * - [3] = STOPCK : 1=Core Clock off
75 * - [1] = PLL_OFF : 1=Disable Power to PLL
76 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
77 * all other bits set to zero
80 p0.h = hi(PLL_LOCKCNT);
81 p0.l = lo(PLL_LOCKCNT);
86 #if defined(CONFIG_BF54x)
87 P2.H = hi(EBIU_RSTCTL);
88 P2.L = lo(EBIU_RSTCTL);
92 P2.H = hi(EBIU_SDGCTL);
93 P2.L = lo(EBIU_SDGCTL);
99 #if defined(CONFIG_BF54x)
103 if !CC JUMP .LSRR_MODE;
106 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
107 r0 = r0 << 9; /* Shift it over, */
108 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
110 r1 = PLL_BYPASS; /* Bypass the PLL? */
111 r1 = r1 << 8; /* Shift it over */
112 r0 = r1 | r0; /* add them all together */
115 p0.l = lo(PLL_CTL); /* Load the address */
116 cli r2; /* Disable interrupts */
118 w[p0] = r0.l; /* Set the value */
119 idle; /* Wait for the PLL to stablize */
120 sti r2; /* Enable interrupts */
127 if ! CC jump .Lcheck_again;
129 /* Configure SCLK & CCLK Dividers */
130 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
136 #if defined(CONFIG_BF54x)
137 P2.H = hi(EBIU_RSTCTL);
138 P2.L = lo(EBIU_RSTCTL);
141 if CC jump .Lskipddrrst;
148 p0.l = lo(EBIU_DDRCTL0);
149 p0.h = hi(EBIU_DDRCTL0);
150 r0.l = lo(mem_DDRCTL0);
151 r0.h = hi(mem_DDRCTL0);
155 p0.l = lo(EBIU_DDRCTL1);
156 p0.h = hi(EBIU_DDRCTL1);
157 r0.l = lo(mem_DDRCTL1);
158 r0.h = hi(mem_DDRCTL1);
162 p0.l = lo(EBIU_DDRCTL2);
163 p0.h = hi(EBIU_DDRCTL2);
164 r0.l = lo(mem_DDRCTL2);
165 r0.h = hi(mem_DDRCTL2);
169 p0.l = lo(EBIU_SDRRC);
170 p0.h = hi(EBIU_SDRRC);
175 p0.l = LO(EBIU_SDBCTL);
176 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
181 P2.H = hi(EBIU_SDGCTL);
182 P2.L = lo(EBIU_SDGCTL);
185 p0.h = hi(EBIU_SDSTAT);
186 p0.l = lo(EBIU_SDSTAT);
196 R0.L = lo(mem_SDGCTL);
197 R0.H = hi(mem_SDGCTL);
206 r0.l = lo(IWR_ENABLE_ALL);
207 r0.h = hi(IWR_ENABLE_ALL);
212 ENDPROC(_start_dma_code)
213 #endif /* CONFIG_BFIN_KERNEL_CLOCK */