2 * File: arch/blackfin/mach-bf537/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: Startup code for Blackfin BF537
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <linux/init.h>
32 #include <asm/blackfin.h>
33 #include <asm/trace.h>
35 #ifdef CONFIG_BFIN_KERNEL_CLOCK
36 #include <asm/mach-common/clocks.h>
37 #include <asm/mach/mem_init.h>
42 .extern _bf53x_relocate_l1_mem
44 #define INITIAL_STACK 0xFFB01000
49 /* R0: argument of command line string, passed from uboot, save it */
51 /* Enable Cycle Counter and Nesting Of Interrupts */
52 #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
55 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
60 /* Clear Out All the data and pointer Registers */
82 /* Clear Out All the DAG Registers */
98 trace_buffer_init(p0,r0);
102 /* Turn off the icache */
103 p0.l = LO(IMEM_CONTROL);
104 p0.h = HI(IMEM_CONTROL);
111 /* Turn off the dcache */
112 p0.l = LO(DMEM_CONTROL);
113 p0.h = HI(DMEM_CONTROL);
120 /* Initialise General-Purpose I/O Modules on BF537 */
121 p0.h = hi(BFIN_PORT_MUX);
122 p0.l = lo(BFIN_PORT_MUX);
123 R0 = (PGDE_UART | PFTE_UART)(Z);
124 W[P0] = R0.L; /* Enable both UARTS */
127 /* Enable peripheral function of PORTF for UART0 and UART1 */
128 p0.h = hi(PORTF_FER);
129 p0.l = lo(PORTF_FER);
134 #if !defined(CONFIG_BF534)
135 p0.h = hi(EMAC_SYSTAT);
136 p0.l = lo(EMAC_SYSTAT);
137 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
143 /* Initialise UART - when booting from u-boot, the UART is not disabled
144 * so if we dont initalize here, our serial console gets hosed */
145 p0.h = hi(BFIN_UART_LCR);
146 p0.l = lo(BFIN_UART_LCR);
148 w[p0] = r0.L; /* To enable DLL writes */
151 p0.h = hi(BFIN_UART_DLL);
152 p0.l = lo(BFIN_UART_DLL);
157 p0.h = hi(BFIN_UART_DLH);
158 p0.l = lo(BFIN_UART_DLH);
163 p0.h = hi(BFIN_UART_GCTL);
164 p0.l = lo(BFIN_UART_GCTL);
166 w[p0] = r0.L; /* To enable UART clock */
169 /* Initialize stack pointer */
170 sp.l = lo(INITIAL_STACK);
171 sp.h = hi(INITIAL_STACK);
175 #ifdef CONFIG_EARLY_PRINTK
177 call _init_early_exception_vectors;
181 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
182 call _bf53x_relocate_l1_mem;
183 #ifdef CONFIG_BFIN_KERNEL_CLOCK
184 call _start_dma_code;
187 /* Code for initializing Async memory banks */
189 p2.h = hi(EBIU_AMBCTL1);
190 p2.l = lo(EBIU_AMBCTL1);
191 r0.h = hi(AMBCTL1VAL);
192 r0.l = lo(AMBCTL1VAL);
196 p2.h = hi(EBIU_AMBCTL0);
197 p2.l = lo(EBIU_AMBCTL0);
198 r0.h = hi(AMBCTL0VAL);
199 r0.l = lo(AMBCTL0VAL);
203 p2.h = hi(EBIU_AMGCTL);
204 p2.l = lo(EBIU_AMGCTL);
209 /* This section keeps the processor in supervisor mode
210 * during kernel boot. Switches to user mode at end of boot.
211 * See page 3-9 of Hardware Reference manual for documentation.
214 /* EVT15 = _real_start */
246 #ifdef CONFIG_BFIN_KERNEL_CLOCK
247 ENTRY(_start_dma_code)
249 /* Enable PHY CLK buffer output */
266 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
267 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
268 * - [7] = output delay (add 200ps of delay to mem signals)
269 * - [6] = input delay (add 200ps of input delay to mem signals)
270 * - [5] = PDWN : 1=All Clocks off
271 * - [3] = STOPCK : 1=Core Clock off
272 * - [1] = PLL_OFF : 1=Disable Power to PLL
273 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
274 * all other bits set to zero
277 p0.h = hi(PLL_LOCKCNT);
278 p0.l = lo(PLL_LOCKCNT);
283 P2.H = hi(EBIU_SDGCTL);
284 P2.L = lo(EBIU_SDGCTL);
290 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
291 r0 = r0 << 9; /* Shift it over, */
292 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
294 r1 = PLL_BYPASS; /* Bypass the PLL? */
295 r1 = r1 << 8; /* Shift it over */
296 r0 = r1 | r0; /* add them all together */
299 p0.l = lo(PLL_CTL); /* Load the address */
300 cli r2; /* Disable interrupts */
302 w[p0] = r0.l; /* Set the value */
303 idle; /* Wait for the PLL to stablize */
304 sti r2; /* Enable interrupts */
311 if ! CC jump .Lcheck_again;
313 /* Configure SCLK & CCLK Dividers */
314 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
320 p0.l = lo(EBIU_SDRRC);
321 p0.h = hi(EBIU_SDRRC);
326 P2.H = hi(EBIU_SDGCTL);
327 P2.L = lo(EBIU_SDGCTL);
330 p0.h = hi(EBIU_SDSTAT);
331 p0.l = lo(EBIU_SDSTAT);
341 R0.L = lo(mem_SDGCTL);
342 R0.H = hi(mem_SDGCTL);
350 r0.l = lo(IWR_ENABLE_ALL);
351 r0.h = hi(IWR_ENABLE_ALL);
356 ENDPROC(_start_dma_code)
357 #endif /* CONFIG_BFIN_KERNEL_CLOCK */