2 * File: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: bf533 startup file
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <linux/init.h>
32 #include <asm/blackfin.h>
33 #include <asm/trace.h>
34 #if CONFIG_BFIN_KERNEL_CLOCK
35 #include <asm/mach-common/clocks.h>
36 #include <asm/mach/mem_init.h>
38 #if CONFIG_DEBUG_KERNEL_START
39 #include <asm/mach-common/def_LPBlackfin.h>
47 .extern _bf53x_relocate_l1_mem
49 #define INITIAL_STACK 0xFFB01000
54 /* R0: argument of command line string, passed from uboot, save it */
56 /* Set the SYSCFG register:
57 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
63 /* Clear Out All the data and pointer Registers */
85 /* Clear Out All the DAG Registers */
101 trace_buffer_init(p0,r0);
105 #if CONFIG_DEBUG_KERNEL_START
108 * Set up a temporary Event Vector Table, so if something bad happens before
109 * the kernel is fully started, it doesn't vector off into the bootloaders
116 P2.l = debug_kernel_start_trap;
117 P2.h = debug_kernel_start_trap;
125 .Lfill_temp_vector_table:
126 [P0++] = P2; /* Core Event Vector Table */
128 if !CC JUMP .Lfill_temp_vector_table
135 p0.h = hi(FIO_MASKA_C);
136 p0.l = lo(FIO_MASKA_C);
138 w[p0] = r0.L; /* Disable all interrupts */
141 p0.h = hi(FIO_MASKB_C);
142 p0.l = lo(FIO_MASKB_C);
144 w[p0] = r0.L; /* Disable all interrupts */
147 /* Turn off the icache */
148 p0.l = LO(IMEM_CONTROL);
149 p0.h = HI(IMEM_CONTROL);
154 /* Anomaly 05000125 */
165 /* Turn off the dcache */
166 p0.l = LO(DMEM_CONTROL);
167 p0.h = HI(DMEM_CONTROL);
172 /* Anomaly 05000125 */
183 /* Initialise UART - when booting from u-boot, the UART is not disabled
184 * so if we dont initalize here, our serial console gets hosed */
188 w[p0] = r0.L; /* To enable DLL writes */
203 p0.h = hi(UART_GCTL);
204 p0.l = lo(UART_GCTL);
206 w[p0] = r0.L; /* To enable UART clock */
209 /* Initialize stack pointer */
210 sp.l = lo(INITIAL_STACK);
211 sp.h = hi(INITIAL_STACK);
215 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
216 call _bf53x_relocate_l1_mem;
217 #if CONFIG_BFIN_KERNEL_CLOCK
218 call _start_dma_code;
221 /* Code for initializing Async memory banks */
223 p2.h = hi(EBIU_AMBCTL1);
224 p2.l = lo(EBIU_AMBCTL1);
225 r0.h = hi(AMBCTL1VAL);
226 r0.l = lo(AMBCTL1VAL);
230 p2.h = hi(EBIU_AMBCTL0);
231 p2.l = lo(EBIU_AMBCTL0);
232 r0.h = hi(AMBCTL0VAL);
233 r0.l = lo(AMBCTL0VAL);
237 p2.h = hi(EBIU_AMGCTL);
238 p2.l = lo(EBIU_AMGCTL);
243 /* This section keeps the processor in supervisor mode
244 * during kernel boot. Switches to user mode at end of boot.
245 * See page 3-9 of Hardware Reference manual for documentation.
248 /* EVT15 = _real_start */
282 w[p0] = r0; /* watchdog off for now */
285 /* Code update for BSS size == 0
286 * Zero out the bss region.
295 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
299 /* In case there is a NULL pointer reference
300 * Zero out region before stext
310 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
314 /* pass the uboot arguments to the global value command line */
333 * load the current thread pointer and stack
335 r1.l = _init_thread_union;
336 r1.h = _init_thread_union;
344 jump.l _start_kernel;
350 #if CONFIG_BFIN_KERNEL_CLOCK
351 ENTRY(_start_dma_code)
361 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
362 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
363 * - [7] = output delay (add 200ps of delay to mem signals)
364 * - [6] = input delay (add 200ps of input delay to mem signals)
365 * - [5] = PDWN : 1=All Clocks off
366 * - [3] = STOPCK : 1=Core Clock off
367 * - [1] = PLL_OFF : 1=Disable Power to PLL
368 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
369 * all other bits set to zero
372 p0.h = hi(PLL_LOCKCNT);
373 p0.l = lo(PLL_LOCKCNT);
378 P2.H = hi(EBIU_SDGCTL);
379 P2.L = lo(EBIU_SDGCTL);
385 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
386 r0 = r0 << 9; /* Shift it over, */
387 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
389 r1 = PLL_BYPASS; /* Bypass the PLL? */
390 r1 = r1 << 8; /* Shift it over */
391 r0 = r1 | r0; /* add them all together */
394 p0.l = lo(PLL_CTL); /* Load the address */
395 cli r2; /* Disable interrupts */
397 w[p0] = r0.l; /* Set the value */
398 idle; /* Wait for the PLL to stablize */
399 sti r2; /* Enable interrupts */
406 if ! CC jump .Lcheck_again;
408 /* Configure SCLK & CCLK Dividers */
409 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
415 p0.l = lo(EBIU_SDRRC);
416 p0.h = hi(EBIU_SDRRC);
421 p0.l = LO(EBIU_SDBCTL);
422 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
427 P2.H = hi(EBIU_SDGCTL);
428 P2.L = lo(EBIU_SDGCTL);
431 p0.h = hi(EBIU_SDSTAT);
432 p0.l = lo(EBIU_SDSTAT);
442 R0.L = lo(mem_SDGCTL);
443 R0.H = hi(mem_SDGCTL);
451 r0.l = lo(IWR_ENABLE_ALL);
452 r0.h = hi(IWR_ENABLE_ALL);
457 ENDPROC(_start_dma_code)
458 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
461 /* No more interrupts to be handled*/
465 #if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
468 r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
473 r0.l = (1 << CONFIG_ENET_FLASH_PIN);
476 p0.h = hi(FIO_FLAG_C);
477 p0.l = lo(FIO_FLAG_C);
478 r0.l = (1 << CONFIG_ENET_FLASH_PIN);
482 /* Clear the IMASK register */
488 /* Clear the ILAT register */
495 /* make sure SYSCR is set to use BMODE */
502 /* issue a system soft reset */
509 /* clear system soft reset */
514 /* issue core reset */
520 #if CONFIG_DEBUG_KERNEL_START
521 debug_kernel_start_trap:
522 /* Set up a temp stack in L1 - SDRAM might not be working */
523 P0.L = lo(L1_DATA_A_START + 0x100);
524 P0.H = hi(L1_DATA_A_START + 0x100);
527 /* Make sure the Clocks are the way I think they should be */
528 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
529 r0 = r0 << 9; /* Shift it over, */
530 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
532 r1 = PLL_BYPASS; /* Bypass the PLL? */
533 r1 = r1 << 8; /* Shift it over */
534 r0 = r1 | r0; /* add them all together */
537 p0.l = lo(PLL_CTL); /* Load the address */
538 cli r2; /* Disable interrupts */
540 w[p0] = r0.l; /* Set the value */
541 idle; /* Wait for the PLL to stablize */
542 sti r2; /* Enable interrupts */
549 if ! CC jump .Lcheck_again1;
551 /* Configure SCLK & CCLK Dividers */
552 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
558 /* Make sure UART is enabled - you can never be sure */
561 * Setup for console. Argument comes from the menuconfig
564 #ifdef CONFIG_BAUD_9600
565 #define CONSOLE_BAUD_RATE 9600
566 #elif CONFIG_BAUD_19200
567 #define CONSOLE_BAUD_RATE 19200
568 #elif CONFIG_BAUD_38400
569 #define CONSOLE_BAUD_RATE 38400
570 #elif CONFIG_BAUD_57600
571 #define CONSOLE_BAUD_RATE 57600
572 #elif CONFIG_BAUD_115200
573 #define CONSOLE_BAUD_RATE 115200
576 p0.h = hi(UART_GCTL);
577 p0.l = lo(UART_GCTL);
579 w[p0] = r0.L; /* To Turn off UART clocks */
585 w[p0] = r0.L; /* To enable DLL writes */
588 R1 = (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_SCLK_DIV) / (CONSOLE_BAUD_RATE * 16));
603 p0.h = hi(UART_GCTL);
604 p0.l = lo(UART_GCTL);
606 w[p0] = r0.L; /* To enable UART clock */
612 w[p0] = r0.L; /* To Turn on UART */
615 p0.h = hi(UART_GCTL);
616 p0.l = lo(UART_GCTL);
618 w[p0] = r0.L; /* To Turn on UART Clocks */
694 .Ldebug_kernel_start_trap_done:
695 JUMP .Ldebug_kernel_start_trap_done;
699 R5 = ':'; /* one past 9 */
708 if CC JUMP .Ldump_reg1;
714 if !CC JUMP .Ldump_reg1;
718 if !CC JUMP .Ldump_reg2
724 if !CC JUMP .Lwait_char;
728 #endif /* CONFIG_DEBUG_KERNEL_START */
733 * Set up the usable of RAM stuff. Size of RAM is determined then
734 * an initial stack set up at the end.