2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/module.h>
25 #include <asm/blackfin.h>
27 #include <asm/cplbinit.h>
29 u_long icplb_table[MAX_CPLBS + 1];
30 u_long dcplb_table[MAX_CPLBS + 1];
32 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
33 # define PDT_ATTR __attribute__((l1_data))
38 u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
39 u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
41 #ifdef CONFIG_CPLB_INFO
42 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
43 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
47 struct cplb_tab init_i;
48 struct cplb_tab init_d;
49 struct cplb_tab switch_i;
50 struct cplb_tab switch_d;
53 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
54 static struct cplb_desc cplb_data[] = {
59 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
62 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
67 .name = "Zero Pointer Guard Page",
70 .start = L1_CODE_START,
71 .end = L1_CODE_START + L1_CODE_LENGTH,
73 .attr = INITIAL_T | SWITCH_T | I_CPLB,
77 .name = "L1 I-Memory",
80 .start = L1_DATA_A_START,
81 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
83 .attr = INITIAL_T | SWITCH_T | D_CPLB,
86 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
91 .name = "L1 D-Memory",
95 .end = 0, /* dynamic */
97 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
98 .i_conf = SDRAM_IGENERIC,
99 .d_conf = SDRAM_DGENERIC,
101 .name = "Kernel Memory",
104 .start = 0, /* dynamic */
105 .end = 0, /* dynamic */
107 .attr = INITIAL_T | SWITCH_T | D_CPLB,
108 .i_conf = SDRAM_IGENERIC,
109 .d_conf = SDRAM_DNON_CHBL,
111 .name = "uClinux MTD Memory",
114 .start = 0, /* dynamic */
115 .end = 0, /* dynamic */
117 .attr = INITIAL_T | SWITCH_T | D_CPLB,
118 .d_conf = SDRAM_DNON_CHBL,
120 .name = "Uncached DMA Zone",
123 .start = 0, /* dynamic */
124 .end = 0, /* dynamic */
126 .attr = SWITCH_T | D_CPLB,
127 .i_conf = 0, /* dynamic */
128 .d_conf = 0, /* dynamic */
130 .name = "Reserved Memory",
133 .start = ASYNC_BANK0_BASE,
134 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
136 .attr = SWITCH_T | D_CPLB,
137 .d_conf = SDRAM_EBIU,
139 .name = "Asynchronous Memory Banks",
144 .end = L2_START + L2_LENGTH,
146 .attr = SWITCH_T | I_CPLB | D_CPLB,
156 .start = BOOT_ROM_START,
157 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
159 .attr = SWITCH_T | I_CPLB | D_CPLB,
160 .i_conf = SDRAM_IGENERIC,
161 .d_conf = SDRAM_DGENERIC,
163 .name = "On-Chip BootROM",
167 static u16 __init lock_kernel_check(u32 start, u32 end)
169 if ((end <= (u32) _end && end >= (u32)_stext) ||
170 (start <= (u32) _end && start >= (u32)_stext))
175 static unsigned short __init
176 fill_cplbtab(struct cplb_tab *table,
177 unsigned long start, unsigned long end,
178 unsigned long block_size, unsigned long cplb_data)
182 switch (block_size) {
198 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
200 while ((start < end) && (table->pos < table->size)) {
202 table->tab[table->pos++] = start;
204 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
205 table->tab[table->pos++] =
206 cplb_data | CPLB_LOCK | CPLB_DIRTY;
208 table->tab[table->pos++] = cplb_data;
215 static unsigned short __init
216 close_cplbtab(struct cplb_tab *table)
219 while (table->pos < table->size) {
221 table->tab[table->pos++] = 0;
222 table->tab[table->pos++] = 0; /* !CPLB_VALID */
227 /* helper function */
228 static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
230 if (cplb_data[i].psize) {
235 cplb_data[i].i_conf);
237 #if defined(CONFIG_BFIN_ICACHE)
238 if (ANOMALY_05000263 && i == SDRAM_KERN) {
243 cplb_data[i].i_conf);
251 cplb_data[i].i_conf);
256 cplb_data[i].i_conf);
257 fill_cplbtab(t, a_end,
260 cplb_data[i].i_conf);
265 static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
267 if (cplb_data[i].psize) {
272 cplb_data[i].d_conf);
277 cplb_data[i].d_conf);
278 fill_cplbtab(t, a_start,
280 cplb_data[i].d_conf);
281 fill_cplbtab(t, a_end,
284 cplb_data[i].d_conf);
288 void __init generate_cpl_tables(void)
292 u32 a_start, a_end, as, ae, as_1m;
294 struct cplb_tab *t_i = NULL;
295 struct cplb_tab *t_d = NULL;
298 cplb.init_i.size = MAX_CPLBS;
299 cplb.init_d.size = MAX_CPLBS;
300 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
301 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
305 cplb.switch_i.pos = 0;
306 cplb.switch_d.pos = 0;
308 cplb.init_i.tab = icplb_table;
309 cplb.init_d.tab = dcplb_table;
310 cplb.switch_i.tab = ipdt_table;
311 cplb.switch_d.tab = dpdt_table;
313 cplb_data[SDRAM_KERN].end = memory_end;
315 #ifdef CONFIG_MTD_UCLINUX
316 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
317 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
318 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
319 # if defined(CONFIG_ROMFS_FS)
320 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
323 * The ROMFS_FS size is often not multiple of 1MB.
324 * This can cause multiple CPLB sets covering the same memory area.
325 * This will then cause multiple CPLB hit exceptions.
326 * Workaround: We ensure a contiguous memory area by extending the kernel
327 * memory section over the mtd section.
328 * For ROMFS_FS memory must be covered with ICPLBs anyways.
329 * So there is no difference between kernel and mtd memory setup.
332 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
333 cplb_data[SDRAM_RAM_MTD].valid = 0;
337 cplb_data[SDRAM_RAM_MTD].valid = 0;
340 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
341 cplb_data[SDRAM_DMAZ].end = _ramend;
343 cplb_data[RES_MEM].start = _ramend;
344 cplb_data[RES_MEM].end = physical_mem_end;
346 if (reserved_mem_dcache_on)
347 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
349 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
351 if (reserved_mem_icache_on)
352 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
354 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
356 for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
357 if (!cplb_data[i].valid)
360 as_1m = cplb_data[i].start % SIZE_1M;
362 /* We need to make sure all sections are properly 1M aligned
363 * However between Kernel Memory and the Kernel mtd section, depending on the
364 * rootfs size, there can be overlapping memory areas.
367 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
368 #ifdef CONFIG_MTD_UCLINUX
369 if (i == SDRAM_RAM_MTD) {
370 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
371 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
373 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
376 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
377 cplb_data[i].name, cplb_data[i].start);
380 as = cplb_data[i].start % SIZE_4M;
381 ae = cplb_data[i].end % SIZE_4M;
384 a_start = cplb_data[i].start + (SIZE_4M - (as));
386 a_start = cplb_data[i].start;
388 a_end = cplb_data[i].end - ae;
390 for (j = INITIAL_T; j <= SWITCH_T; j++) {
394 if (cplb_data[i].attr & INITIAL_T) {
402 if (cplb_data[i].attr & SWITCH_T) {
403 t_i = &cplb.switch_i;
404 t_d = &cplb.switch_d;
416 if (cplb_data[i].attr & I_CPLB)
417 __fill_code_cplbtab(t_i, i, a_start, a_end);
419 if (cplb_data[i].attr & D_CPLB)
420 __fill_data_cplbtab(t_d, i, a_start, a_end);
426 close_cplbtab(&cplb.init_i);
427 close_cplbtab(&cplb.init_d);
429 cplb.init_i.tab[cplb.init_i.pos] = -1;
430 cplb.init_d.tab[cplb.init_d.pos] = -1;
431 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
432 cplb.switch_d.tab[cplb.switch_d.pos] = -1;