2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 Not Supported Yet - Work in progress - BF561 Processor Support.
171 default BF_REV_0_1 if BF527
172 default BF_REV_0_2 if BF537
173 default BF_REV_0_3 if BF533
174 default BF_REV_0_0 if BF549
178 depends on (BF52x || BF54x)
182 depends on (BF52x || BF54x)
186 depends on (BF537 || BF536 || BF534)
190 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
194 depends on (BF561 || BF533 || BF532 || BF531)
198 depends on (BF561 || BF533 || BF532 || BF531)
210 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
215 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
220 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
223 config MEM_GENERIC_BOARD
225 depends on GENERIC_BOARD
228 config MEM_MT48LC64M4A2FB_7E
230 depends on (BFIN533_STAMP)
233 config MEM_MT48LC16M16A2TG_75
235 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
236 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
240 config MEM_MT48LC32M8A2_75
242 depends on (BFIN537_STAMP || PNAV10)
245 config MEM_MT48LC8M32B2B5_7
247 depends on (BFIN561_BLUETECHNIX_CM)
250 config MEM_MT48LC32M16A2TG_75
252 depends on (BFIN527_EZKIT || BFIN532_IP0X)
255 source "arch/blackfin/mach-bf527/Kconfig"
256 source "arch/blackfin/mach-bf533/Kconfig"
257 source "arch/blackfin/mach-bf561/Kconfig"
258 source "arch/blackfin/mach-bf537/Kconfig"
259 source "arch/blackfin/mach-bf548/Kconfig"
261 menu "Board customizations"
264 bool "Default bootloader kernel arguments"
267 string "Initial kernel command string"
268 depends on CMDLINE_BOOL
269 default "console=ttyBF0,57600"
271 If you don't have a boot loader capable of passing a command line string
272 to the kernel, you may specify one here. As a minimum, you should specify
273 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
276 hex "Kernel load address for booting"
278 range 0x1000 0x20000000
280 This option allows you to set the load address of the kernel.
281 This can be useful if you are on a board which has a small amount
282 of memory or you wish to reserve some memory at the beginning of
285 Note that you need to keep this value above 4k (0x1000) as this
286 memory region is used to capture NULL pointer references as well
287 as some core kernel functions.
289 comment "Clock/PLL Setup"
292 int "Frequency of the crystal on the board in Hz"
293 default "11059200" if BFIN533_STAMP
294 default "27000000" if BFIN533_EZKIT
295 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
296 default "30000000" if BFIN561_EZKIT
297 default "24576000" if PNAV10
298 default "10000000" if BFIN532_IP0X
300 The frequency of CLKIN crystal oscillator on the board in Hz.
301 Warning: This value should match the crystal on the board. Otherwise,
302 peripherals won't work properly.
304 config BFIN_KERNEL_CLOCK
305 bool "Re-program Clocks while Kernel boots?"
308 This option decides if kernel clocks are re-programed from the
309 bootloader settings. If the clocks are not set, the SDRAM settings
310 are also not changed, and the Bootloader does 100% of the hardware
315 depends on BFIN_KERNEL_CLOCK
320 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
323 If this is set the clock will be divided by 2, before it goes to the PLL.
327 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
329 default "22" if BFIN533_EZKIT
330 default "45" if BFIN533_STAMP
331 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
332 default "22" if BFIN533_BLUETECHNIX_CM
333 default "20" if BFIN537_BLUETECHNIX_CM
334 default "20" if BFIN561_BLUETECHNIX_CM
335 default "20" if BFIN561_EZKIT
336 default "16" if H8606_HVSISTEMAS
338 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
339 PLL Frequency = (Crystal Frequency) * (this setting)
342 prompt "Core Clock Divider"
343 depends on BFIN_KERNEL_CLOCK
346 This sets the frequency of the core. It can be 1, 2, 4 or 8
347 Core Frequency = (PLL frequency) / (this setting)
363 int "System Clock Divider"
364 depends on BFIN_KERNEL_CLOCK
368 This sets the frequency of the system clock (including SDRAM or DDR).
369 This can be between 1 and 15
370 System Clock = (PLL frequency) / (this setting)
373 int "Max SDRAM Memory Size in MBytes"
377 This is the max memory size that the kernel will create CPLB
378 tables for. Your system will not be able to handle any more.
381 prompt "DDR SDRAM Chip Type"
382 depends on BFIN_KERNEL_CLOCK
384 default MEM_MT46V32M16_5B
386 config MEM_MT46V32M16_6T
389 config MEM_MT46V32M16_5B
394 # Max & Min Speeds for various Chips
398 default 600000000 if BF522
399 default 400000000 if BF523
400 default 400000000 if BF524
401 default 600000000 if BF525
402 default 400000000 if BF526
403 default 600000000 if BF527
404 default 400000000 if BF531
405 default 400000000 if BF532
406 default 750000000 if BF533
407 default 500000000 if BF534
408 default 400000000 if BF536
409 default 600000000 if BF537
410 default 533333333 if BF538
411 default 533333333 if BF539
412 default 600000000 if BF542
413 default 533333333 if BF544
414 default 600000000 if BF547
415 default 600000000 if BF548
416 default 533333333 if BF549
417 default 600000000 if BF561
431 comment "Kernel Timer/Scheduler"
433 source kernel/Kconfig.hz
439 config GENERIC_CLOCKEVENTS
440 bool "Generic clock events"
441 depends on GENERIC_TIME
444 config CYCLES_CLOCKSOURCE
445 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
446 depends on EXPERIMENTAL
447 depends on GENERIC_CLOCKEVENTS
448 depends on !BFIN_SCRATCH_REG_CYCLES
451 If you say Y here, you will enable support for using the 'cycles'
452 registers as a clock source. Doing so means you will be unable to
453 safely write to the 'cycles' register during runtime. You will
454 still be able to read it (such as for performance monitoring), but
455 writing the registers will most likely crash the kernel.
457 source kernel/time/Kconfig
459 comment "Memory Setup"
464 prompt "Blackfin Exception Scratch Register"
465 default BFIN_SCRATCH_REG_RETN
467 Select the resource to reserve for the Exception handler:
468 - RETN: Non-Maskable Interrupt (NMI)
469 - RETE: Exception Return (JTAG/ICE)
470 - CYCLES: Performance counter
472 If you are unsure, please select "RETN".
474 config BFIN_SCRATCH_REG_RETN
477 Use the RETN register in the Blackfin exception handler
478 as a stack scratch register. This means you cannot
479 safely use NMI on the Blackfin while running Linux, but
480 you can debug the system with a JTAG ICE and use the
481 CYCLES performance registers.
483 If you are unsure, please select "RETN".
485 config BFIN_SCRATCH_REG_RETE
488 Use the RETE register in the Blackfin exception handler
489 as a stack scratch register. This means you cannot
490 safely use a JTAG ICE while debugging a Blackfin board,
491 but you can safely use the CYCLES performance registers
494 If you are unsure, please select "RETN".
496 config BFIN_SCRATCH_REG_CYCLES
499 Use the CYCLES register in the Blackfin exception handler
500 as a stack scratch register. This means you cannot
501 safely use the CYCLES performance registers on a Blackfin
502 board at anytime, but you can debug the system with a JTAG
505 If you are unsure, please select "RETN".
512 menu "Blackfin Kernel Optimizations"
514 comment "Memory Optimizations"
517 bool "Locate interrupt entry code in L1 Memory"
520 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
521 into L1 instruction memory. (less latency)
523 config EXCPT_IRQ_SYSC_L1
524 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
527 If enabled, the entire ASM lowlevel exception and interrupt entry code
528 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
532 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
535 If enabled, the frequently called do_irq dispatcher function is linked
536 into L1 instruction memory. (less latency)
538 config CORE_TIMER_IRQ_L1
539 bool "Locate frequently called timer_interrupt() function in L1 Memory"
542 If enabled, the frequently called timer_interrupt() function is linked
543 into L1 instruction memory. (less latency)
546 bool "Locate frequently idle function in L1 Memory"
549 If enabled, the frequently called idle function is linked
550 into L1 instruction memory. (less latency)
553 bool "Locate kernel schedule function in L1 Memory"
556 If enabled, the frequently called kernel schedule is linked
557 into L1 instruction memory. (less latency)
559 config ARITHMETIC_OPS_L1
560 bool "Locate kernel owned arithmetic functions in L1 Memory"
563 If enabled, arithmetic functions are linked
564 into L1 instruction memory. (less latency)
567 bool "Locate access_ok function in L1 Memory"
570 If enabled, the access_ok function is linked
571 into L1 instruction memory. (less latency)
574 bool "Locate memset function in L1 Memory"
577 If enabled, the memset function is linked
578 into L1 instruction memory. (less latency)
581 bool "Locate memcpy function in L1 Memory"
584 If enabled, the memcpy function is linked
585 into L1 instruction memory. (less latency)
587 config SYS_BFIN_SPINLOCK_L1
588 bool "Locate sys_bfin_spinlock function in L1 Memory"
591 If enabled, sys_bfin_spinlock function is linked
592 into L1 instruction memory. (less latency)
594 config IP_CHECKSUM_L1
595 bool "Locate IP Checksum function in L1 Memory"
598 If enabled, the IP Checksum function is linked
599 into L1 instruction memory. (less latency)
601 config CACHELINE_ALIGNED_L1
602 bool "Locate cacheline_aligned data to L1 Data Memory"
607 If enabled, cacheline_anligned data is linked
608 into L1 data memory. (less latency)
610 config SYSCALL_TAB_L1
611 bool "Locate Syscall Table L1 Data Memory"
615 If enabled, the Syscall LUT is linked
616 into L1 data memory. (less latency)
618 config CPLB_SWITCH_TAB_L1
619 bool "Locate CPLB Switch Tables L1 Data Memory"
623 If enabled, the CPLB Switch Tables are linked
624 into L1 data memory. (less latency)
630 prompt "Kernel executes from"
632 Choose the memory type that the kernel will be running in.
637 The kernel will be resident in RAM when running.
642 The kernel will be resident in FLASH/ROM when running.
649 tristate "Enable Blackfin General Purpose Timers API"
652 Enable support for the General Purpose Timers API. If you
655 To compile this driver as a module, choose M here: the module
656 will be called gptimers.ko.
659 bool "Enable DMA Support"
660 depends on (BF52x || BF53x || BF561 || BF54x)
663 DMA driver for BF5xx.
666 prompt "Uncached SDRAM region"
667 default DMA_UNCACHED_1M
668 depends on BFIN_DMA_5XX
669 config DMA_UNCACHED_4M
670 bool "Enable 4M DMA region"
671 config DMA_UNCACHED_2M
672 bool "Enable 2M DMA region"
673 config DMA_UNCACHED_1M
674 bool "Enable 1M DMA region"
675 config DMA_UNCACHED_NONE
676 bool "Disable DMA region"
680 comment "Cache Support"
685 config BFIN_DCACHE_BANKA
686 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
687 depends on BFIN_DCACHE && !BF531
689 config BFIN_ICACHE_LOCK
690 bool "Enable Instruction Cache Locking"
694 depends on BFIN_DCACHE
700 Cached data will be written back to SDRAM only when needed.
701 This can give a nice increase in performance, but beware of
702 broken drivers that do not properly invalidate/flush their
705 Write Through Policy:
706 Cached data will always be written back to SDRAM when the
707 cache is updated. This is a completely safe setting, but
708 performance is worse than Write Back.
710 If you are unsure of the options and you want to be safe,
711 then go with Write Through.
717 Cached data will be written back to SDRAM only when needed.
718 This can give a nice increase in performance, but beware of
719 broken drivers that do not properly invalidate/flush their
722 Write Through Policy:
723 Cached data will always be written back to SDRAM when the
724 cache is updated. This is a completely safe setting, but
725 performance is worse than Write Back.
727 If you are unsure of the options and you want to be safe,
728 then go with Write Through.
733 int "Set the max L1 SRAM pieces"
736 Set the max memory pieces for the L1 SRAM allocation algorithm.
737 Min value is 16. Max value is 1024.
741 bool "Enable the memory protection unit (EXPERIMENTAL)"
744 Use the processor's MPU to protect applications from accessing
745 memory they do not own. This comes at a performance penalty
746 and is recommended only for debugging.
748 comment "Asynchonous Memory Configuration"
750 menu "EBIU_AMGCTL Global Control"
756 bool "DMA has priority over core for ext. accesses"
761 bool "Bank 0 16 bit packing enable"
766 bool "Bank 1 16 bit packing enable"
771 bool "Bank 2 16 bit packing enable"
776 bool "Bank 3 16 bit packing enable"
780 prompt"Enable Asynchonous Memory Banks"
784 bool "Disable All Banks"
790 bool "Enable Bank 0 & 1"
792 config C_AMBEN_B0_B1_B2
793 bool "Enable Bank 0 & 1 & 2"
796 bool "Enable All Banks"
800 menu "EBIU_AMBCTL Control"
808 default 0x5558 if BF54x
819 config EBIU_MBSCTLVAL
820 hex "EBIU Bank Select Control Register"
825 hex "Flash Memory Mode Control Register"
830 hex "Flash Memory Bank Control Register"
835 #############################################################################
836 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
843 source "drivers/pci/Kconfig"
846 bool "Support for hot-pluggable device"
848 Say Y here if you want to plug devices into your computer while
849 the system is running, and be able to use them quickly. In many
850 cases, the devices can likewise be unplugged at any time too.
852 One well known example of this is PCMCIA- or PC-cards, credit-card
853 size devices such as network cards, modems or hard drives which are
854 plugged into slots found on all modern laptop computers. Another
855 example, used on modern desktops as well as laptops, is USB.
857 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
858 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
859 Then your kernel will automatically call out to a user mode "policy
860 agent" (/sbin/hotplug) to load modules and set up software needed
861 to use devices as you hotplug them.
863 source "drivers/pcmcia/Kconfig"
865 source "drivers/pci/hotplug/Kconfig"
869 menu "Executable file formats"
871 source "fs/Kconfig.binfmt"
875 menu "Power management options"
876 source "kernel/power/Kconfig"
878 config ARCH_SUSPEND_POSSIBLE
883 prompt "Default Power Saving Mode"
885 default PM_BFIN_SLEEP_DEEPER
886 config PM_BFIN_SLEEP_DEEPER
889 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
890 power dissipation by disabling the clock to the processor core (CCLK).
891 Furthermore, Standby sets the internal power supply voltage (VDDINT)
892 to 0.85 V to provide the greatest power savings, while preserving the
894 The PLL and system clock (SCLK) continue to operate at a very low
895 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
896 the SDRAM is put into Self Refresh Mode. Typically an external event
897 such as GPIO interrupt or RTC activity wakes up the processor.
898 Various Peripherals such as UART, SPORT, PPI may not function as
899 normal during Sleep Deeper, due to the reduced SCLK frequency.
900 When in the sleep mode, system DMA access to L1 memory is not supported.
905 Sleep Mode (High Power Savings) - The sleep mode reduces power
906 dissipation by disabling the clock to the processor core (CCLK).
907 The PLL and system clock (SCLK), however, continue to operate in
908 this mode. Typically an external event or RTC activity will wake
909 up the processor. When in the sleep mode,
910 system DMA access to L1 memory is not supported.
913 config PM_WAKEUP_BY_GPIO
914 bool "Cause Wakeup Event by GPIO"
916 config PM_WAKEUP_GPIO_NUMBER
917 int "Wakeup GPIO number"
919 depends on PM_WAKEUP_BY_GPIO
920 default 2 if BFIN537_STAMP
923 prompt "GPIO Polarity"
924 depends on PM_WAKEUP_BY_GPIO
925 default PM_WAKEUP_GPIO_POLAR_H
926 config PM_WAKEUP_GPIO_POLAR_H
928 config PM_WAKEUP_GPIO_POLAR_L
930 config PM_WAKEUP_GPIO_POLAR_EDGE_F
932 config PM_WAKEUP_GPIO_POLAR_EDGE_R
934 config PM_WAKEUP_GPIO_POLAR_EDGE_B
940 menu "CPU Frequency scaling"
942 source "drivers/cpufreq/Kconfig"
945 bool "CPU Voltage scaling"
946 depends on EXPERIMENTAL
950 Say Y here if you want CPU voltage scaling according to the CPU frequency.
951 This option violates the PLL BYPASS recommendation in the Blackfin Processor
952 manuals. There is a theoretical risk that during VDDINT transitions
959 source "drivers/Kconfig"
963 source "arch/blackfin/Kconfig.debug"
965 source "security/Kconfig"
967 source "crypto/Kconfig"