2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 Not Supported Yet - Work in progress - BF561 Processor Support.
171 default BF_REV_0_1 if BF527
172 default BF_REV_0_2 if BF537
173 default BF_REV_0_3 if BF533
174 default BF_REV_0_0 if BF549
178 depends on (BF52x || BF54x)
182 depends on (BF52x || BF54x)
186 depends on (BF537 || BF536 || BF534)
190 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
194 depends on (BF561 || BF533 || BF532 || BF531)
198 depends on (BF561 || BF533 || BF532 || BF531)
210 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
215 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
220 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
223 config MEM_GENERIC_BOARD
225 depends on GENERIC_BOARD
228 config MEM_MT48LC64M4A2FB_7E
230 depends on (BFIN533_STAMP)
233 config MEM_MT48LC16M16A2TG_75
235 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
236 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
240 config MEM_MT48LC32M8A2_75
242 depends on (BFIN537_STAMP || PNAV10)
245 config MEM_MT48LC8M32B2B5_7
247 depends on (BFIN561_BLUETECHNIX_CM)
250 config MEM_MT48LC32M16A2TG_75
252 depends on (BFIN527_EZKIT || BFIN532_IP0X)
255 source "arch/blackfin/mach-bf527/Kconfig"
256 source "arch/blackfin/mach-bf533/Kconfig"
257 source "arch/blackfin/mach-bf561/Kconfig"
258 source "arch/blackfin/mach-bf537/Kconfig"
259 source "arch/blackfin/mach-bf548/Kconfig"
261 menu "Board customizations"
264 bool "Default bootloader kernel arguments"
267 string "Initial kernel command string"
268 depends on CMDLINE_BOOL
269 default "console=ttyBF0,57600"
271 If you don't have a boot loader capable of passing a command line string
272 to the kernel, you may specify one here. As a minimum, you should specify
273 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
276 hex "Kernel load address for booting"
278 range 0x1000 0x20000000
280 This option allows you to set the load address of the kernel.
281 This can be useful if you are on a board which has a small amount
282 of memory or you wish to reserve some memory at the beginning of
285 Note that you need to keep this value above 4k (0x1000) as this
286 memory region is used to capture NULL pointer references as well
287 as some core kernel functions.
289 comment "Clock/PLL Setup"
292 int "Crystal Frequency in Hz"
293 default "11059200" if BFIN533_STAMP
294 default "27000000" if BFIN533_EZKIT
295 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
296 default "30000000" if BFIN561_EZKIT
297 default "24576000" if PNAV10
298 default "10000000" if BFIN532_IP0X
300 The frequency of CLKIN crystal oscillator on the board in Hz.
302 config BFIN_KERNEL_CLOCK
303 bool "Re-program Clocks while Kernel boots?"
306 This option decides if kernel clocks are re-programed from the
307 bootloader settings. If the clocks are not set, the SDRAM settings
308 are also not changed, and the Bootloader does 100% of the hardware
312 int "SDRAM Memory Size in MBytes"
313 depends on BFIN_KERNEL_CLOCK
317 int "Memory Address Width"
318 depends on BFIN_KERNEL_CLOCK
321 default 9 if BFIN533_EZKIT
322 default 9 if BFIN561_EZKIT
323 default 9 if H8606_HVSISTEMAS
324 default 10 if BFIN527_EZKIT
325 default 10 if BFIN537_STAMP
326 default 11 if BFIN533_STAMP
328 default 10 if BFIN532_IP0X
332 depends on BFIN_KERNEL_CLOCK
337 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
340 If this is set the clock will be divided by 2, before it goes to the PLL.
344 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
346 default "22" if BFIN533_EZKIT
347 default "45" if BFIN533_STAMP
348 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
349 default "22" if BFIN533_BLUETECHNIX_CM
350 default "20" if BFIN537_BLUETECHNIX_CM
351 default "20" if BFIN561_BLUETECHNIX_CM
352 default "20" if BFIN561_EZKIT
353 default "16" if H8606_HVSISTEMAS
355 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
356 PLL Frequency = (Crystal Frequency) * (this setting)
359 prompt "Core Clock Divider"
360 depends on BFIN_KERNEL_CLOCK
363 This sets the frequency of the core. It can be 1, 2, 4 or 8
364 Core Frequency = (PLL frequency) / (this setting)
380 int "System Clock Divider"
381 depends on BFIN_KERNEL_CLOCK
385 This sets the frequency of the system clock (including SDRAM or DDR).
386 This can be between 1 and 15
387 System Clock = (PLL frequency) / (this setting)
390 int "Max SDRAM Memory Size in MBytes"
391 depends on !BFIN_KERNEL_CLOCK && !MPU
394 This is the max memory size that the kernel will create CPLB
395 tables for. Your system will not be able to handle any more.
398 prompt "DDR SDRAM Chip Type"
399 depends on BFIN_KERNEL_CLOCK
401 default MEM_MT46V32M16_5B
403 config MEM_MT46V32M16_6T
406 config MEM_MT46V32M16_5B
411 # Max & Min Speeds for various Chips
415 default 600000000 if BF522
416 default 400000000 if BF523
417 default 400000000 if BF524
418 default 600000000 if BF525
419 default 400000000 if BF526
420 default 600000000 if BF527
421 default 400000000 if BF531
422 default 400000000 if BF532
423 default 750000000 if BF533
424 default 500000000 if BF534
425 default 400000000 if BF536
426 default 600000000 if BF537
427 default 533333333 if BF538
428 default 533333333 if BF539
429 default 600000000 if BF542
430 default 533333333 if BF544
431 default 600000000 if BF547
432 default 600000000 if BF548
433 default 533333333 if BF549
434 default 600000000 if BF561
448 comment "Kernel Timer/Scheduler"
450 source kernel/Kconfig.hz
456 config GENERIC_CLOCKEVENTS
457 bool "Generic clock events"
458 depends on GENERIC_TIME
461 config CYCLES_CLOCKSOURCE
462 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
463 depends on EXPERIMENTAL
464 depends on GENERIC_CLOCKEVENTS
465 depends on !BFIN_SCRATCH_REG_CYCLES
468 If you say Y here, you will enable support for using the 'cycles'
469 registers as a clock source. Doing so means you will be unable to
470 safely write to the 'cycles' register during runtime. You will
471 still be able to read it (such as for performance monitoring), but
472 writing the registers will most likely crash the kernel.
474 source kernel/time/Kconfig
476 comment "Memory Setup"
480 config ENET_FLASH_PIN
481 int "PF port/pin used for flash and ethernet sharing"
482 depends on (BFIN533_STAMP)
485 PF port/pin used for flash and ethernet sharing to allow other PF
486 pins to be used on other platforms without having to touch common
488 For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
491 prompt "Blackfin Exception Scratch Register"
492 default BFIN_SCRATCH_REG_RETN
494 Select the resource to reserve for the Exception handler:
495 - RETN: Non-Maskable Interrupt (NMI)
496 - RETE: Exception Return (JTAG/ICE)
497 - CYCLES: Performance counter
499 If you are unsure, please select "RETN".
501 config BFIN_SCRATCH_REG_RETN
504 Use the RETN register in the Blackfin exception handler
505 as a stack scratch register. This means you cannot
506 safely use NMI on the Blackfin while running Linux, but
507 you can debug the system with a JTAG ICE and use the
508 CYCLES performance registers.
510 If you are unsure, please select "RETN".
512 config BFIN_SCRATCH_REG_RETE
515 Use the RETE register in the Blackfin exception handler
516 as a stack scratch register. This means you cannot
517 safely use a JTAG ICE while debugging a Blackfin board,
518 but you can safely use the CYCLES performance registers
521 If you are unsure, please select "RETN".
523 config BFIN_SCRATCH_REG_CYCLES
526 Use the CYCLES register in the Blackfin exception handler
527 as a stack scratch register. This means you cannot
528 safely use the CYCLES performance registers on a Blackfin
529 board at anytime, but you can debug the system with a JTAG
532 If you are unsure, please select "RETN".
539 menu "Blackfin Kernel Optimizations"
541 comment "Memory Optimizations"
544 bool "Locate interrupt entry code in L1 Memory"
547 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
548 into L1 instruction memory. (less latency)
550 config EXCPT_IRQ_SYSC_L1
551 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
554 If enabled, the entire ASM lowlevel exception and interrupt entry code
555 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
559 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
562 If enabled, the frequently called do_irq dispatcher function is linked
563 into L1 instruction memory. (less latency)
565 config CORE_TIMER_IRQ_L1
566 bool "Locate frequently called timer_interrupt() function in L1 Memory"
569 If enabled, the frequently called timer_interrupt() function is linked
570 into L1 instruction memory. (less latency)
573 bool "Locate frequently idle function in L1 Memory"
576 If enabled, the frequently called idle function is linked
577 into L1 instruction memory. (less latency)
580 bool "Locate kernel schedule function in L1 Memory"
583 If enabled, the frequently called kernel schedule is linked
584 into L1 instruction memory. (less latency)
586 config ARITHMETIC_OPS_L1
587 bool "Locate kernel owned arithmetic functions in L1 Memory"
590 If enabled, arithmetic functions are linked
591 into L1 instruction memory. (less latency)
594 bool "Locate access_ok function in L1 Memory"
597 If enabled, the access_ok function is linked
598 into L1 instruction memory. (less latency)
601 bool "Locate memset function in L1 Memory"
604 If enabled, the memset function is linked
605 into L1 instruction memory. (less latency)
608 bool "Locate memcpy function in L1 Memory"
611 If enabled, the memcpy function is linked
612 into L1 instruction memory. (less latency)
614 config SYS_BFIN_SPINLOCK_L1
615 bool "Locate sys_bfin_spinlock function in L1 Memory"
618 If enabled, sys_bfin_spinlock function is linked
619 into L1 instruction memory. (less latency)
621 config IP_CHECKSUM_L1
622 bool "Locate IP Checksum function in L1 Memory"
625 If enabled, the IP Checksum function is linked
626 into L1 instruction memory. (less latency)
628 config CACHELINE_ALIGNED_L1
629 bool "Locate cacheline_aligned data to L1 Data Memory"
634 If enabled, cacheline_anligned data is linked
635 into L1 data memory. (less latency)
637 config SYSCALL_TAB_L1
638 bool "Locate Syscall Table L1 Data Memory"
642 If enabled, the Syscall LUT is linked
643 into L1 data memory. (less latency)
645 config CPLB_SWITCH_TAB_L1
646 bool "Locate CPLB Switch Tables L1 Data Memory"
650 If enabled, the CPLB Switch Tables are linked
651 into L1 data memory. (less latency)
657 prompt "Kernel executes from"
659 Choose the memory type that the kernel will be running in.
664 The kernel will be resident in RAM when running.
669 The kernel will be resident in FLASH/ROM when running.
676 tristate "Enable Blackfin General Purpose Timers API"
679 Enable support for the General Purpose Timers API. If you
682 To compile this driver as a module, choose M here: the module
683 will be called gptimers.ko.
686 bool "Enable DMA Support"
687 depends on (BF52x || BF53x || BF561 || BF54x)
690 DMA driver for BF5xx.
693 prompt "Uncached SDRAM region"
694 default DMA_UNCACHED_1M
695 depends on BFIN_DMA_5XX
696 config DMA_UNCACHED_2M
697 bool "Enable 2M DMA region"
698 config DMA_UNCACHED_1M
699 bool "Enable 1M DMA region"
700 config DMA_UNCACHED_NONE
701 bool "Disable DMA region"
705 comment "Cache Support"
710 config BFIN_DCACHE_BANKA
711 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
712 depends on BFIN_DCACHE && !BF531
714 config BFIN_ICACHE_LOCK
715 bool "Enable Instruction Cache Locking"
719 depends on BFIN_DCACHE
725 Cached data will be written back to SDRAM only when needed.
726 This can give a nice increase in performance, but beware of
727 broken drivers that do not properly invalidate/flush their
730 Write Through Policy:
731 Cached data will always be written back to SDRAM when the
732 cache is updated. This is a completely safe setting, but
733 performance is worse than Write Back.
735 If you are unsure of the options and you want to be safe,
736 then go with Write Through.
742 Cached data will be written back to SDRAM only when needed.
743 This can give a nice increase in performance, but beware of
744 broken drivers that do not properly invalidate/flush their
747 Write Through Policy:
748 Cached data will always be written back to SDRAM when the
749 cache is updated. This is a completely safe setting, but
750 performance is worse than Write Back.
752 If you are unsure of the options and you want to be safe,
753 then go with Write Through.
758 int "Set the max L1 SRAM pieces"
761 Set the max memory pieces for the L1 SRAM allocation algorithm.
762 Min value is 16. Max value is 1024.
766 bool "Enable the memory protection unit (EXPERIMENTAL)"
769 Use the processor's MPU to protect applications from accessing
770 memory they do not own. This comes at a performance penalty
771 and is recommended only for debugging.
773 comment "Asynchonous Memory Configuration"
775 menu "EBIU_AMGCTL Global Control"
781 bool "DMA has priority over core for ext. accesses"
786 bool "Bank 0 16 bit packing enable"
791 bool "Bank 1 16 bit packing enable"
796 bool "Bank 2 16 bit packing enable"
801 bool "Bank 3 16 bit packing enable"
805 prompt"Enable Asynchonous Memory Banks"
809 bool "Disable All Banks"
815 bool "Enable Bank 0 & 1"
817 config C_AMBEN_B0_B1_B2
818 bool "Enable Bank 0 & 1 & 2"
821 bool "Enable All Banks"
825 menu "EBIU_AMBCTL Control"
843 config EBIU_MBSCTLVAL
844 hex "EBIU Bank Select Control Register"
849 hex "Flash Memory Mode Control Register"
854 hex "Flash Memory Bank Control Register"
859 #############################################################################
860 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
867 source "drivers/pci/Kconfig"
870 bool "Support for hot-pluggable device"
872 Say Y here if you want to plug devices into your computer while
873 the system is running, and be able to use them quickly. In many
874 cases, the devices can likewise be unplugged at any time too.
876 One well known example of this is PCMCIA- or PC-cards, credit-card
877 size devices such as network cards, modems or hard drives which are
878 plugged into slots found on all modern laptop computers. Another
879 example, used on modern desktops as well as laptops, is USB.
881 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
882 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
883 Then your kernel will automatically call out to a user mode "policy
884 agent" (/sbin/hotplug) to load modules and set up software needed
885 to use devices as you hotplug them.
887 source "drivers/pcmcia/Kconfig"
889 source "drivers/pci/hotplug/Kconfig"
893 menu "Executable file formats"
895 source "fs/Kconfig.binfmt"
899 menu "Power management options"
900 source "kernel/power/Kconfig"
902 config ARCH_SUSPEND_POSSIBLE
907 prompt "Default Power Saving Mode"
909 default PM_BFIN_SLEEP_DEEPER
910 config PM_BFIN_SLEEP_DEEPER
913 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
914 power dissipation by disabling the clock to the processor core (CCLK).
915 Furthermore, Standby sets the internal power supply voltage (VDDINT)
916 to 0.85 V to provide the greatest power savings, while preserving the
918 The PLL and system clock (SCLK) continue to operate at a very low
919 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
920 the SDRAM is put into Self Refresh Mode. Typically an external event
921 such as GPIO interrupt or RTC activity wakes up the processor.
922 Various Peripherals such as UART, SPORT, PPI may not function as
923 normal during Sleep Deeper, due to the reduced SCLK frequency.
924 When in the sleep mode, system DMA access to L1 memory is not supported.
929 Sleep Mode (High Power Savings) - The sleep mode reduces power
930 dissipation by disabling the clock to the processor core (CCLK).
931 The PLL and system clock (SCLK), however, continue to operate in
932 this mode. Typically an external event or RTC activity will wake
933 up the processor. When in the sleep mode,
934 system DMA access to L1 memory is not supported.
937 config PM_WAKEUP_BY_GPIO
938 bool "Cause Wakeup Event by GPIO"
940 config PM_WAKEUP_GPIO_NUMBER
941 int "Wakeup GPIO number"
943 depends on PM_WAKEUP_BY_GPIO
944 default 2 if BFIN537_STAMP
947 prompt "GPIO Polarity"
948 depends on PM_WAKEUP_BY_GPIO
949 default PM_WAKEUP_GPIO_POLAR_H
950 config PM_WAKEUP_GPIO_POLAR_H
952 config PM_WAKEUP_GPIO_POLAR_L
954 config PM_WAKEUP_GPIO_POLAR_EDGE_F
956 config PM_WAKEUP_GPIO_POLAR_EDGE_R
958 config PM_WAKEUP_GPIO_POLAR_EDGE_B
964 if (BF537 || BF533 || BF54x)
966 menu "CPU Frequency scaling"
968 source "drivers/cpufreq/Kconfig"
974 If you want to enable this option, you should select the
975 DPMC driver from Character Devices.
982 source "drivers/Kconfig"
986 source "arch/blackfin/Kconfig.debug"
988 source "security/Kconfig"
990 source "crypto/Kconfig"