2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 Not Supported Yet - Work in progress - BF561 Processor Support.
171 default BF_REV_0_1 if BF527
172 default BF_REV_0_2 if BF537
173 default BF_REV_0_3 if BF533
174 default BF_REV_0_0 if BF549
178 depends on (BF52x || BF54x)
182 depends on (BF52x || BF54x)
186 depends on (BF537 || BF536 || BF534)
190 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
194 depends on (BF561 || BF533 || BF532 || BF531)
198 depends on (BF561 || BF533 || BF532 || BF531)
210 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
215 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
220 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
223 config MEM_GENERIC_BOARD
225 depends on GENERIC_BOARD
228 config MEM_MT48LC64M4A2FB_7E
230 depends on (BFIN533_STAMP)
233 config MEM_MT48LC16M16A2TG_75
235 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
236 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
240 config MEM_MT48LC32M8A2_75
242 depends on (BFIN537_STAMP || PNAV10)
245 config MEM_MT48LC8M32B2B5_7
247 depends on (BFIN561_BLUETECHNIX_CM)
250 config MEM_MT48LC32M16A2TG_75
252 depends on (BFIN527_EZKIT || BFIN532_IP0X)
255 source "arch/blackfin/mach-bf527/Kconfig"
256 source "arch/blackfin/mach-bf533/Kconfig"
257 source "arch/blackfin/mach-bf561/Kconfig"
258 source "arch/blackfin/mach-bf537/Kconfig"
259 source "arch/blackfin/mach-bf548/Kconfig"
261 menu "Board customizations"
264 bool "Default bootloader kernel arguments"
267 string "Initial kernel command string"
268 depends on CMDLINE_BOOL
269 default "console=ttyBF0,57600"
271 If you don't have a boot loader capable of passing a command line string
272 to the kernel, you may specify one here. As a minimum, you should specify
273 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
275 comment "Clock/PLL Setup"
278 int "Crystal Frequency in Hz"
279 default "11059200" if BFIN533_STAMP
280 default "27000000" if BFIN533_EZKIT
281 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
282 default "30000000" if BFIN561_EZKIT
283 default "24576000" if PNAV10
284 default "10000000" if BFIN532_IP0X
286 The frequency of CLKIN crystal oscillator on the board in Hz.
288 config BFIN_KERNEL_CLOCK
289 bool "Re-program Clocks while Kernel boots?"
292 This option decides if kernel clocks are re-programed from the
293 bootloader settings. If the clocks are not set, the SDRAM settings
294 are also not changed, and the Bootloader does 100% of the hardware
298 int "Memory Address Width"
299 depends on BFIN_KERNEL_CLOCK
301 default 9 if BFIN533_EZKIT
302 default 9 if BFIN561_EZKIT
303 default 9 if H8606_HVSISTEMAS
304 default 10 if BFIN527_EZKIT
305 default 10 if BFIN537_STAMP
306 default 11 if BFIN533_STAMP
308 default 10 if BFIN532_IP0X
312 depends on BFIN_KERNEL_CLOCK
317 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
320 If this is set the clock will be divided by 2, before it goes to the PLL.
324 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
326 default "22" if BFIN533_EZKIT
327 default "45" if BFIN533_STAMP
328 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
329 default "22" if BFIN533_BLUETECHNIX_CM
330 default "20" if BFIN537_BLUETECHNIX_CM
331 default "20" if BFIN561_BLUETECHNIX_CM
332 default "20" if BFIN561_EZKIT
333 default "16" if H8606_HVSISTEMAS
335 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
336 PLL Frequency = (Crystal Frequency) * (this setting)
339 prompt "Core Clock Divider"
340 depends on BFIN_KERNEL_CLOCK
343 This sets the frequency of the core. It can be 1, 2, 4 or 8
344 Core Frequency = (PLL frequency) / (this setting)
360 int "System Clock Divider"
361 depends on BFIN_KERNEL_CLOCK
363 default 5 if BFIN533_EZKIT
364 default 5 if BFIN533_STAMP
365 default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
366 default 5 if BFIN533_BLUETECHNIX_CM
367 default 4 if BFIN537_BLUETECHNIX_CM
368 default 4 if BFIN561_BLUETECHNIX_CM
369 default 5 if BFIN561_EZKIT
370 default 3 if H8606_HVSISTEMAS
372 This sets the frequency of the system clock (including SDRAM or DDR).
373 This can be between 1 and 15
374 System Clock = (PLL frequency) / (this setting)
377 # Max & Min Speeds for various Chips
381 default 600000000 if BF522
382 default 400000000 if BF523
383 default 400000000 if BF524
384 default 600000000 if BF525
385 default 400000000 if BF526
386 default 600000000 if BF527
387 default 400000000 if BF531
388 default 400000000 if BF532
389 default 750000000 if BF533
390 default 500000000 if BF534
391 default 400000000 if BF536
392 default 600000000 if BF537
393 default 533333333 if BF538
394 default 533333333 if BF539
395 default 600000000 if BF542
396 default 533333333 if BF544
397 default 600000000 if BF547
398 default 600000000 if BF548
399 default 533333333 if BF549
400 default 600000000 if BF561
414 comment "Kernel Timer/Scheduler"
416 source kernel/Kconfig.hz
422 config GENERIC_CLOCKEVENTS
423 bool "Generic clock events"
424 depends on GENERIC_TIME
427 config CYCLES_CLOCKSOURCE
428 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
429 depends on EXPERIMENTAL
430 depends on GENERIC_CLOCKEVENTS
431 depends on !BFIN_SCRATCH_REG_CYCLES
434 If you say Y here, you will enable support for using the 'cycles'
435 registers as a clock source. Doing so means you will be unable to
436 safely write to the 'cycles' register during runtime. You will
437 still be able to read it (such as for performance monitoring), but
438 writing the registers will most likely crash the kernel.
440 source kernel/time/Kconfig
442 comment "Memory Setup"
445 int "SDRAM Memory Size in MBytes"
446 default 32 if BFIN533_EZKIT
447 default 64 if BFIN527_EZKIT
448 default 64 if BFIN537_STAMP
449 default 64 if BFIN548_EZKIT
450 default 64 if BFIN561_EZKIT
451 default 128 if BFIN533_STAMP
453 default 32 if H8606_HVSISTEMAS
454 default 64 if BFIN548_BLUETECHNIX_CM
455 default 64 if BFIN532_IP0X
458 prompt "DDR SDRAM Chip Type"
459 depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
460 default MEM_MT46V32M16_5B
462 config MEM_MT46V32M16_6T
465 config MEM_MT46V32M16_5B
469 config ENET_FLASH_PIN
470 int "PF port/pin used for flash and ethernet sharing"
471 depends on (BFIN533_STAMP)
474 PF port/pin used for flash and ethernet sharing to allow other PF
475 pins to be used on other platforms without having to touch common
477 For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
480 hex "Kernel load address for booting"
482 range 0x1000 0x20000000
484 This option allows you to set the load address of the kernel.
485 This can be useful if you are on a board which has a small amount
486 of memory or you wish to reserve some memory at the beginning of
489 Note that you need to keep this value above 4k (0x1000) as this
490 memory region is used to capture NULL pointer references as well
491 as some core kernel functions.
494 prompt "Blackfin Exception Scratch Register"
495 default BFIN_SCRATCH_REG_RETN
497 Select the resource to reserve for the Exception handler:
498 - RETN: Non-Maskable Interrupt (NMI)
499 - RETE: Exception Return (JTAG/ICE)
500 - CYCLES: Performance counter
502 If you are unsure, please select "RETN".
504 config BFIN_SCRATCH_REG_RETN
507 Use the RETN register in the Blackfin exception handler
508 as a stack scratch register. This means you cannot
509 safely use NMI on the Blackfin while running Linux, but
510 you can debug the system with a JTAG ICE and use the
511 CYCLES performance registers.
513 If you are unsure, please select "RETN".
515 config BFIN_SCRATCH_REG_RETE
518 Use the RETE register in the Blackfin exception handler
519 as a stack scratch register. This means you cannot
520 safely use a JTAG ICE while debugging a Blackfin board,
521 but you can safely use the CYCLES performance registers
524 If you are unsure, please select "RETN".
526 config BFIN_SCRATCH_REG_CYCLES
529 Use the CYCLES register in the Blackfin exception handler
530 as a stack scratch register. This means you cannot
531 safely use the CYCLES performance registers on a Blackfin
532 board at anytime, but you can debug the system with a JTAG
535 If you are unsure, please select "RETN".
542 menu "Blackfin Kernel Optimizations"
544 comment "Memory Optimizations"
547 bool "Locate interrupt entry code in L1 Memory"
550 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
551 into L1 instruction memory. (less latency)
553 config EXCPT_IRQ_SYSC_L1
554 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
557 If enabled, the entire ASM lowlevel exception and interrupt entry code
558 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
562 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
565 If enabled, the frequently called do_irq dispatcher function is linked
566 into L1 instruction memory. (less latency)
568 config CORE_TIMER_IRQ_L1
569 bool "Locate frequently called timer_interrupt() function in L1 Memory"
572 If enabled, the frequently called timer_interrupt() function is linked
573 into L1 instruction memory. (less latency)
576 bool "Locate frequently idle function in L1 Memory"
579 If enabled, the frequently called idle function is linked
580 into L1 instruction memory. (less latency)
583 bool "Locate kernel schedule function in L1 Memory"
586 If enabled, the frequently called kernel schedule is linked
587 into L1 instruction memory. (less latency)
589 config ARITHMETIC_OPS_L1
590 bool "Locate kernel owned arithmetic functions in L1 Memory"
593 If enabled, arithmetic functions are linked
594 into L1 instruction memory. (less latency)
597 bool "Locate access_ok function in L1 Memory"
600 If enabled, the access_ok function is linked
601 into L1 instruction memory. (less latency)
604 bool "Locate memset function in L1 Memory"
607 If enabled, the memset function is linked
608 into L1 instruction memory. (less latency)
611 bool "Locate memcpy function in L1 Memory"
614 If enabled, the memcpy function is linked
615 into L1 instruction memory. (less latency)
617 config SYS_BFIN_SPINLOCK_L1
618 bool "Locate sys_bfin_spinlock function in L1 Memory"
621 If enabled, sys_bfin_spinlock function is linked
622 into L1 instruction memory. (less latency)
624 config IP_CHECKSUM_L1
625 bool "Locate IP Checksum function in L1 Memory"
628 If enabled, the IP Checksum function is linked
629 into L1 instruction memory. (less latency)
631 config CACHELINE_ALIGNED_L1
632 bool "Locate cacheline_aligned data to L1 Data Memory"
637 If enabled, cacheline_anligned data is linked
638 into L1 data memory. (less latency)
640 config SYSCALL_TAB_L1
641 bool "Locate Syscall Table L1 Data Memory"
645 If enabled, the Syscall LUT is linked
646 into L1 data memory. (less latency)
648 config CPLB_SWITCH_TAB_L1
649 bool "Locate CPLB Switch Tables L1 Data Memory"
653 If enabled, the CPLB Switch Tables are linked
654 into L1 data memory. (less latency)
660 prompt "Kernel executes from"
662 Choose the memory type that the kernel will be running in.
667 The kernel will be resident in RAM when running.
672 The kernel will be resident in FLASH/ROM when running.
679 tristate "Enable Blackfin General Purpose Timers API"
682 Enable support for the General Purpose Timers API. If you
685 To compile this driver as a module, choose M here: the module
686 will be called gptimers.ko.
689 bool "Enable DMA Support"
690 depends on (BF52x || BF53x || BF561 || BF54x)
693 DMA driver for BF5xx.
696 prompt "Uncached SDRAM region"
697 default DMA_UNCACHED_1M
698 depends on BFIN_DMA_5XX
699 config DMA_UNCACHED_2M
700 bool "Enable 2M DMA region"
701 config DMA_UNCACHED_1M
702 bool "Enable 1M DMA region"
703 config DMA_UNCACHED_NONE
704 bool "Disable DMA region"
708 comment "Cache Support"
713 config BFIN_DCACHE_BANKA
714 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
715 depends on BFIN_DCACHE && !BF531
717 config BFIN_ICACHE_LOCK
718 bool "Enable Instruction Cache Locking"
722 depends on BFIN_DCACHE
728 Cached data will be written back to SDRAM only when needed.
729 This can give a nice increase in performance, but beware of
730 broken drivers that do not properly invalidate/flush their
733 Write Through Policy:
734 Cached data will always be written back to SDRAM when the
735 cache is updated. This is a completely safe setting, but
736 performance is worse than Write Back.
738 If you are unsure of the options and you want to be safe,
739 then go with Write Through.
745 Cached data will be written back to SDRAM only when needed.
746 This can give a nice increase in performance, but beware of
747 broken drivers that do not properly invalidate/flush their
750 Write Through Policy:
751 Cached data will always be written back to SDRAM when the
752 cache is updated. This is a completely safe setting, but
753 performance is worse than Write Back.
755 If you are unsure of the options and you want to be safe,
756 then go with Write Through.
761 int "Set the max L1 SRAM pieces"
764 Set the max memory pieces for the L1 SRAM allocation algorithm.
765 Min value is 16. Max value is 1024.
769 bool "Enable the memory protection unit (EXPERIMENTAL)"
772 Use the processor's MPU to protect applications from accessing
773 memory they do not own. This comes at a performance penalty
774 and is recommended only for debugging.
776 comment "Asynchonous Memory Configuration"
778 menu "EBIU_AMGCTL Global Control"
784 bool "DMA has priority over core for ext. accesses"
789 bool "Bank 0 16 bit packing enable"
794 bool "Bank 1 16 bit packing enable"
799 bool "Bank 2 16 bit packing enable"
804 bool "Bank 3 16 bit packing enable"
808 prompt"Enable Asynchonous Memory Banks"
812 bool "Disable All Banks"
818 bool "Enable Bank 0 & 1"
820 config C_AMBEN_B0_B1_B2
821 bool "Enable Bank 0 & 1 & 2"
824 bool "Enable All Banks"
828 menu "EBIU_AMBCTL Control"
846 config EBIU_MBSCTLVAL
847 hex "EBIU Bank Select Control Register"
852 hex "Flash Memory Mode Control Register"
857 hex "Flash Memory Bank Control Register"
862 #############################################################################
863 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
870 source "drivers/pci/Kconfig"
873 bool "Support for hot-pluggable device"
875 Say Y here if you want to plug devices into your computer while
876 the system is running, and be able to use them quickly. In many
877 cases, the devices can likewise be unplugged at any time too.
879 One well known example of this is PCMCIA- or PC-cards, credit-card
880 size devices such as network cards, modems or hard drives which are
881 plugged into slots found on all modern laptop computers. Another
882 example, used on modern desktops as well as laptops, is USB.
884 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
885 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
886 Then your kernel will automatically call out to a user mode "policy
887 agent" (/sbin/hotplug) to load modules and set up software needed
888 to use devices as you hotplug them.
890 source "drivers/pcmcia/Kconfig"
892 source "drivers/pci/hotplug/Kconfig"
896 menu "Executable file formats"
898 source "fs/Kconfig.binfmt"
902 menu "Power management options"
903 source "kernel/power/Kconfig"
905 config ARCH_SUSPEND_POSSIBLE
910 prompt "Default Power Saving Mode"
912 default PM_BFIN_SLEEP_DEEPER
913 config PM_BFIN_SLEEP_DEEPER
916 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
917 power dissipation by disabling the clock to the processor core (CCLK).
918 Furthermore, Standby sets the internal power supply voltage (VDDINT)
919 to 0.85 V to provide the greatest power savings, while preserving the
921 The PLL and system clock (SCLK) continue to operate at a very low
922 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
923 the SDRAM is put into Self Refresh Mode. Typically an external event
924 such as GPIO interrupt or RTC activity wakes up the processor.
925 Various Peripherals such as UART, SPORT, PPI may not function as
926 normal during Sleep Deeper, due to the reduced SCLK frequency.
927 When in the sleep mode, system DMA access to L1 memory is not supported.
932 Sleep Mode (High Power Savings) - The sleep mode reduces power
933 dissipation by disabling the clock to the processor core (CCLK).
934 The PLL and system clock (SCLK), however, continue to operate in
935 this mode. Typically an external event or RTC activity will wake
936 up the processor. When in the sleep mode,
937 system DMA access to L1 memory is not supported.
940 config PM_WAKEUP_BY_GPIO
941 bool "Cause Wakeup Event by GPIO"
943 config PM_WAKEUP_GPIO_NUMBER
944 int "Wakeup GPIO number"
946 depends on PM_WAKEUP_BY_GPIO
947 default 2 if BFIN537_STAMP
950 prompt "GPIO Polarity"
951 depends on PM_WAKEUP_BY_GPIO
952 default PM_WAKEUP_GPIO_POLAR_H
953 config PM_WAKEUP_GPIO_POLAR_H
955 config PM_WAKEUP_GPIO_POLAR_L
957 config PM_WAKEUP_GPIO_POLAR_EDGE_F
959 config PM_WAKEUP_GPIO_POLAR_EDGE_R
961 config PM_WAKEUP_GPIO_POLAR_EDGE_B
967 if (BF537 || BF533 || BF54x)
969 menu "CPU Frequency scaling"
971 source "drivers/cpufreq/Kconfig"
977 If you want to enable this option, you should select the
978 DPMC driver from Character Devices.
985 source "drivers/Kconfig"
989 source "arch/blackfin/Kconfig.debug"
991 source "security/Kconfig"
993 source "crypto/Kconfig"