2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/spi/spi.h>
15 #include <asm/arch/at32ap7000.h>
16 #include <asm/arch/board.h>
17 #include <asm/arch/portmux.h>
18 #include <asm/arch/sm.h>
28 .end = base + 0x3ff, \
29 .flags = IORESOURCE_MEM, \
35 .flags = IORESOURCE_IRQ, \
37 #define NAMED_IRQ(num, _name) \
42 .flags = IORESOURCE_IRQ, \
45 #define DEFINE_DEV(_name, _id) \
46 static struct platform_device _name##_id##_device = { \
49 .resource = _name##_id##_resource, \
50 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
52 #define DEFINE_DEV_DATA(_name, _id) \
53 static struct platform_device _name##_id##_device = { \
57 .platform_data = &_name##_id##_data, \
59 .resource = _name##_id##_resource, \
60 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
63 #define select_peripheral(pin, periph, flags) \
64 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
66 #define DEV_CLK(_name, devname, bus, _index) \
67 static struct clk devname##_##_name = { \
69 .dev = &devname##_device.dev, \
70 .parent = &bus##_clk, \
71 .mode = bus##_clk_mode, \
72 .get_rate = bus##_clk_get_rate, \
76 unsigned long at32ap7000_osc_rates[3] = {
78 /* FIXME: these are ATSTK1002-specific */
83 static unsigned long osc_get_rate(struct clk *clk)
85 return at32ap7000_osc_rates[clk->index];
88 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
90 unsigned long div, mul, rate;
92 if (!(control & SM_BIT(PLLEN)))
95 div = SM_BFEXT(PLLDIV, control) + 1;
96 mul = SM_BFEXT(PLLMUL, control) + 1;
98 rate = clk->parent->get_rate(clk->parent);
99 rate = (rate + div / 2) / div;
105 static unsigned long pll0_get_rate(struct clk *clk)
109 control = sm_readl(&system_manager, PM_PLL0);
111 return pll_get_rate(clk, control);
114 static unsigned long pll1_get_rate(struct clk *clk)
118 control = sm_readl(&system_manager, PM_PLL1);
120 return pll_get_rate(clk, control);
124 * The AT32AP7000 has five primary clock sources: One 32kHz
125 * oscillator, two crystal oscillators and two PLLs.
127 static struct clk osc32k = {
129 .get_rate = osc_get_rate,
133 static struct clk osc0 = {
135 .get_rate = osc_get_rate,
139 static struct clk osc1 = {
141 .get_rate = osc_get_rate,
144 static struct clk pll0 = {
146 .get_rate = pll0_get_rate,
149 static struct clk pll1 = {
151 .get_rate = pll1_get_rate,
156 * The main clock can be either osc0 or pll0. The boot loader may
157 * have chosen one for us, so we don't really know which one until we
158 * have a look at the SM.
160 static struct clk *main_clock;
163 * Synchronous clocks are generated from the main clock. The clocks
164 * must satisfy the constraint
165 * fCPU >= fHSB >= fPB
166 * i.e. each clock must not be faster than its parent.
168 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
170 return main_clock->get_rate(main_clock) >> shift;
173 static void cpu_clk_mode(struct clk *clk, int enabled)
175 struct at32_sm *sm = &system_manager;
179 spin_lock_irqsave(&sm->lock, flags);
180 mask = sm_readl(sm, PM_CPU_MASK);
182 mask |= 1 << clk->index;
184 mask &= ~(1 << clk->index);
185 sm_writel(sm, PM_CPU_MASK, mask);
186 spin_unlock_irqrestore(&sm->lock, flags);
189 static unsigned long cpu_clk_get_rate(struct clk *clk)
191 unsigned long cksel, shift = 0;
193 cksel = sm_readl(&system_manager, PM_CKSEL);
194 if (cksel & SM_BIT(CPUDIV))
195 shift = SM_BFEXT(CPUSEL, cksel) + 1;
197 return bus_clk_get_rate(clk, shift);
200 static void hsb_clk_mode(struct clk *clk, int enabled)
202 struct at32_sm *sm = &system_manager;
206 spin_lock_irqsave(&sm->lock, flags);
207 mask = sm_readl(sm, PM_HSB_MASK);
209 mask |= 1 << clk->index;
211 mask &= ~(1 << clk->index);
212 sm_writel(sm, PM_HSB_MASK, mask);
213 spin_unlock_irqrestore(&sm->lock, flags);
216 static unsigned long hsb_clk_get_rate(struct clk *clk)
218 unsigned long cksel, shift = 0;
220 cksel = sm_readl(&system_manager, PM_CKSEL);
221 if (cksel & SM_BIT(HSBDIV))
222 shift = SM_BFEXT(HSBSEL, cksel) + 1;
224 return bus_clk_get_rate(clk, shift);
227 static void pba_clk_mode(struct clk *clk, int enabled)
229 struct at32_sm *sm = &system_manager;
233 spin_lock_irqsave(&sm->lock, flags);
234 mask = sm_readl(sm, PM_PBA_MASK);
236 mask |= 1 << clk->index;
238 mask &= ~(1 << clk->index);
239 sm_writel(sm, PM_PBA_MASK, mask);
240 spin_unlock_irqrestore(&sm->lock, flags);
243 static unsigned long pba_clk_get_rate(struct clk *clk)
245 unsigned long cksel, shift = 0;
247 cksel = sm_readl(&system_manager, PM_CKSEL);
248 if (cksel & SM_BIT(PBADIV))
249 shift = SM_BFEXT(PBASEL, cksel) + 1;
251 return bus_clk_get_rate(clk, shift);
254 static void pbb_clk_mode(struct clk *clk, int enabled)
256 struct at32_sm *sm = &system_manager;
260 spin_lock_irqsave(&sm->lock, flags);
261 mask = sm_readl(sm, PM_PBB_MASK);
263 mask |= 1 << clk->index;
265 mask &= ~(1 << clk->index);
266 sm_writel(sm, PM_PBB_MASK, mask);
267 spin_unlock_irqrestore(&sm->lock, flags);
270 static unsigned long pbb_clk_get_rate(struct clk *clk)
272 unsigned long cksel, shift = 0;
274 cksel = sm_readl(&system_manager, PM_CKSEL);
275 if (cksel & SM_BIT(PBBDIV))
276 shift = SM_BFEXT(PBBSEL, cksel) + 1;
278 return bus_clk_get_rate(clk, shift);
281 static struct clk cpu_clk = {
283 .get_rate = cpu_clk_get_rate,
286 static struct clk hsb_clk = {
289 .get_rate = hsb_clk_get_rate,
291 static struct clk pba_clk = {
294 .mode = hsb_clk_mode,
295 .get_rate = pba_clk_get_rate,
298 static struct clk pbb_clk = {
301 .mode = hsb_clk_mode,
302 .get_rate = pbb_clk_get_rate,
307 /* --------------------------------------------------------------------
308 * Generic Clock operations
309 * -------------------------------------------------------------------- */
311 static void genclk_mode(struct clk *clk, int enabled)
315 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
317 control |= SM_BIT(CEN);
319 control &= ~SM_BIT(CEN);
320 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
323 static unsigned long genclk_get_rate(struct clk *clk)
326 unsigned long div = 1;
328 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
329 if (control & SM_BIT(DIVEN))
330 div = 2 * (SM_BFEXT(DIV, control) + 1);
332 return clk->parent->get_rate(clk->parent) / div;
335 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
338 unsigned long parent_rate, actual_rate, div;
340 parent_rate = clk->parent->get_rate(clk->parent);
341 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
343 if (rate > 3 * parent_rate / 4) {
344 actual_rate = parent_rate;
345 control &= ~SM_BIT(DIVEN);
347 div = (parent_rate + rate) / (2 * rate) - 1;
348 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
349 actual_rate = parent_rate / (2 * (div + 1));
352 printk("clk %s: new rate %lu (actual rate %lu)\n",
353 clk->name, rate, actual_rate);
356 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
362 int genclk_set_parent(struct clk *clk, struct clk *parent)
366 printk("clk %s: new parent %s (was %s)\n",
367 clk->name, parent->name, clk->parent->name);
369 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
371 if (parent == &osc1 || parent == &pll1)
372 control |= SM_BIT(OSCSEL);
373 else if (parent == &osc0 || parent == &pll0)
374 control &= ~SM_BIT(OSCSEL);
378 if (parent == &pll0 || parent == &pll1)
379 control |= SM_BIT(PLLSEL);
381 control &= ~SM_BIT(PLLSEL);
383 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
384 clk->parent = parent;
389 static void __init genclk_init_parent(struct clk *clk)
394 BUG_ON(clk->index > 7);
396 control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
397 if (control & SM_BIT(OSCSEL))
398 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
400 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
402 clk->parent = parent;
405 /* --------------------------------------------------------------------
407 * -------------------------------------------------------------------- */
408 static struct resource sm_resource[] = {
410 NAMED_IRQ(19, "eim"),
412 NAMED_IRQ(21, "rtc"),
414 struct platform_device at32_sm_device = {
417 .resource = sm_resource,
418 .num_resources = ARRAY_SIZE(sm_resource),
420 static struct clk at32_sm_pclk = {
422 .dev = &at32_sm_device.dev,
424 .mode = pbb_clk_mode,
425 .get_rate = pbb_clk_get_rate,
430 static struct resource intc0_resource[] = {
433 struct platform_device at32_intc0_device = {
436 .resource = intc0_resource,
437 .num_resources = ARRAY_SIZE(intc0_resource),
439 DEV_CLK(pclk, at32_intc0, pbb, 1);
441 static struct clk ebi_clk = {
444 .mode = hsb_clk_mode,
445 .get_rate = hsb_clk_get_rate,
448 static struct clk hramc_clk = {
451 .mode = hsb_clk_mode,
452 .get_rate = hsb_clk_get_rate,
457 static struct resource smc0_resource[] = {
461 DEV_CLK(pclk, smc0, pbb, 13);
462 DEV_CLK(mck, smc0, hsb, 0);
464 static struct platform_device pdc_device = {
468 DEV_CLK(hclk, pdc, hsb, 4);
469 DEV_CLK(pclk, pdc, pba, 16);
471 static struct clk pico_clk = {
474 .mode = cpu_clk_mode,
475 .get_rate = cpu_clk_get_rate,
479 /* --------------------------------------------------------------------
481 * -------------------------------------------------------------------- */
483 static struct clk hmatrix_clk = {
484 .name = "hmatrix_clk",
486 .mode = pbb_clk_mode,
487 .get_rate = pbb_clk_get_rate,
491 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
493 #define hmatrix_readl(reg) \
494 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
495 #define hmatrix_writel(reg,value) \
496 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
499 * Set bits in the HMATRIX Special Function Register (SFR) used by the
500 * External Bus Interface (EBI). This can be used to enable special
501 * features like CompactFlash support, NAND Flash support, etc. on
502 * certain chipselects.
504 static inline void set_ebi_sfr_bits(u32 mask)
508 clk_enable(&hmatrix_clk);
509 sfr = hmatrix_readl(SFR4);
511 hmatrix_writel(SFR4, sfr);
512 clk_disable(&hmatrix_clk);
515 /* --------------------------------------------------------------------
516 * System Timer/Counter (TC)
517 * -------------------------------------------------------------------- */
518 static struct resource at32_systc0_resource[] = {
522 struct platform_device at32_systc0_device = {
525 .resource = at32_systc0_resource,
526 .num_resources = ARRAY_SIZE(at32_systc0_resource),
528 DEV_CLK(pclk, at32_systc0, pbb, 3);
530 /* --------------------------------------------------------------------
532 * -------------------------------------------------------------------- */
534 static struct resource pio0_resource[] = {
539 DEV_CLK(mck, pio0, pba, 10);
541 static struct resource pio1_resource[] = {
546 DEV_CLK(mck, pio1, pba, 11);
548 static struct resource pio2_resource[] = {
553 DEV_CLK(mck, pio2, pba, 12);
555 static struct resource pio3_resource[] = {
560 DEV_CLK(mck, pio3, pba, 13);
562 static struct resource pio4_resource[] = {
567 DEV_CLK(mck, pio4, pba, 14);
569 void __init at32_add_system_devices(void)
571 system_manager.eim_first_irq = EIM_IRQ_BASE;
573 platform_device_register(&at32_sm_device);
574 platform_device_register(&at32_intc0_device);
575 platform_device_register(&smc0_device);
576 platform_device_register(&pdc_device);
578 platform_device_register(&at32_systc0_device);
580 platform_device_register(&pio0_device);
581 platform_device_register(&pio1_device);
582 platform_device_register(&pio2_device);
583 platform_device_register(&pio3_device);
584 platform_device_register(&pio4_device);
587 /* --------------------------------------------------------------------
589 * -------------------------------------------------------------------- */
591 static struct atmel_uart_data atmel_usart0_data = {
595 static struct resource atmel_usart0_resource[] = {
599 DEFINE_DEV_DATA(atmel_usart, 0);
600 DEV_CLK(usart, atmel_usart0, pba, 4);
602 static struct atmel_uart_data atmel_usart1_data = {
606 static struct resource atmel_usart1_resource[] = {
610 DEFINE_DEV_DATA(atmel_usart, 1);
611 DEV_CLK(usart, atmel_usart1, pba, 4);
613 static struct atmel_uart_data atmel_usart2_data = {
617 static struct resource atmel_usart2_resource[] = {
621 DEFINE_DEV_DATA(atmel_usart, 2);
622 DEV_CLK(usart, atmel_usart2, pba, 5);
624 static struct atmel_uart_data atmel_usart3_data = {
628 static struct resource atmel_usart3_resource[] = {
632 DEFINE_DEV_DATA(atmel_usart, 3);
633 DEV_CLK(usart, atmel_usart3, pba, 6);
635 static inline void configure_usart0_pins(void)
637 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
638 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
641 static inline void configure_usart1_pins(void)
643 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
644 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
647 static inline void configure_usart2_pins(void)
649 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
650 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
653 static inline void configure_usart3_pins(void)
655 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
656 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
659 static struct platform_device *__initdata at32_usarts[4];
661 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
663 struct platform_device *pdev;
667 pdev = &atmel_usart0_device;
668 configure_usart0_pins();
671 pdev = &atmel_usart1_device;
672 configure_usart1_pins();
675 pdev = &atmel_usart2_device;
676 configure_usart2_pins();
679 pdev = &atmel_usart3_device;
680 configure_usart3_pins();
686 if (PXSEG(pdev->resource[0].start) == P4SEG) {
687 /* Addresses in the P4 segment are permanently mapped 1:1 */
688 struct atmel_uart_data *data = pdev->dev.platform_data;
689 data->regs = (void __iomem *)pdev->resource[0].start;
693 at32_usarts[line] = pdev;
696 struct platform_device *__init at32_add_device_usart(unsigned int id)
698 platform_device_register(at32_usarts[id]);
699 return at32_usarts[id];
702 struct platform_device *atmel_default_console_device;
704 void __init at32_setup_serial_console(unsigned int usart_id)
706 atmel_default_console_device = at32_usarts[usart_id];
709 /* --------------------------------------------------------------------
711 * -------------------------------------------------------------------- */
713 static struct eth_platform_data macb0_data;
714 static struct resource macb0_resource[] = {
718 DEFINE_DEV_DATA(macb, 0);
719 DEV_CLK(hclk, macb0, hsb, 8);
720 DEV_CLK(pclk, macb0, pbb, 6);
722 static struct eth_platform_data macb1_data;
723 static struct resource macb1_resource[] = {
727 DEFINE_DEV_DATA(macb, 1);
728 DEV_CLK(hclk, macb1, hsb, 9);
729 DEV_CLK(pclk, macb1, pbb, 7);
731 struct platform_device *__init
732 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
734 struct platform_device *pdev;
738 pdev = &macb0_device;
740 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
741 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
742 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
743 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
744 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
745 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
746 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
747 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
748 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
749 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
751 if (!data->is_rmii) {
752 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
753 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
754 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
755 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
756 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
757 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
758 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
759 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
760 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
765 pdev = &macb1_device;
767 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
768 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
769 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
770 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
771 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
772 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
773 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
774 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
775 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
776 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
778 if (!data->is_rmii) {
779 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
780 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
781 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
782 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
783 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
784 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
785 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
786 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
787 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
795 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
796 platform_device_register(pdev);
801 /* --------------------------------------------------------------------
803 * -------------------------------------------------------------------- */
804 static struct resource atmel_spi0_resource[] = {
808 DEFINE_DEV(atmel_spi, 0);
809 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
811 static struct resource atmel_spi1_resource[] = {
815 DEFINE_DEV(atmel_spi, 1);
816 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
819 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
820 unsigned int n, const u8 *pins)
822 unsigned int pin, mode;
824 for (; n; n--, b++) {
825 b->bus_num = bus_num;
826 if (b->chip_select >= 4)
828 pin = (unsigned)b->controller_data;
830 pin = pins[b->chip_select];
831 b->controller_data = (void *)pin;
833 mode = AT32_GPIOF_OUTPUT;
834 if (!(b->mode & SPI_CS_HIGH))
835 mode |= AT32_GPIOF_HIGH;
836 at32_select_gpio(pin, mode);
840 struct platform_device *__init
841 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
844 * Manage the chipselects as GPIOs, normally using the same pins
845 * the SPI controller expects; but boards can use other pins.
847 static u8 __initdata spi0_pins[] =
848 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
849 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
850 static u8 __initdata spi1_pins[] =
851 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
852 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
853 struct platform_device *pdev;
857 pdev = &atmel_spi0_device;
858 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
859 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
860 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
861 at32_spi_setup_slaves(0, b, n, spi0_pins);
865 pdev = &atmel_spi1_device;
866 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
867 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
868 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
869 at32_spi_setup_slaves(1, b, n, spi1_pins);
876 spi_register_board_info(b, n);
877 platform_device_register(pdev);
881 /* --------------------------------------------------------------------
883 * -------------------------------------------------------------------- */
884 static struct lcdc_platform_data lcdc0_data;
885 static struct resource lcdc0_resource[] = {
889 .flags = IORESOURCE_MEM,
893 DEFINE_DEV_DATA(lcdc, 0);
894 DEV_CLK(hclk, lcdc0, hsb, 7);
895 static struct clk lcdc0_pixclk = {
897 .dev = &lcdc0_device.dev,
899 .get_rate = genclk_get_rate,
900 .set_rate = genclk_set_rate,
901 .set_parent = genclk_set_parent,
905 struct platform_device *__init
906 at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
908 struct platform_device *pdev;
912 pdev = &lcdc0_device;
913 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
914 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
915 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
916 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
917 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
918 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
919 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
920 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
921 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
922 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
923 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
924 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
925 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
926 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
927 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
928 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
929 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
930 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
931 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
932 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
933 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
934 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
935 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
936 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
937 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
938 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
939 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
940 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
941 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
942 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
943 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
945 clk_set_parent(&lcdc0_pixclk, &pll0);
946 clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0));
953 memcpy(pdev->dev.platform_data, data,
954 sizeof(struct lcdc_platform_data));
956 platform_device_register(pdev);
960 /* --------------------------------------------------------------------
962 * -------------------------------------------------------------------- */
963 static struct clk gclk0 = {
966 .get_rate = genclk_get_rate,
967 .set_rate = genclk_set_rate,
968 .set_parent = genclk_set_parent,
971 static struct clk gclk1 = {
974 .get_rate = genclk_get_rate,
975 .set_rate = genclk_set_rate,
976 .set_parent = genclk_set_parent,
979 static struct clk gclk2 = {
982 .get_rate = genclk_get_rate,
983 .set_rate = genclk_set_rate,
984 .set_parent = genclk_set_parent,
987 static struct clk gclk3 = {
990 .get_rate = genclk_get_rate,
991 .set_rate = genclk_set_rate,
992 .set_parent = genclk_set_parent,
995 static struct clk gclk4 = {
998 .get_rate = genclk_get_rate,
999 .set_rate = genclk_set_rate,
1000 .set_parent = genclk_set_parent,
1004 struct clk *at32_clock_list[] = {
1030 &atmel_usart0_usart,
1031 &atmel_usart1_usart,
1032 &atmel_usart2_usart,
1033 &atmel_usart3_usart,
1038 &atmel_spi0_spi_clk,
1039 &atmel_spi1_spi_clk,
1048 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1050 void __init at32_portmux_init(void)
1052 at32_init_pio(&pio0_device);
1053 at32_init_pio(&pio1_device);
1054 at32_init_pio(&pio2_device);
1055 at32_init_pio(&pio3_device);
1056 at32_init_pio(&pio4_device);
1059 void __init at32_clock_init(void)
1061 struct at32_sm *sm = &system_manager;
1062 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1065 if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
1070 if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
1071 pll0.parent = &osc1;
1072 if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
1073 pll1.parent = &osc1;
1075 genclk_init_parent(&gclk0);
1076 genclk_init_parent(&gclk1);
1077 genclk_init_parent(&gclk2);
1078 genclk_init_parent(&gclk3);
1079 genclk_init_parent(&gclk4);
1080 genclk_init_parent(&lcdc0_pixclk);
1083 * Turn on all clocks that have at least one user already, and
1084 * turn off everything else. We only do this for module
1085 * clocks, and even though it isn't particularly pretty to
1086 * check the address of the mode function, it should do the
1089 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1090 struct clk *clk = at32_clock_list[i];
1092 if (clk->users == 0)
1095 if (clk->mode == &cpu_clk_mode)
1096 cpu_mask |= 1 << clk->index;
1097 else if (clk->mode == &hsb_clk_mode)
1098 hsb_mask |= 1 << clk->index;
1099 else if (clk->mode == &pba_clk_mode)
1100 pba_mask |= 1 << clk->index;
1101 else if (clk->mode == &pbb_clk_mode)
1102 pbb_mask |= 1 << clk->index;
1105 sm_writel(sm, PM_CPU_MASK, cpu_mask);
1106 sm_writel(sm, PM_HSB_MASK, hsb_mask);
1107 sm_writel(sm, PM_PBA_MASK, pba_mask);
1108 sm_writel(sm, PM_PBB_MASK, pbb_mask);