2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
28 #include <asm/system.h>
30 #include <asm/hardware.h>
34 #include <asm/arch/tc.h>
39 #define debug_printk(x) printk x
41 #define debug_printk(x)
44 #define OMAP_DMA_ACTIVE 0x01
45 #define OMAP_DMA_CCR_EN (1 << 7)
47 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
49 static int enable_1510_mode = 0;
57 void (* callback)(int lch, u16 ch_status, void *data);
62 static int dma_chan_count;
64 static spinlock_t dma_chan_lock;
65 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
67 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
68 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
69 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
70 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
71 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
72 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
75 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
78 #ifdef CONFIG_ARCH_OMAP15XX
79 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
80 int omap_dma_in_1510_mode(void)
82 return enable_1510_mode;
85 #define omap_dma_in_1510_mode() 0
88 #ifdef CONFIG_ARCH_OMAP1
89 static inline int get_gdma_dev(int req)
91 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
92 int shift = ((req - 1) % 5) * 6;
94 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
97 static inline void set_gdma_dev(int req, int dev)
99 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
100 int shift = ((req - 1) % 5) * 6;
104 l &= ~(0x3f << shift);
105 l |= (dev - 1) << shift;
109 #define set_gdma_dev(req, dev) do {} while (0)
112 static void clear_lch_regs(int lch)
115 u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
117 for (i = 0; i < 0x2c; i += 2)
118 omap_writew(0, lch_base + i);
121 void omap_set_dma_priority(int dst_port, int priority)
127 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
128 reg = OMAP_TC_OCPT1_PRIOR;
130 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
131 reg = OMAP_TC_OCPT2_PRIOR;
133 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
134 reg = OMAP_TC_EMIFF_PRIOR;
136 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
137 reg = OMAP_TC_EMIFS_PRIOR;
145 l |= (priority & 0xf) << 8;
149 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
150 int frame_count, int sync_mode,
151 int dma_trigger, int src_or_dst_synch)
153 OMAP_DMA_CSDP_REG(lch) &= ~0x03;
154 OMAP_DMA_CSDP_REG(lch) |= data_type;
156 if (cpu_class_is_omap1()) {
157 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
158 if (sync_mode == OMAP_DMA_SYNC_FRAME)
159 OMAP_DMA_CCR_REG(lch) |= 1 << 5;
161 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
162 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
163 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
166 if (cpu_is_omap24xx() && dma_trigger) {
167 u32 val = OMAP_DMA_CCR_REG(lch);
170 if (dma_trigger > 63)
172 if (dma_trigger > 31)
176 val |= (dma_trigger & 0x1f);
178 if (sync_mode & OMAP_DMA_SYNC_FRAME)
183 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
188 if (src_or_dst_synch)
189 val |= 1 << 24; /* source synch */
191 val &= ~(1 << 24); /* dest synch */
193 OMAP_DMA_CCR_REG(lch) = val;
196 OMAP_DMA_CEN_REG(lch) = elem_count;
197 OMAP_DMA_CFN_REG(lch) = frame_count;
200 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
204 BUG_ON(omap_dma_in_1510_mode());
206 if (cpu_is_omap24xx()) {
211 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
213 case OMAP_DMA_CONSTANT_FILL:
216 case OMAP_DMA_TRANSPARENT_COPY:
219 case OMAP_DMA_COLOR_DIS:
224 OMAP1_DMA_CCR2_REG(lch) = w;
226 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
227 /* Default is channel type 2D */
229 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
230 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
231 w |= 1; /* Channel type G */
233 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
236 /* Note that src_port is only for omap1 */
237 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
238 unsigned long src_start,
239 int src_ei, int src_fi)
241 if (cpu_class_is_omap1()) {
242 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
243 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
246 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
247 OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
249 if (cpu_class_is_omap1()) {
250 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
251 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
254 if (cpu_is_omap24xx())
255 OMAP2_DMA_CSSA_REG(lch) = src_start;
257 OMAP_DMA_CSEI_REG(lch) = src_ei;
258 OMAP_DMA_CSFI_REG(lch) = src_fi;
261 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
263 omap_set_dma_transfer_params(lch, params->data_type,
264 params->elem_count, params->frame_count,
265 params->sync_mode, params->trigger,
266 params->src_or_dst_synch);
267 omap_set_dma_src_params(lch, params->src_port,
268 params->src_amode, params->src_start,
269 params->src_ei, params->src_fi);
271 omap_set_dma_dest_params(lch, params->dst_port,
272 params->dst_amode, params->dst_start,
273 params->dst_ei, params->dst_fi);
276 void omap_set_dma_src_index(int lch, int eidx, int fidx)
278 if (cpu_is_omap24xx()) {
282 OMAP_DMA_CSEI_REG(lch) = eidx;
283 OMAP_DMA_CSFI_REG(lch) = fidx;
286 void omap_set_dma_src_data_pack(int lch, int enable)
288 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
290 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
293 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
295 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
297 switch (burst_mode) {
298 case OMAP_DMA_DATA_BURST_DIS:
300 case OMAP_DMA_DATA_BURST_4:
301 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7);
303 case OMAP_DMA_DATA_BURST_8:
304 /* not supported by current hardware
313 /* Note that dest_port is only for OMAP1 */
314 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
315 unsigned long dest_start,
316 int dst_ei, int dst_fi)
318 if (cpu_class_is_omap1()) {
319 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
320 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
323 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
324 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
326 if (cpu_class_is_omap1()) {
327 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
328 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
331 if (cpu_is_omap24xx())
332 OMAP2_DMA_CDSA_REG(lch) = dest_start;
334 OMAP_DMA_CDEI_REG(lch) = dst_ei;
335 OMAP_DMA_CDFI_REG(lch) = dst_fi;
338 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
340 if (cpu_is_omap24xx()) {
344 OMAP_DMA_CDEI_REG(lch) = eidx;
345 OMAP_DMA_CDFI_REG(lch) = fidx;
348 void omap_set_dma_dest_data_pack(int lch, int enable)
350 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
352 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
355 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
357 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
359 switch (burst_mode) {
360 case OMAP_DMA_DATA_BURST_DIS:
362 case OMAP_DMA_DATA_BURST_4:
363 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14);
365 case OMAP_DMA_DATA_BURST_8:
366 OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14);
369 printk(KERN_ERR "Invalid DMA burst mode\n");
375 static inline void omap_enable_channel_irq(int lch)
379 /* Read CSR to make sure it's cleared. */
380 status = OMAP_DMA_CSR_REG(lch);
382 /* Enable some nice interrupts. */
383 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
385 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
388 static void omap_disable_channel_irq(int lch)
390 if (cpu_is_omap24xx())
391 OMAP_DMA_CICR_REG(lch) = 0;
394 void omap_enable_dma_irq(int lch, u16 bits)
396 dma_chan[lch].enabled_irqs |= bits;
399 void omap_disable_dma_irq(int lch, u16 bits)
401 dma_chan[lch].enabled_irqs &= ~bits;
404 static inline void enable_lnk(int lch)
406 if (cpu_class_is_omap1())
407 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
409 /* Set the ENABLE_LNK bits */
410 if (dma_chan[lch].next_lch != -1)
411 OMAP_DMA_CLNK_CTRL_REG(lch) =
412 dma_chan[lch].next_lch | (1 << 15);
415 static inline void disable_lnk(int lch)
417 /* Disable interrupts */
418 if (cpu_class_is_omap1()) {
419 OMAP_DMA_CICR_REG(lch) = 0;
420 /* Set the STOP_LNK bit */
421 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
424 if (cpu_is_omap24xx()) {
425 omap_disable_channel_irq(lch);
426 /* Clear the ENABLE_LNK bit */
427 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
430 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
433 static inline void omap2_enable_irq_lch(int lch)
437 if (!cpu_is_omap24xx())
440 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
442 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
445 int omap_request_dma(int dev_id, const char *dev_name,
446 void (* callback)(int lch, u16 ch_status, void *data),
447 void *data, int *dma_ch_out)
449 int ch, free_ch = -1;
451 struct omap_dma_lch *chan;
453 spin_lock_irqsave(&dma_chan_lock, flags);
454 for (ch = 0; ch < dma_chan_count; ch++) {
455 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
462 spin_unlock_irqrestore(&dma_chan_lock, flags);
465 chan = dma_chan + free_ch;
466 chan->dev_id = dev_id;
468 if (cpu_class_is_omap1())
469 clear_lch_regs(free_ch);
471 if (cpu_is_omap24xx())
472 omap_clear_dma(free_ch);
474 spin_unlock_irqrestore(&dma_chan_lock, flags);
476 chan->dev_name = dev_name;
477 chan->callback = callback;
479 chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
482 if (cpu_is_omap24xx())
483 chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
485 if (cpu_is_omap16xx()) {
486 /* If the sync device is set, configure it dynamically. */
488 set_gdma_dev(free_ch + 1, dev_id);
489 dev_id = free_ch + 1;
491 /* Disable the 1510 compatibility mode and set the sync device
493 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
494 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
495 OMAP_DMA_CCR_REG(free_ch) = dev_id;
498 if (cpu_is_omap24xx()) {
499 omap2_enable_irq_lch(free_ch);
501 omap_enable_channel_irq(free_ch);
502 /* Clear the CSR register and IRQ status register */
503 OMAP_DMA_CSR_REG(free_ch) = 0x0;
504 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
507 *dma_ch_out = free_ch;
512 void omap_free_dma(int lch)
516 spin_lock_irqsave(&dma_chan_lock, flags);
517 if (dma_chan[lch].dev_id == -1) {
518 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
520 spin_unlock_irqrestore(&dma_chan_lock, flags);
523 dma_chan[lch].dev_id = -1;
524 dma_chan[lch].next_lch = -1;
525 dma_chan[lch].callback = NULL;
526 spin_unlock_irqrestore(&dma_chan_lock, flags);
528 if (cpu_class_is_omap1()) {
529 /* Disable all DMA interrupts for the channel. */
530 OMAP_DMA_CICR_REG(lch) = 0;
531 /* Make sure the DMA transfer is stopped. */
532 OMAP_DMA_CCR_REG(lch) = 0;
535 if (cpu_is_omap24xx()) {
537 /* Disable interrupts */
538 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
540 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
542 /* Clear the CSR register and IRQ status register */
543 OMAP_DMA_CSR_REG(lch) = 0x0;
545 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
547 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
549 /* Disable all DMA interrupts for the channel. */
550 OMAP_DMA_CICR_REG(lch) = 0;
552 /* Make sure the DMA transfer is stopped. */
553 OMAP_DMA_CCR_REG(lch) = 0;
559 * Clears any DMA state so the DMA engine is ready to restart with new buffers
560 * through omap_start_dma(). Any buffers in flight are discarded.
562 void omap_clear_dma(int lch)
566 local_irq_save(flags);
568 if (cpu_class_is_omap1()) {
570 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
572 /* Clear pending interrupts */
573 status = OMAP_DMA_CSR_REG(lch);
576 if (cpu_is_omap24xx()) {
578 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
579 for (i = 0; i < 0x44; i += 4)
580 omap_writel(0, lch_base + i);
583 local_irq_restore(flags);
586 void omap_start_dma(int lch)
588 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
589 int next_lch, cur_lch;
590 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
592 dma_chan_link_map[lch] = 1;
593 /* Set the link register of the first channel */
596 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
597 cur_lch = dma_chan[lch].next_lch;
599 next_lch = dma_chan[cur_lch].next_lch;
601 /* The loop case: we've been here already */
602 if (dma_chan_link_map[cur_lch])
604 /* Mark the current channel */
605 dma_chan_link_map[cur_lch] = 1;
608 omap_enable_channel_irq(cur_lch);
611 } while (next_lch != -1);
612 } else if (cpu_is_omap24xx()) {
613 /* Errata: Need to write lch even if not using chaining */
614 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
617 omap_enable_channel_irq(lch);
619 /* Errata: On ES2.0 BUFFERING disable must be set.
620 * This will always fail on ES1.0 */
621 if (cpu_is_omap24xx()) {
622 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
625 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
627 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
630 void omap_stop_dma(int lch)
632 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
633 int next_lch, cur_lch = lch;
634 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
636 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
638 /* The loop case: we've been here already */
639 if (dma_chan_link_map[cur_lch])
641 /* Mark the current channel */
642 dma_chan_link_map[cur_lch] = 1;
644 disable_lnk(cur_lch);
646 next_lch = dma_chan[cur_lch].next_lch;
648 } while (next_lch != -1);
653 /* Disable all interrupts on the channel */
654 if (cpu_class_is_omap1())
655 OMAP_DMA_CICR_REG(lch) = 0;
657 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
658 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
662 * Returns current physical source address for the given DMA channel.
663 * If the channel is running the caller must disable interrupts prior calling
664 * this function and process the returned value before re-enabling interrupt to
665 * prevent races with the interrupt handler. Note that in continuous mode there
666 * is a chance for CSSA_L register overflow inbetween the two reads resulting
667 * in incorrect return value.
669 dma_addr_t omap_get_dma_src_pos(int lch)
673 if (cpu_class_is_omap1())
674 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
675 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
677 if (cpu_is_omap24xx())
678 offset = OMAP_DMA_CSAC_REG(lch);
684 * Returns current physical destination address for the given DMA channel.
685 * If the channel is running the caller must disable interrupts prior calling
686 * this function and process the returned value before re-enabling interrupt to
687 * prevent races with the interrupt handler. Note that in continuous mode there
688 * is a chance for CDSA_L register overflow inbetween the two reads resulting
689 * in incorrect return value.
691 dma_addr_t omap_get_dma_dst_pos(int lch)
695 if (cpu_class_is_omap1())
696 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
697 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
699 if (cpu_is_omap24xx())
700 offset = OMAP2_DMA_CDSA_REG(lch);
706 * Returns current source transfer counting for the given DMA channel.
707 * Can be used to monitor the progress of a transfer inside a block.
708 * It must be called with disabled interrupts.
710 int omap_get_dma_src_addr_counter(int lch)
712 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
715 int omap_dma_running(void)
719 /* Check if LCD DMA is running */
720 if (cpu_is_omap16xx())
721 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
724 for (lch = 0; lch < dma_chan_count; lch++)
725 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
732 * lch_queue DMA will start right after lch_head one is finished.
733 * For this DMA link to start, you still need to start (see omap_start_dma)
734 * the first one. That will fire up the entire queue.
736 void omap_dma_link_lch (int lch_head, int lch_queue)
738 if (omap_dma_in_1510_mode()) {
739 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
744 if ((dma_chan[lch_head].dev_id == -1) ||
745 (dma_chan[lch_queue].dev_id == -1)) {
746 printk(KERN_ERR "omap_dma: trying to link "
747 "non requested channels\n");
751 dma_chan[lch_head].next_lch = lch_queue;
755 * Once the DMA queue is stopped, we can destroy it.
757 void omap_dma_unlink_lch (int lch_head, int lch_queue)
759 if (omap_dma_in_1510_mode()) {
760 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
765 if (dma_chan[lch_head].next_lch != lch_queue ||
766 dma_chan[lch_head].next_lch == -1) {
767 printk(KERN_ERR "omap_dma: trying to unlink "
768 "non linked channels\n");
773 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
774 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
775 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
776 "before unlinking\n");
780 dma_chan[lch_head].next_lch = -1;
783 /*----------------------------------------------------------------------------*/
785 #ifdef CONFIG_ARCH_OMAP1
787 static int omap1_dma_handle_ch(int ch)
791 if (enable_1510_mode && ch >= 6) {
792 csr = dma_chan[ch].saved_csr;
793 dma_chan[ch].saved_csr = 0;
795 csr = OMAP_DMA_CSR_REG(ch);
796 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
797 dma_chan[ch + 6].saved_csr = csr >> 7;
800 if ((csr & 0x3f) == 0)
802 if (unlikely(dma_chan[ch].dev_id == -1)) {
803 printk(KERN_WARNING "Spurious interrupt from DMA channel "
804 "%d (CSR %04x)\n", ch, csr);
807 if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
808 printk(KERN_WARNING "DMA timeout with device %d\n",
809 dma_chan[ch].dev_id);
810 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
811 printk(KERN_WARNING "DMA synchronization event drop occurred "
812 "with device %d\n", dma_chan[ch].dev_id);
813 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
814 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
815 if (likely(dma_chan[ch].callback != NULL))
816 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
820 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
821 struct pt_regs *regs)
823 int ch = ((int) dev_id) - 1;
829 handled_now += omap1_dma_handle_ch(ch);
830 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
831 handled_now += omap1_dma_handle_ch(ch + 6);
834 handled += handled_now;
837 return handled ? IRQ_HANDLED : IRQ_NONE;
841 #define omap1_dma_irq_handler NULL
844 #ifdef CONFIG_ARCH_OMAP2
846 static int omap2_dma_handle_ch(int ch)
848 u32 status = OMAP_DMA_CSR_REG(ch);
853 if (unlikely(dma_chan[ch].dev_id == -1))
855 /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
856 if (unlikely(status & OMAP_DMA_TOUT_IRQ))
857 printk(KERN_INFO "DMA timeout with device %d\n",
858 dma_chan[ch].dev_id);
859 if (unlikely(status & OMAP_DMA_DROP_IRQ))
861 "DMA synchronization event drop occurred with device "
862 "%d\n", dma_chan[ch].dev_id);
864 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
865 printk(KERN_INFO "DMA transaction error with device %d\n",
866 dma_chan[ch].dev_id);
868 OMAP_DMA_CSR_REG(ch) = 0x20;
870 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
871 /* ch in this function is from 0-31 while in register it is 1-32 */
873 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
875 if (likely(dma_chan[ch].callback != NULL))
876 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
881 /* STATUS register count is from 1-32 while our is 0-31 */
882 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
883 struct pt_regs *regs)
888 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
890 for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
891 int active = val & (1 << (i - 1));
893 omap2_dma_handle_ch(i - 1);
899 static struct irqaction omap24xx_dma_irq = {
901 .handler = omap2_dma_irq_handler,
902 .flags = SA_INTERRUPT
906 static struct irqaction omap24xx_dma_irq;
909 /*----------------------------------------------------------------------------*/
911 static struct lcd_dma_info {
914 void (* callback)(u16 status, void *data);
918 unsigned long addr, size;
919 int rotate, data_type, xres, yres;
928 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
932 lcd_dma.data_type = data_type;
933 lcd_dma.xres = fb_xres;
934 lcd_dma.yres = fb_yres;
937 void omap_set_lcd_dma_src_port(int port)
939 lcd_dma.src_port = port;
942 void omap_set_lcd_dma_ext_controller(int external)
944 lcd_dma.ext_ctrl = external;
947 void omap_set_lcd_dma_single_transfer(int single)
949 lcd_dma.single_transfer = single;
953 void omap_set_lcd_dma_b1_rotation(int rotate)
955 if (omap_dma_in_1510_mode()) {
956 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
960 lcd_dma.rotate = rotate;
963 void omap_set_lcd_dma_b1_mirror(int mirror)
965 if (omap_dma_in_1510_mode()) {
966 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
969 lcd_dma.mirror = mirror;
972 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
974 if (omap_dma_in_1510_mode()) {
975 printk(KERN_ERR "DMA virtual resulotion is not supported "
979 lcd_dma.vxres = vxres;
982 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
984 if (omap_dma_in_1510_mode()) {
985 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
988 lcd_dma.xscale = xscale;
989 lcd_dma.yscale = yscale;
992 static void set_b1_regs(void)
994 unsigned long top, bottom;
997 unsigned long en, fn;
1000 unsigned int xscale, yscale;
1002 switch (lcd_dma.data_type) {
1003 case OMAP_DMA_DATA_TYPE_S8:
1006 case OMAP_DMA_DATA_TYPE_S16:
1009 case OMAP_DMA_DATA_TYPE_S32:
1017 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1018 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1019 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1020 BUG_ON(vxres < lcd_dma.xres);
1021 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1022 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1023 switch (lcd_dma.rotate) {
1025 if (!lcd_dma.mirror) {
1026 top = PIXADDR(0, 0);
1027 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1028 /* 1510 DMA requires the bottom address to be 2 more
1029 * than the actual last memory access location. */
1030 if (omap_dma_in_1510_mode() &&
1031 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1033 ei = PIXSTEP(0, 0, 1, 0);
1034 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1036 top = PIXADDR(lcd_dma.xres - 1, 0);
1037 bottom = PIXADDR(0, lcd_dma.yres - 1);
1038 ei = PIXSTEP(1, 0, 0, 0);
1039 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1045 if (!lcd_dma.mirror) {
1046 top = PIXADDR(0, lcd_dma.yres - 1);
1047 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1048 ei = PIXSTEP(0, 1, 0, 0);
1049 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1051 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1052 bottom = PIXADDR(0, 0);
1053 ei = PIXSTEP(0, 1, 0, 0);
1054 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1060 if (!lcd_dma.mirror) {
1061 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1062 bottom = PIXADDR(0, 0);
1063 ei = PIXSTEP(1, 0, 0, 0);
1064 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1066 top = PIXADDR(0, lcd_dma.yres - 1);
1067 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1068 ei = PIXSTEP(0, 0, 1, 0);
1069 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1075 if (!lcd_dma.mirror) {
1076 top = PIXADDR(lcd_dma.xres - 1, 0);
1077 bottom = PIXADDR(0, lcd_dma.yres - 1);
1078 ei = PIXSTEP(0, 0, 0, 1);
1079 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1081 top = PIXADDR(0, 0);
1082 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1083 ei = PIXSTEP(0, 0, 0, 1);
1084 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1091 return; /* Supress warning about uninitialized vars */
1094 if (omap_dma_in_1510_mode()) {
1095 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1096 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1097 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1098 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1104 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1105 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1106 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1107 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1109 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1110 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1112 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1114 w |= lcd_dma.data_type;
1115 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1117 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1118 /* Always set the source port as SDRAM for now*/
1120 if (lcd_dma.callback != NULL)
1121 w |= 1 << 1; /* Block interrupt enable */
1124 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1126 if (!(lcd_dma.rotate || lcd_dma.mirror ||
1127 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1130 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1131 /* Set the double-indexed addressing mode */
1133 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1135 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1136 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1137 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1140 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
1141 struct pt_regs *regs)
1145 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1146 if (unlikely(!(w & (1 << 3)))) {
1147 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1152 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1154 if (lcd_dma.callback != NULL)
1155 lcd_dma.callback(w, lcd_dma.cb_data);
1160 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
1163 spin_lock_irq(&lcd_dma.lock);
1164 if (lcd_dma.reserved) {
1165 spin_unlock_irq(&lcd_dma.lock);
1166 printk(KERN_ERR "LCD DMA channel already reserved\n");
1170 lcd_dma.reserved = 1;
1171 spin_unlock_irq(&lcd_dma.lock);
1172 lcd_dma.callback = callback;
1173 lcd_dma.cb_data = data;
1175 lcd_dma.single_transfer = 0;
1181 lcd_dma.ext_ctrl = 0;
1182 lcd_dma.src_port = 0;
1187 void omap_free_lcd_dma(void)
1189 spin_lock(&lcd_dma.lock);
1190 if (!lcd_dma.reserved) {
1191 spin_unlock(&lcd_dma.lock);
1192 printk(KERN_ERR "LCD DMA is not reserved\n");
1196 if (!enable_1510_mode)
1197 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
1198 OMAP1610_DMA_LCD_CCR);
1199 lcd_dma.reserved = 0;
1200 spin_unlock(&lcd_dma.lock);
1203 void omap_enable_lcd_dma(void)
1207 /* Set the Enable bit only if an external controller is
1208 * connected. Otherwise the OMAP internal controller will
1209 * start the transfer when it gets enabled.
1211 if (enable_1510_mode || !lcd_dma.ext_ctrl)
1214 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1216 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1220 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1222 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1225 void omap_setup_lcd_dma(void)
1227 BUG_ON(lcd_dma.active);
1228 if (!enable_1510_mode) {
1229 /* Set some reasonable defaults */
1230 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
1231 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
1232 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
1235 if (!enable_1510_mode) {
1238 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1239 /* If DMA was already active set the end_prog bit to have
1240 * the programmed register set loaded into the active
1243 w |= 1 << 11; /* End_prog */
1244 if (!lcd_dma.single_transfer)
1245 w |= (3 << 8); /* Auto_init, repeat */
1246 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1250 void omap_stop_lcd_dma(void)
1255 if (enable_1510_mode || !lcd_dma.ext_ctrl)
1258 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1260 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1262 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1264 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1267 int omap_lcd_dma_ext_running(void)
1269 return lcd_dma.ext_ctrl && lcd_dma.active;
1272 /*----------------------------------------------------------------------------*/
1274 static int __init omap_init_dma(void)
1278 if (cpu_is_omap15xx()) {
1279 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
1281 enable_1510_mode = 1;
1282 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1283 printk(KERN_INFO "OMAP DMA hardware version %d\n",
1284 omap_readw(OMAP_DMA_HW_ID));
1285 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1286 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
1287 omap_readw(OMAP_DMA_CAPS_0_L),
1288 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
1289 omap_readw(OMAP_DMA_CAPS_1_L),
1290 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
1291 omap_readw(OMAP_DMA_CAPS_4));
1292 if (!enable_1510_mode) {
1295 /* Disable OMAP 3.0/3.1 compatibility mode. */
1296 w = omap_readw(OMAP_DMA_GSCR);
1298 omap_writew(w, OMAP_DMA_GSCR);
1299 dma_chan_count = 16;
1302 } else if (cpu_is_omap24xx()) {
1303 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1304 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1305 revision >> 4, revision & 0xf);
1306 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
1312 memset(&lcd_dma, 0, sizeof(lcd_dma));
1313 spin_lock_init(&lcd_dma.lock);
1314 spin_lock_init(&dma_chan_lock);
1315 memset(&dma_chan, 0, sizeof(dma_chan));
1317 for (ch = 0; ch < dma_chan_count; ch++) {
1319 dma_chan[ch].dev_id = -1;
1320 dma_chan[ch].next_lch = -1;
1322 if (ch >= 6 && enable_1510_mode)
1325 if (cpu_class_is_omap1()) {
1326 /* request_irq() doesn't like dev_id (ie. ch) being
1327 * zero, so we have to kludge around this. */
1328 r = request_irq(omap1_dma_irq[ch],
1329 omap1_dma_irq_handler, 0, "DMA",
1334 printk(KERN_ERR "unable to request IRQ %d "
1335 "for DMA (error %d)\n",
1336 omap1_dma_irq[ch], r);
1337 for (i = 0; i < ch; i++)
1338 free_irq(omap1_dma_irq[i],
1345 if (cpu_is_omap24xx())
1346 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1348 /* FIXME: Update LCD DMA to work on 24xx */
1349 if (cpu_class_is_omap1()) {
1350 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
1355 printk(KERN_ERR "unable to request IRQ for LCD DMA "
1357 for (i = 0; i < dma_chan_count; i++)
1358 free_irq(omap1_dma_irq[i], (void *) (i + 1));
1366 arch_initcall(omap_init_dma);
1368 EXPORT_SYMBOL(omap_get_dma_src_pos);
1369 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1370 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
1371 EXPORT_SYMBOL(omap_clear_dma);
1372 EXPORT_SYMBOL(omap_set_dma_priority);
1373 EXPORT_SYMBOL(omap_request_dma);
1374 EXPORT_SYMBOL(omap_free_dma);
1375 EXPORT_SYMBOL(omap_start_dma);
1376 EXPORT_SYMBOL(omap_stop_dma);
1377 EXPORT_SYMBOL(omap_enable_dma_irq);
1378 EXPORT_SYMBOL(omap_disable_dma_irq);
1380 EXPORT_SYMBOL(omap_set_dma_transfer_params);
1381 EXPORT_SYMBOL(omap_set_dma_color_mode);
1383 EXPORT_SYMBOL(omap_set_dma_src_params);
1384 EXPORT_SYMBOL(omap_set_dma_src_index);
1385 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
1386 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
1388 EXPORT_SYMBOL(omap_set_dma_dest_params);
1389 EXPORT_SYMBOL(omap_set_dma_dest_index);
1390 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
1391 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
1393 EXPORT_SYMBOL(omap_set_dma_params);
1395 EXPORT_SYMBOL(omap_dma_link_lch);
1396 EXPORT_SYMBOL(omap_dma_unlink_lch);
1398 EXPORT_SYMBOL(omap_request_lcd_dma);
1399 EXPORT_SYMBOL(omap_free_lcd_dma);
1400 EXPORT_SYMBOL(omap_enable_lcd_dma);
1401 EXPORT_SYMBOL(omap_setup_lcd_dma);
1402 EXPORT_SYMBOL(omap_stop_lcd_dma);
1403 EXPORT_SYMBOL(omap_lcd_dma_ext_running);
1404 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1405 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1406 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1407 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1408 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1409 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1410 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);