2 * linux/arch/arm/mm/proc-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv6 processor support.
12 #include <linux/linkage.h>
13 #include <asm/assembler.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/hardware/arm_scu.h>
16 #include <asm/procinfo.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define D_CACHE_LINE_SIZE 32
24 #define TTB_C (1 << 0)
25 #define TTB_S (1 << 1)
26 #define TTB_IMP (1 << 2)
27 #define TTB_RGN_NC (0 << 3)
28 #define TTB_RGN_WBWA (1 << 3)
29 #define TTB_RGN_WT (2 << 3)
30 #define TTB_RGN_WB (3 << 3)
32 ENTRY(cpu_v6_proc_init)
35 ENTRY(cpu_v6_proc_fin)
37 cpsid if @ disable interrupts
38 bl v6_flush_kern_cache_all
39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
40 bic r0, r0, #0x1000 @ ...i............
41 bic r0, r0, #0x0006 @ .............ca.
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
48 * Perform a soft reset of the system. Put the CPU into the
49 * same state as it would be if it had been reset, and branch
50 * to what would be the reset vector.
52 * - loc - location to jump to for soft reset
63 * Idle the processor (eg, wait for interrupt).
65 * IRQs are already disabled.
68 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
71 ENTRY(cpu_v6_dcache_clean_area)
72 #ifndef TLB_CAN_READ_FROM_L1_CACHE
73 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
74 add r0, r0, #D_CACHE_LINE_SIZE
75 subs r1, r1, #D_CACHE_LINE_SIZE
81 * cpu_arm926_switch_mm(pgd_phys, tsk)
83 * Set the translation table base pointer to be pgd_phys
85 * - pgd_phys - physical address of new TTB
88 * - we are not using split page tables
90 ENTRY(cpu_v6_switch_mm)
92 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
94 orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
96 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
97 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
98 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
99 mcr p15, 0, r1, c13, c0, 1 @ set context ID
103 * cpu_v6_set_pte(ptep, pte)
105 * Set a level 2 translation table entry.
107 * - ptep - pointer to level 2 translation table entry
108 * (hardware version is stored at -1024 bytes)
109 * - pte - PTE value to store
112 * YUWD APX AP1 AP0 SVC User
113 * 0xxx 0 0 0 no acc no acc
114 * 100x 1 0 1 r/o no acc
115 * 10x0 1 0 1 r/o no acc
116 * 1011 0 0 1 r/w no acc
121 ENTRY(cpu_v6_set_pte)
122 str r1, [r0], #-2048 @ linux version
124 bic r2, r1, #0x000003f0
125 bic r2, r2, #0x00000003
126 orr r2, r2, #PTE_EXT_AP0 | 2
129 tstne r1, #L_PTE_DIRTY
130 orreq r2, r2, #PTE_EXT_APX
133 orrne r2, r2, #PTE_EXT_AP1
134 tstne r2, #PTE_EXT_APX
135 bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0
138 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
141 orreq r2, r2, #PTE_EXT_XN
143 tst r1, #L_PTE_PRESENT
147 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
154 .asciz "Some Random V6 Processor"
157 .section ".text.init", #alloc, #execinstr
162 * Initialise TLB, Caches, and MMU state ready to switch the MMU
163 * on. Return in r0 the new CP15 C1 control register setting.
165 * We automatically detect if we have a Harvard cache, and use the
166 * Harvard cache control instructions insead of the unified cache
167 * control instructions.
169 * This should be able to cover all ARMv6 cores.
171 * It is assumed that:
172 * - cache type register is implemented
176 /* Set up the SCU on core 0 only */
177 mrc p15, 0, r0, c0, c0, 5 @ CPU core number
179 moveq r0, #0x10000000 @ SCU_BASE
180 orreq r0, r0, #0x00100000
181 ldreq r5, [r0, #SCU_CTRL]
183 streq r5, [r0, #SCU_CTRL]
185 #ifndef CONFIG_CPU_DCACHE_DISABLE
186 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
188 mcr p15, 0, r0, c1, c0, 1
193 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
194 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
195 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
196 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
197 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
198 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
200 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
202 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
204 mrc p15, 0, r0, c1, c0, 2
205 orr r0, r0, #(0xf << 20)
206 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
208 mrc p15, 0, r0, c1, c0, 0 @ read control register
209 ldr r5, v6_cr1_clear @ get mask for bits to clear
210 bic r0, r0, r5 @ clear bits them
211 ldr r5, v6_cr1_set @ get mask for bits to set
212 orr r0, r0, r5 @ set them
213 mov pc, lr @ return to head.S:__ret
217 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
218 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
219 * 0 110 0011 1.00 .111 1101 < we want
221 .type v6_cr1_clear, #object
222 .type v6_cr1_set, #object
228 .type v6_processor_functions, #object
229 ENTRY(v6_processor_functions)
231 .word cpu_v6_proc_init
232 .word cpu_v6_proc_fin
235 .word cpu_v6_dcache_clean_area
236 .word cpu_v6_switch_mm
238 .size v6_processor_functions, . - v6_processor_functions
240 .type cpu_arch_name, #object
243 .size cpu_arch_name, . - cpu_arch_name
245 .type cpu_elf_name, #object
248 .size cpu_elf_name, . - cpu_elf_name
251 .section ".proc.info.init", #alloc, #execinstr
254 * Match any ARMv6 processor core.
256 .type __v6_proc_info, #object
260 .long PMD_TYPE_SECT | \
261 PMD_SECT_BUFFERABLE | \
262 PMD_SECT_CACHEABLE | \
263 PMD_SECT_AP_WRITE | \
268 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA
270 .long v6_processor_functions
274 .size __v6_proc_info, . - __v6_proc_info