2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
4 * Heavily based on proc-arm926.S
5 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/linkage.h>
23 #include <linux/init.h>
24 #include <asm/assembler.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
29 #include <asm/ptrace.h>
30 #include "proc-macros.S"
33 * This is the maximum size of an area which will be invalidated
34 * using the single invalidate entry instructions. Anything larger
35 * than this, and we go for the whole cache.
37 * This value should be chosen such that we choose the cheapest
40 #define CACHE_DLIMIT 16384
43 * the cache line size of the I and D cache
45 #define CACHE_DLINESIZE 32
49 * cpu_feroceon_proc_init()
51 ENTRY(cpu_feroceon_proc_init)
55 * cpu_feroceon_proc_fin()
57 ENTRY(cpu_feroceon_proc_fin)
59 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
61 bl feroceon_flush_kern_cache_all
62 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
63 bic r0, r0, #0x1000 @ ...i............
64 bic r0, r0, #0x000e @ ............wca.
65 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 * cpu_feroceon_reset(loc)
71 * Perform a soft reset of the system. Put the CPU into the
72 * same state as it would be if it had been reset, and branch
73 * to what would be the reset vector.
75 * loc: location to jump to for soft reset
78 ENTRY(cpu_feroceon_reset)
80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
81 mcr p15, 0, ip, c7, c10, 4 @ drain WB
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
85 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
86 bic ip, ip, #0x000f @ ............wcam
87 bic ip, ip, #0x1100 @ ...i...s........
88 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
92 * cpu_feroceon_do_idle()
94 * Called with IRQs disabled
97 ENTRY(cpu_feroceon_do_idle)
99 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
104 * flush_user_cache_all()
106 * Clean and invalidate all cache entries in a particular
109 ENTRY(feroceon_flush_user_cache_all)
113 * flush_kern_cache_all()
115 * Clean and invalidate the entire cache.
117 ENTRY(feroceon_flush_kern_cache_all)
121 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
124 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
125 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
129 * flush_user_cache_range(start, end, flags)
131 * Clean and invalidate a range of cache entries in the
132 * specified address range.
134 * - start - start address (inclusive)
135 * - end - end address (exclusive)
136 * - flags - vm_flags describing address space
138 ENTRY(feroceon_flush_user_cache_range)
140 sub r3, r1, r0 @ calculate total size
141 cmp r3, #CACHE_DLIMIT
142 bgt __flush_whole_cache
144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
146 add r0, r0, #CACHE_DLINESIZE
147 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
149 add r0, r0, #CACHE_DLINESIZE
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
157 * coherent_kern_range(start, end)
159 * Ensure coherency between the Icache and the Dcache in the
160 * region described by start, end. If you have non-snooping
161 * Harvard caches, you need to implement this function.
163 * - start - virtual start address
164 * - end - virtual end address
166 ENTRY(feroceon_coherent_kern_range)
170 * coherent_user_range(start, end)
172 * Ensure coherency between the Icache and the Dcache in the
173 * region described by start, end. If you have non-snooping
174 * Harvard caches, you need to implement this function.
176 * - start - virtual start address
177 * - end - virtual end address
179 ENTRY(feroceon_coherent_user_range)
180 bic r0, r0, #CACHE_DLINESIZE - 1
181 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
182 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
183 add r0, r0, #CACHE_DLINESIZE
186 mcr p15, 0, r0, c7, c10, 4 @ drain WB
190 * flush_kern_dcache_page(void *page)
192 * Ensure no D cache aliasing occurs, either with itself or
195 * - addr - page aligned address
197 ENTRY(feroceon_flush_kern_dcache_page)
199 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
200 add r0, r0, #CACHE_DLINESIZE
204 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
205 mcr p15, 0, r0, c7, c10, 4 @ drain WB
209 * dma_inv_range(start, end)
211 * Invalidate (discard) the specified virtual address range.
212 * May not write back any entries. If 'start' or 'end'
213 * are not cache line aligned, those lines must be written
216 * - start - virtual start address
217 * - end - virtual end address
221 ENTRY(feroceon_dma_inv_range)
222 tst r0, #CACHE_DLINESIZE - 1
223 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
224 tst r1, #CACHE_DLINESIZE - 1
225 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
226 bic r0, r0, #CACHE_DLINESIZE - 1
227 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
228 add r0, r0, #CACHE_DLINESIZE
231 mcr p15, 0, r0, c7, c10, 4 @ drain WB
235 * dma_clean_range(start, end)
237 * Clean the specified virtual address range.
239 * - start - virtual start address
240 * - end - virtual end address
244 ENTRY(feroceon_dma_clean_range)
245 bic r0, r0, #CACHE_DLINESIZE - 1
246 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
247 add r0, r0, #CACHE_DLINESIZE
250 mcr p15, 0, r0, c7, c10, 4 @ drain WB
254 * dma_flush_range(start, end)
256 * Clean and invalidate the specified virtual address range.
258 * - start - virtual start address
259 * - end - virtual end address
261 ENTRY(feroceon_dma_flush_range)
262 bic r0, r0, #CACHE_DLINESIZE - 1
264 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
265 add r0, r0, #CACHE_DLINESIZE
268 mcr p15, 0, r0, c7, c10, 4 @ drain WB
271 ENTRY(feroceon_cache_fns)
272 .long feroceon_flush_kern_cache_all
273 .long feroceon_flush_user_cache_all
274 .long feroceon_flush_user_cache_range
275 .long feroceon_coherent_kern_range
276 .long feroceon_coherent_user_range
277 .long feroceon_flush_kern_dcache_page
278 .long feroceon_dma_inv_range
279 .long feroceon_dma_clean_range
280 .long feroceon_dma_flush_range
282 ENTRY(cpu_feroceon_dcache_clean_area)
283 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
284 add r0, r0, #CACHE_DLINESIZE
285 subs r1, r1, #CACHE_DLINESIZE
287 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 /* =============================== PageTable ============================== */
293 * cpu_feroceon_switch_mm(pgd)
295 * Set the translation base pointer to be as described by pgd.
297 * pgd: new page tables
300 ENTRY(cpu_feroceon_switch_mm)
303 @ && 'Clean & Invalidate whole DCache'
304 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
306 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
307 mcr p15, 0, ip, c7, c10, 4 @ drain WB
308 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
309 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
314 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
316 * Set a PTE and flush it out
319 ENTRY(cpu_feroceon_set_pte_ext)
321 str r1, [r0], #-2048 @ linux version
323 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
325 bic r2, r1, #PTE_SMALL_AP_MASK
326 bic r2, r2, #PTE_TYPE_MASK
327 orr r2, r2, #PTE_TYPE_SMALL
329 tst r1, #L_PTE_USER @ User?
330 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
332 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
333 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
335 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
338 str r2, [r0] @ hardware version
340 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
341 mcr p15, 0, r0, c7, c10, 4 @ drain WB
347 .type __feroceon_setup, #function
350 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
351 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
353 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
356 adr r5, feroceon_crval
358 mrc p15, 0, r0, c1, c0 @ get control register v4
362 .size __feroceon_setup, . - __feroceon_setup
366 * .RVI ZFRS BLDP WCAM
367 * .011 0001 ..11 0101
370 .type feroceon_crval, #object
372 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
377 * Purpose : Function pointers used to access above functions - all calls
380 .type feroceon_processor_functions, #object
381 feroceon_processor_functions:
382 .word v5t_early_abort
384 .word cpu_feroceon_proc_init
385 .word cpu_feroceon_proc_fin
386 .word cpu_feroceon_reset
387 .word cpu_feroceon_do_idle
388 .word cpu_feroceon_dcache_clean_area
389 .word cpu_feroceon_switch_mm
390 .word cpu_feroceon_set_pte_ext
391 .size feroceon_processor_functions, . - feroceon_processor_functions
395 .type cpu_arch_name, #object
398 .size cpu_arch_name, . - cpu_arch_name
400 .type cpu_elf_name, #object
403 .size cpu_elf_name, . - cpu_elf_name
405 .type cpu_feroceon_name, #object
408 .size cpu_feroceon_name, . - cpu_feroceon_name
412 .section ".proc.info.init", #alloc, #execinstr
414 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
415 .type __feroceon_old_id_proc_info,#object
416 __feroceon_old_id_proc_info:
419 .long PMD_TYPE_SECT | \
420 PMD_SECT_BUFFERABLE | \
421 PMD_SECT_CACHEABLE | \
423 PMD_SECT_AP_WRITE | \
425 .long PMD_TYPE_SECT | \
427 PMD_SECT_AP_WRITE | \
432 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
433 .long cpu_feroceon_name
434 .long feroceon_processor_functions
437 .long feroceon_cache_fns
438 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
441 .type __feroceon_proc_info,#object
442 __feroceon_proc_info:
445 .long PMD_TYPE_SECT | \
446 PMD_SECT_BUFFERABLE | \
447 PMD_SECT_CACHEABLE | \
449 PMD_SECT_AP_WRITE | \
451 .long PMD_TYPE_SECT | \
453 PMD_SECT_AP_WRITE | \
458 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
459 .long cpu_feroceon_name
460 .long feroceon_processor_functions
463 .long feroceon_cache_fns
464 .size __feroceon_proc_info, . - __feroceon_proc_info