2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
4 * Heavily based on proc-arm926.S
5 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/linkage.h>
23 #include <linux/init.h>
24 #include <asm/assembler.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
29 #include <asm/ptrace.h>
30 #include "proc-macros.S"
33 * This is the maximum size of an area which will be invalidated
34 * using the single invalidate entry instructions. Anything larger
35 * than this, and we go for the whole cache.
37 * This value should be chosen such that we choose the cheapest
40 #define CACHE_DLIMIT 16384
43 * the cache line size of the I and D cache
45 #define CACHE_DLINESIZE 32
54 .word __cache_params_loc
57 * cpu_feroceon_proc_init()
59 ENTRY(cpu_feroceon_proc_init)
60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
61 ldr r1, __cache_params
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
65 movne r3, #((4 - 1) << 30) @ 4-way
68 mov r2, r2, lsl r0 @ actual cache size
69 movne r2, r2, lsr #2 @ turned into # of sets
75 * cpu_feroceon_proc_fin()
77 ENTRY(cpu_feroceon_proc_fin)
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
81 bl feroceon_flush_kern_cache_all
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 * cpu_feroceon_reset(loc)
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
95 * loc: location to jump to for soft reset
98 ENTRY(cpu_feroceon_reset)
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
112 * cpu_feroceon_do_idle()
114 * Called with IRQs disabled
117 ENTRY(cpu_feroceon_do_idle)
119 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
124 * flush_user_cache_all()
126 * Clean and invalidate all cache entries in a particular
130 ENTRY(feroceon_flush_user_cache_all)
134 * flush_kern_cache_all()
136 * Clean and invalidate the entire cache.
138 ENTRY(feroceon_flush_kern_cache_all)
142 ldr r1, __cache_params
145 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
146 subs ip, ip, #(1 << 30) @ next way
148 subs r1, r1, #(1 << 5) @ next set
153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
154 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
158 * flush_user_cache_range(start, end, flags)
160 * Clean and invalidate a range of cache entries in the
161 * specified address range.
163 * - start - start address (inclusive)
164 * - end - end address (exclusive)
165 * - flags - vm_flags describing address space
168 ENTRY(feroceon_flush_user_cache_range)
169 sub r3, r1, r0 @ calculate total size
170 cmp r3, #CACHE_DLIMIT
171 bgt __flush_whole_cache
173 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 add r0, r0, #CACHE_DLINESIZE
183 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
187 * coherent_kern_range(start, end)
189 * Ensure coherency between the Icache and the Dcache in the
190 * region described by start, end. If you have non-snooping
191 * Harvard caches, you need to implement this function.
193 * - start - virtual start address
194 * - end - virtual end address
197 ENTRY(feroceon_coherent_kern_range)
201 * coherent_user_range(start, end)
203 * Ensure coherency between the Icache and the Dcache in the
204 * region described by start, end. If you have non-snooping
205 * Harvard caches, you need to implement this function.
207 * - start - virtual start address
208 * - end - virtual end address
210 ENTRY(feroceon_coherent_user_range)
211 bic r0, r0, #CACHE_DLINESIZE - 1
212 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
213 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
214 add r0, r0, #CACHE_DLINESIZE
217 mcr p15, 0, r0, c7, c10, 4 @ drain WB
221 * flush_kern_dcache_page(void *page)
223 * Ensure no D cache aliasing occurs, either with itself or
226 * - addr - page aligned address
229 ENTRY(feroceon_flush_kern_dcache_page)
231 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
232 add r0, r0, #CACHE_DLINESIZE
236 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
237 mcr p15, 0, r0, c7, c10, 4 @ drain WB
241 * dma_inv_range(start, end)
243 * Invalidate (discard) the specified virtual address range.
244 * May not write back any entries. If 'start' or 'end'
245 * are not cache line aligned, those lines must be written
248 * - start - virtual start address
249 * - end - virtual end address
254 ENTRY(feroceon_dma_inv_range)
255 tst r0, #CACHE_DLINESIZE - 1
256 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
257 tst r1, #CACHE_DLINESIZE - 1
258 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
259 bic r0, r0, #CACHE_DLINESIZE - 1
260 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
261 add r0, r0, #CACHE_DLINESIZE
264 mcr p15, 0, r0, c7, c10, 4 @ drain WB
268 * dma_clean_range(start, end)
270 * Clean the specified virtual address range.
272 * - start - virtual start address
273 * - end - virtual end address
278 ENTRY(feroceon_dma_clean_range)
279 bic r0, r0, #CACHE_DLINESIZE - 1
280 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
281 add r0, r0, #CACHE_DLINESIZE
284 mcr p15, 0, r0, c7, c10, 4 @ drain WB
288 * dma_flush_range(start, end)
290 * Clean and invalidate the specified virtual address range.
292 * - start - virtual start address
293 * - end - virtual end address
296 ENTRY(feroceon_dma_flush_range)
297 bic r0, r0, #CACHE_DLINESIZE - 1
298 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
299 add r0, r0, #CACHE_DLINESIZE
302 mcr p15, 0, r0, c7, c10, 4 @ drain WB
305 ENTRY(feroceon_cache_fns)
306 .long feroceon_flush_kern_cache_all
307 .long feroceon_flush_user_cache_all
308 .long feroceon_flush_user_cache_range
309 .long feroceon_coherent_kern_range
310 .long feroceon_coherent_user_range
311 .long feroceon_flush_kern_dcache_page
312 .long feroceon_dma_inv_range
313 .long feroceon_dma_clean_range
314 .long feroceon_dma_flush_range
317 ENTRY(cpu_feroceon_dcache_clean_area)
318 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
319 add r0, r0, #CACHE_DLINESIZE
320 subs r1, r1, #CACHE_DLINESIZE
322 mcr p15, 0, r0, c7, c10, 4 @ drain WB
325 /* =============================== PageTable ============================== */
328 * cpu_feroceon_switch_mm(pgd)
330 * Set the translation base pointer to be as described by pgd.
332 * pgd: new page tables
335 ENTRY(cpu_feroceon_switch_mm)
338 * Note: we wish to call __flush_whole_cache but we need to preserve
339 * lr to do so. The only way without touching main memory is to
340 * use r2 which is normally used to test the VM_EXEC flag, and
341 * compensate locally for the skipped ops if it is not set.
343 mov r2, lr @ abuse r2 to preserve lr
344 bl __flush_whole_cache
345 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
347 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
348 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
350 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
351 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
358 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
360 * Set a PTE and flush it out
363 ENTRY(cpu_feroceon_set_pte_ext)
365 str r1, [r0], #-2048 @ linux version
367 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
369 bic r2, r1, #PTE_SMALL_AP_MASK
370 bic r2, r2, #PTE_TYPE_MASK
371 orr r2, r2, #PTE_TYPE_SMALL
373 tst r1, #L_PTE_USER @ User?
374 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
376 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
377 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
379 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
382 str r2, [r0] @ hardware version
384 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
385 mcr p15, 0, r0, c7, c10, 4 @ drain WB
391 .type __feroceon_setup, #function
394 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
395 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
400 adr r5, feroceon_crval
402 mrc p15, 0, r0, c1, c0 @ get control register v4
406 .size __feroceon_setup, . - __feroceon_setup
410 * .RVI ZFRS BLDP WCAM
411 * .011 0001 ..11 0101
414 .type feroceon_crval, #object
416 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
421 * Purpose : Function pointers used to access above functions - all calls
424 .type feroceon_processor_functions, #object
425 feroceon_processor_functions:
426 .word v5t_early_abort
428 .word cpu_feroceon_proc_init
429 .word cpu_feroceon_proc_fin
430 .word cpu_feroceon_reset
431 .word cpu_feroceon_do_idle
432 .word cpu_feroceon_dcache_clean_area
433 .word cpu_feroceon_switch_mm
434 .word cpu_feroceon_set_pte_ext
435 .size feroceon_processor_functions, . - feroceon_processor_functions
439 .type cpu_arch_name, #object
442 .size cpu_arch_name, . - cpu_arch_name
444 .type cpu_elf_name, #object
447 .size cpu_elf_name, . - cpu_elf_name
449 .type cpu_feroceon_name, #object
452 .size cpu_feroceon_name, . - cpu_feroceon_name
454 .type cpu_88fr531_name, #object
456 .asciz "Feroceon 88FR531-vd"
457 .size cpu_88fr531_name, . - cpu_88fr531_name
461 .section ".proc.info.init", #alloc, #execinstr
463 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
464 .type __feroceon_old_id_proc_info,#object
465 __feroceon_old_id_proc_info:
468 .long PMD_TYPE_SECT | \
469 PMD_SECT_BUFFERABLE | \
470 PMD_SECT_CACHEABLE | \
472 PMD_SECT_AP_WRITE | \
474 .long PMD_TYPE_SECT | \
476 PMD_SECT_AP_WRITE | \
481 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
482 .long cpu_feroceon_name
483 .long feroceon_processor_functions
485 .long feroceon_user_fns
486 .long feroceon_cache_fns
487 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
490 .type __88fr531_proc_info,#object
494 .long PMD_TYPE_SECT | \
495 PMD_SECT_BUFFERABLE | \
496 PMD_SECT_CACHEABLE | \
498 PMD_SECT_AP_WRITE | \
500 .long PMD_TYPE_SECT | \
502 PMD_SECT_AP_WRITE | \
507 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
508 .long cpu_88fr531_name
509 .long feroceon_processor_functions
511 .long feroceon_user_fns
512 .long feroceon_cache_fns
513 .size __88fr531_proc_info, . - __88fr531_proc_info