2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * These are the low level assembler for performing cache and TLB
23 * functions on the arm1020e.
25 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 #include <linux/linkage.h>
28 #include <linux/config.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/pgtable.h>
33 #include <asm/procinfo.h>
34 #include <asm/ptrace.h>
37 * This is the maximum size of an area which will be invalidated
38 * using the single invalidate entry instructions. Anything larger
39 * than this, and we go for the whole cache.
41 * This value should be chosen such that we choose the cheapest
44 #define MAX_AREA_SIZE 32768
47 * The size of one data cache line.
49 #define CACHE_DLINESIZE 32
52 * The number of data cache segments.
54 #define CACHE_DSEGMENTS 16
57 * The number of lines in a cache segment.
59 #define CACHE_DENTRIES 64
62 * This is the size at which it becomes more efficient to
63 * clean the whole cache, rather than using the individual
64 * cache line maintainence instructions.
66 #define CACHE_DLIMIT 32768
70 * cpu_arm1020e_proc_init()
72 ENTRY(cpu_arm1020e_proc_init)
76 * cpu_arm1020e_proc_fin()
78 ENTRY(cpu_arm1020e_proc_fin)
80 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
82 bl arm1020e_flush_kern_cache_all
83 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
84 bic r0, r0, #0x1000 @ ...i............
85 bic r0, r0, #0x000e @ ............wca.
86 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 * cpu_arm1020e_reset(loc)
92 * Perform a soft reset of the system. Put the CPU into the
93 * same state as it would be if it had been reset, and branch
94 * to what would be the reset vector.
96 * loc: location to jump to for soft reset
99 ENTRY(cpu_arm1020e_reset)
101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
105 bic ip, ip, #0x000f @ ............wcam
106 bic ip, ip, #0x1100 @ ...i...s........
107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
111 * cpu_arm1020e_do_idle()
114 ENTRY(cpu_arm1020e_do_idle)
115 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 /* ================================= CACHE ================================ */
122 * flush_user_cache_all()
124 * Invalidate all cache entries in a particular address
127 ENTRY(arm1020e_flush_user_cache_all)
130 * flush_kern_cache_all()
132 * Clean and invalidate the entire cache.
134 ENTRY(arm1020e_flush_kern_cache_all)
138 #ifndef CONFIG_CPU_DCACHE_DISABLE
139 mcr p15, 0, ip, c7, c10, 4 @ drain WB
140 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
141 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
142 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
143 subs r3, r3, #1 << 26
144 bcs 2b @ entries 63 to 0
146 bcs 1b @ segments 15 to 0
149 #ifndef CONFIG_CPU_ICACHE_DISABLE
150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
156 * flush_user_cache_range(start, end, flags)
158 * Invalidate a range of cache entries in the specified
161 * - start - start address (inclusive)
162 * - end - end address (exclusive)
163 * - flags - vm_flags for this space
165 ENTRY(arm1020e_flush_user_cache_range)
167 sub r3, r1, r0 @ calculate total size
168 cmp r3, #CACHE_DLIMIT
169 bhs __flush_whole_cache
171 #ifndef CONFIG_CPU_DCACHE_DISABLE
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
173 add r0, r0, #CACHE_DLINESIZE
178 #ifndef CONFIG_CPU_ICACHE_DISABLE
179 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
181 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
185 * coherent_kern_range(start, end)
187 * Ensure coherency between the Icache and the Dcache in the
188 * region described by start. If you have non-snooping
189 * Harvard caches, you need to implement this function.
191 * - start - virtual start address
192 * - end - virtual end address
194 ENTRY(arm1020e_coherent_kern_range)
197 * coherent_user_range(start, end)
199 * Ensure coherency between the Icache and the Dcache in the
200 * region described by start. If you have non-snooping
201 * Harvard caches, you need to implement this function.
203 * - start - virtual start address
204 * - end - virtual end address
206 ENTRY(arm1020e_coherent_user_range)
208 bic r0, r0, #CACHE_DLINESIZE - 1
210 #ifndef CONFIG_CPU_DCACHE_DISABLE
211 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
213 #ifndef CONFIG_CPU_ICACHE_DISABLE
214 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
216 add r0, r0, #CACHE_DLINESIZE
219 mcr p15, 0, ip, c7, c10, 4 @ drain WB
223 * flush_kern_dcache_page(void *page)
225 * Ensure no D cache aliasing occurs, either with itself or
228 * - page - page aligned address
230 ENTRY(arm1020e_flush_kern_dcache_page)
232 #ifndef CONFIG_CPU_DCACHE_DISABLE
234 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
235 add r0, r0, #CACHE_DLINESIZE
239 mcr p15, 0, ip, c7, c10, 4 @ drain WB
243 * dma_inv_range(start, end)
245 * Invalidate (discard) the specified virtual address range.
246 * May not write back any entries. If 'start' or 'end'
247 * are not cache line aligned, those lines must be written
250 * - start - virtual start address
251 * - end - virtual end address
255 ENTRY(arm1020e_dma_inv_range)
257 #ifndef CONFIG_CPU_DCACHE_DISABLE
258 tst r0, #CACHE_DLINESIZE - 1
259 bic r0, r0, #CACHE_DLINESIZE - 1
260 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
261 tst r1, #CACHE_DLINESIZE - 1
262 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
263 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
264 add r0, r0, #CACHE_DLINESIZE
268 mcr p15, 0, ip, c7, c10, 4 @ drain WB
272 * dma_clean_range(start, end)
274 * Clean the specified virtual address range.
276 * - start - virtual start address
277 * - end - virtual end address
281 ENTRY(arm1020e_dma_clean_range)
283 #ifndef CONFIG_CPU_DCACHE_DISABLE
284 bic r0, r0, #CACHE_DLINESIZE - 1
285 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
286 add r0, r0, #CACHE_DLINESIZE
290 mcr p15, 0, ip, c7, c10, 4 @ drain WB
294 * dma_flush_range(start, end)
296 * Clean and invalidate the specified virtual address range.
298 * - start - virtual start address
299 * - end - virtual end address
301 ENTRY(arm1020e_dma_flush_range)
303 #ifndef CONFIG_CPU_DCACHE_DISABLE
304 bic r0, r0, #CACHE_DLINESIZE - 1
305 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
306 add r0, r0, #CACHE_DLINESIZE
310 mcr p15, 0, ip, c7, c10, 4 @ drain WB
313 ENTRY(arm1020e_cache_fns)
314 .long arm1020e_flush_kern_cache_all
315 .long arm1020e_flush_user_cache_all
316 .long arm1020e_flush_user_cache_range
317 .long arm1020e_coherent_kern_range
318 .long arm1020e_coherent_user_range
319 .long arm1020e_flush_kern_dcache_page
320 .long arm1020e_dma_inv_range
321 .long arm1020e_dma_clean_range
322 .long arm1020e_dma_flush_range
325 ENTRY(cpu_arm1020e_dcache_clean_area)
326 #ifndef CONFIG_CPU_DCACHE_DISABLE
328 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
329 add r0, r0, #CACHE_DLINESIZE
330 subs r1, r1, #CACHE_DLINESIZE
335 /* =============================== PageTable ============================== */
338 * cpu_arm1020e_switch_mm(pgd)
340 * Set the translation base pointer to be as described by pgd.
342 * pgd: new page tables
345 ENTRY(cpu_arm1020e_switch_mm)
346 #ifndef CONFIG_CPU_DCACHE_DISABLE
347 mcr p15, 0, r3, c7, c10, 4
348 mov r1, #0xF @ 16 segments
349 1: mov r3, #0x3F @ 64 entries
350 2: mov ip, r3, LSL #26 @ shift up entry
351 orr ip, ip, r1, LSL #5 @ shift in/up index
352 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
356 bge 2b @ entries 3F to 0
359 bge 1b @ segments 15 to 0
363 #ifndef CONFIG_CPU_ICACHE_DISABLE
364 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
366 mcr p15, 0, r1, c7, c10, 4 @ drain WB
367 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
368 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
372 * cpu_arm1020e_set_pte(ptep, pte)
374 * Set a PTE and flush it out
377 ENTRY(cpu_arm1020e_set_pte)
378 str r1, [r0], #-2048 @ linux version
380 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
382 bic r2, r1, #PTE_SMALL_AP_MASK
383 bic r2, r2, #PTE_TYPE_MASK
384 orr r2, r2, #PTE_TYPE_SMALL
386 tst r1, #L_PTE_USER @ User?
387 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
389 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
390 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
392 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
395 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
396 eor r3, r1, #0x0a @ C & small page?
400 str r2, [r0] @ hardware version
402 #ifndef CONFIG_CPU_DCACHE_DISABLE
403 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
409 .type __arm1020e_setup, #function
412 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
413 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
414 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
415 mrc p15, 0, r0, c1, c0 @ get control register v4
416 ldr r5, arm1020e_cr1_clear
418 ldr r5, arm1020e_cr1_set
420 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
421 orr r0, r0, #0x4000 @ .R.. .... .... ....
424 .size __arm1020e_setup, . - __arm1020e_setup
428 * .RVI ZFRS BLDP WCAM
429 * .011 1001 ..11 0101
431 .type arm1020e_cr1_clear, #object
432 .type arm1020e_cr1_set, #object
441 * Purpose : Function pointers used to access above functions - all calls
444 .type arm1020e_processor_functions, #object
445 arm1020e_processor_functions:
446 .word v4t_early_abort
447 .word cpu_arm1020e_proc_init
448 .word cpu_arm1020e_proc_fin
449 .word cpu_arm1020e_reset
450 .word cpu_arm1020e_do_idle
451 .word cpu_arm1020e_dcache_clean_area
452 .word cpu_arm1020e_switch_mm
453 .word cpu_arm1020e_set_pte
454 .size arm1020e_processor_functions, . - arm1020e_processor_functions
458 .type cpu_arch_name, #object
461 .size cpu_arch_name, . - cpu_arch_name
463 .type cpu_elf_name, #object
466 .size cpu_elf_name, . - cpu_elf_name
468 .type cpu_arm1020e_name, #object
471 #ifndef CONFIG_CPU_ICACHE_DISABLE
474 #ifndef CONFIG_CPU_DCACHE_DISABLE
476 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
482 #ifndef CONFIG_CPU_BPREDICT_DISABLE
485 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
489 .size cpu_arm1020e_name, . - cpu_arm1020e_name
493 .section ".proc.info.init", #alloc, #execinstr
495 .type __arm1020e_proc_info,#object
496 __arm1020e_proc_info:
497 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
499 .long PMD_TYPE_SECT | \
501 PMD_SECT_AP_WRITE | \
506 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
507 .long cpu_arm1020e_name
508 .long arm1020e_processor_functions
511 .long arm1020e_cache_fns
512 .size __arm1020e_proc_info, . - __arm1020e_proc_info