1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
25 Say Y if you want support for the ARM610 processor.
30 bool "Support ARM7TDMI processor"
35 A 32-bit RISC microprocessor based on the ARM7 processor core
36 which has no memory control unit and cache.
38 Say Y if you want support for the ARM7TDMI processor.
43 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
44 default y if ARCH_CLPS7500
49 select CPU_COPY_V3 if MMU
50 select CPU_TLB_V3 if MMU
52 A 32-bit RISC microprocessor based on the ARM7 processor core
53 designed by Advanced RISC Machines Ltd. The ARM710 is the
54 successor to the ARM610 processor. It was released in
55 July 1994 by VLSI Technology Inc.
57 Say Y if you want support for the ARM710 processor.
62 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
63 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
69 select CPU_COPY_V4WT if MMU
70 select CPU_TLB_V4WT if MMU
72 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
73 MMU built around an ARM7TDMI core.
75 Say Y if you want support for the ARM720T processor.
80 bool "Support ARM740T processor" if ARCH_INTEGRATOR
83 select CPU_CACHE_V3 # although the core is v4t
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
90 Say Y if you want support for the ARM740T processor.
95 bool "Support ARM9TDMI processor"
100 A 32-bit RISC microprocessor based on the ARM9 processor core
101 which has no memory control unit and cache.
103 Say Y if you want support for the ARM9TDMI processor.
108 bool "Support ARM920T processor"
109 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
110 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
113 select CPU_CACHE_V4WT
114 select CPU_CACHE_VIVT
116 select CPU_COPY_V4WB if MMU
117 select CPU_TLB_V4WBI if MMU
119 The ARM920T is licensed to be produced by numerous vendors,
120 and is used in the Maverick EP9312 and the Samsung S3C2410.
122 More information on the Maverick EP9312 at
123 <http://linuxdevices.com/products/PD2382866068.html>.
125 Say Y if you want support for the ARM920T processor.
130 bool "Support ARM922T processor" if ARCH_INTEGRATOR
131 depends on ARCH_LH7A40X || ARCH_INTEGRATOR
132 default y if ARCH_LH7A40X
135 select CPU_CACHE_V4WT
136 select CPU_CACHE_VIVT
138 select CPU_COPY_V4WB if MMU
139 select CPU_TLB_V4WBI if MMU
141 The ARM922T is a version of the ARM920T, but with smaller
142 instruction and data caches. It is used in Altera's
143 Excalibur XA device family.
145 Say Y if you want support for the ARM922T processor.
150 bool "Support ARM925T processor" if ARCH_OMAP1
151 depends on ARCH_OMAP15XX
152 default y if ARCH_OMAP15XX
155 select CPU_CACHE_V4WT
156 select CPU_CACHE_VIVT
158 select CPU_COPY_V4WB if MMU
159 select CPU_TLB_V4WBI if MMU
161 The ARM925T is a mix between the ARM920T and ARM926T, but with
162 different instruction and data caches. It is used in TI's OMAP
165 Say Y if you want support for the ARM925T processor.
170 bool "Support ARM926T processor"
171 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
172 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
174 select CPU_ABRT_EV5TJ
175 select CPU_CACHE_VIVT
177 select CPU_COPY_V4WB if MMU
178 select CPU_TLB_V4WBI if MMU
180 This is a variant of the ARM920. It has slightly different
181 instruction sequences for cache and TLB operations. Curiously,
182 there is no documentation on it at the ARM corporate website.
184 Say Y if you want support for the ARM926T processor.
187 # ARM1020 - needs validating
189 bool "Support ARM1020T (rev 0) processor"
190 depends on ARCH_INTEGRATOR
193 select CPU_CACHE_V4WT
194 select CPU_CACHE_VIVT
196 select CPU_COPY_V4WB if MMU
197 select CPU_TLB_V4WBI if MMU
199 The ARM1020 is the 32K cached version of the ARM10 processor,
200 with an addition of a floating-point unit.
202 Say Y if you want support for the ARM1020 processor.
205 # ARM1020E - needs validating
207 bool "Support ARM1020E processor"
208 depends on ARCH_INTEGRATOR
211 select CPU_CACHE_V4WT
212 select CPU_CACHE_VIVT
214 select CPU_COPY_V4WB if MMU
215 select CPU_TLB_V4WBI if MMU
220 bool "Support ARM1022E processor"
221 depends on ARCH_INTEGRATOR
224 select CPU_CACHE_VIVT
226 select CPU_COPY_V4WB if MMU # can probably do better
227 select CPU_TLB_V4WBI if MMU
229 The ARM1022E is an implementation of the ARMv5TE architecture
230 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
231 embedded trace macrocell, and a floating-point unit.
233 Say Y if you want support for the ARM1022E processor.
238 bool "Support ARM1026EJ-S processor"
239 depends on ARCH_INTEGRATOR
241 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
242 select CPU_CACHE_VIVT
244 select CPU_COPY_V4WB if MMU # can probably do better
245 select CPU_TLB_V4WBI if MMU
247 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
248 based upon the ARM10 integer core.
250 Say Y if you want support for the ARM1026EJ-S processor.
255 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
256 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
257 select CPU_32v3 if ARCH_RPC
258 select CPU_32v4 if !ARCH_RPC
260 select CPU_CACHE_V4WB
261 select CPU_CACHE_VIVT
263 select CPU_COPY_V4WB if MMU
264 select CPU_TLB_V4WB if MMU
266 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
267 is available at five speeds ranging from 100 MHz to 233 MHz.
268 More information is available at
269 <http://developer.intel.com/design/strong/sa110.htm>.
271 Say Y if you want support for the SA-110 processor.
277 depends on ARCH_SA1100
281 select CPU_CACHE_V4WB
282 select CPU_CACHE_VIVT
284 select CPU_TLB_V4WB if MMU
289 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
293 select CPU_CACHE_VIVT
295 select CPU_TLB_V4WBI if MMU
297 # XScale Core Version 3
300 depends on ARCH_IXP23XX
304 select CPU_CACHE_VIVT
306 select CPU_TLB_V4WBI if MMU
311 bool "Support ARM V6 processor"
312 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
316 select CPU_CACHE_VIPT
318 select CPU_COPY_V6 if MMU
319 select CPU_TLB_V6 if MMU
323 bool "Support ARM V6K processor extensions" if !SMP
327 Say Y here if your ARMv6 processor supports the 'K' extension.
328 This enables the kernel to use some instructions not present
329 on previous processors, and as such a kernel build with this
330 enabled will not boot on processors with do not support these
333 # Figure out what processor architecture version we should be using.
334 # This defines the compiler instruction set which depends on the machine type.
337 select TLS_REG_EMUL if SMP || !MMU
338 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
342 select TLS_REG_EMUL if SMP || !MMU
343 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
347 select TLS_REG_EMUL if SMP || !MMU
348 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
352 select TLS_REG_EMUL if SMP || !MMU
353 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
371 config CPU_ABRT_EV5TJ
384 config CPU_CACHE_V4WT
387 config CPU_CACHE_V4WB
393 config CPU_CACHE_VIVT
396 config CPU_CACHE_VIPT
400 # The copy-page model
413 # This selects the TLB model
417 ARM Architecture Version 3 TLB.
422 ARM Architecture Version 4 TLB with writethrough cache.
427 ARM Architecture Version 4 TLB with writeback cache.
432 ARM Architecture Version 4 TLB with writeback cache and invalidate
433 instruction cache entry.
443 Processor has the CP15 register.
449 Processor has the CP15 register, which has MMU related registers.
455 Processor has the CP15 register, which has MPU related registers.
458 # CPU supports 36-bit I/O
463 comment "Processor Features"
466 bool "Support Thumb user binaries"
467 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
470 Say Y if you want to include kernel support for running user space
473 The Thumb instruction set is a compressed form of the standard ARM
474 instruction set resulting in smaller binaries at the expense of
475 slightly less efficient code.
477 If you don't know what this all is, saying Y is a safe choice.
479 config CPU_BIG_ENDIAN
480 bool "Build big-endian kernel"
481 depends on ARCH_SUPPORTS_BIG_ENDIAN
483 Say Y if you plan on running a kernel in big-endian mode.
484 Note that your board must be properly built and your board
485 port must properly enable any big-endian related features
486 of your chipset/board/processor.
488 config CPU_ICACHE_DISABLE
489 bool "Disable I-Cache (I-bit)"
490 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
492 Say Y here to disable the processor instruction cache. Unless
493 you have a reason not to or are unsure, say N.
495 config CPU_DCACHE_DISABLE
496 bool "Disable D-Cache (C-bit)"
499 Say Y here to disable the processor data cache. Unless
500 you have a reason not to or are unsure, say N.
502 config CPU_DCACHE_WRITETHROUGH
503 bool "Force write through D-cache"
504 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
505 default y if CPU_ARM925T
507 Say Y here to use the data cache in writethrough mode. Unless you
508 specifically require this or are unsure, say N.
510 config CPU_CACHE_ROUND_ROBIN
511 bool "Round robin I and D cache replacement algorithm"
512 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
514 Say Y here to use the predictable round-robin cache replacement
515 policy. Unless you specifically require this or are unsure, say N.
517 config CPU_BPREDICT_DISABLE
518 bool "Disable branch prediction"
519 depends on CPU_ARM1020 || CPU_V6
521 Say Y here to disable branch prediction. If unsure, say N.
526 An SMP system using a pre-ARMv6 processor (there are apparently
527 a few prototypes like that in existence) and therefore access to
528 that required register must be emulated.
532 depends on !TLS_REG_EMUL
533 default y if SMP || CPU_32v7
535 This selects support for the CP15 thread register.
536 It is defined to be available on some ARMv6 processors (including
537 all SMP capable ARMv6's) or later processors. User space may
538 assume directly accessing that register and always obtain the
539 expected value only on ARMv7 and above.
541 config NEEDS_SYSCALL_FOR_CMPXCHG
544 SMP on a pre-ARMv6 processor? Well OK then.
545 Forget about fast user space cmpxchg support.
546 It is just not possible.