2 * linux/arch/arm/mach-sa1100/cpu-sa1110.c
4 * Copyright (C) 2001 Russell King
6 * $Id: cpu-sa1110.c,v 1.9 2002/07/06 16:53:18 rmk Exp $
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Note: there are two erratas that apply to the SA1110 here:
13 * 7 - SDRAM auto-power-up failure (rev A0)
14 * 13 - Corruption of internal register reads/writes following
15 * SDRAM reads (rev A0, B0, B1)
17 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
19 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
21 #include <linux/moduleparam.h>
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/sched.h>
25 #include <linux/cpufreq.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
29 #include <asm/hardware.h>
30 #include <asm/mach-types.h>
32 #include <asm/system.h>
38 static struct cpufreq_driver sa1110_driver;
42 u_char rows; /* bits */
43 u_char cas_latency; /* cycles */
44 u_char tck; /* clock cycle time (ns) */
45 u_char trcd; /* activate to r/w (ns) */
46 u_char trp; /* precharge to activate (ns) */
47 u_char twr; /* write recovery time (ns) */
48 u_short refresh; /* refresh time for array (us) */
57 static struct sdram_params sdram_tbl[] __initdata = {
58 { /* Toshiba TC59SM716 CL2 */
59 .name = "TC59SM716-CL2",
67 }, { /* Toshiba TC59SM716 CL3 */
68 .name = "TC59SM716-CL3",
76 }, { /* Samsung K4S641632D TC75 */
85 }, { /* Samsung KM416S4030CT */
86 .name = "KM416S4030CT",
89 .trcd = 24, /* 3 CLKs */
90 .trp = 24, /* 3 CLKs */
91 .twr = 16, /* Trdl: 2 CLKs */
94 }, { /* Winbond W982516AH75L CL3 */
95 .name = "W982516AH75L",
106 static struct sdram_params sdram_params;
109 * Given a period in ns and frequency in khz, calculate the number of
110 * cycles of frequency in period. Note that we round up to the next
111 * cycle, even if we are only slightly over.
113 static inline u_int ns_to_cycles(u_int ns, u_int khz)
115 return (ns * khz + 999999) / 1000000;
119 * Create the MDCAS register bit pattern.
121 static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
126 shift = delayed + 1 + rcd;
128 mdcas[0] = (1 << rcd) - 1;
129 mdcas[0] |= 0x55555555 << shift;
130 mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
134 sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
135 struct sdram_params *sdram)
137 u_int mem_khz, sd_khz, trp, twr;
139 mem_khz = cpu_khz / 2;
143 * If SDCLK would invalidate the SDRAM timings,
144 * run SDCLK at half speed.
146 * CPU steppings prior to B2 must either run the memory at
147 * half speed or use delayed read latching (errata 13).
149 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
150 (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
153 sd->mdcnfg = MDCNFG & 0x007f007f;
155 twr = ns_to_cycles(sdram->twr, mem_khz);
157 /* trp should always be >1 */
158 trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
162 sd->mdcnfg |= trp << 8;
163 sd->mdcnfg |= trp << 24;
164 sd->mdcnfg |= sdram->cas_latency << 12;
165 sd->mdcnfg |= sdram->cas_latency << 28;
166 sd->mdcnfg |= twr << 14;
167 sd->mdcnfg |= twr << 30;
169 sd->mdrefr = MDREFR & 0xffbffff0;
172 if (sd_khz != mem_khz)
173 sd->mdrefr |= MDREFR_K1DB2;
175 /* initial number of '1's in MDCAS + 1 */
176 set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
179 printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
180 sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
185 * Set the SDRAM refresh rate.
187 static inline void sdram_set_refresh(u_int dri)
189 MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
194 * Update the refresh period. We do this such that we always refresh
195 * the SDRAMs within their permissible period. The refresh period is
196 * always a multiple of the memory clock (fixed at cpu_clock / 2).
198 * FIXME: we don't currently take account of burst accesses here,
199 * but neither do Intels DM nor Angel.
202 sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
204 u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
205 u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
209 printk("new dri value = %d\n", dri);
212 sdram_set_refresh(dri);
216 * Ok, set the CPU frequency.
218 static int sa1110_target(struct cpufreq_policy *policy,
219 unsigned int target_freq,
220 unsigned int relation)
222 struct sdram_params *sdram = &sdram_params;
223 struct cpufreq_freqs freqs;
224 struct sdram_info sd;
226 unsigned int ppcr, unused;
229 case CPUFREQ_RELATION_L:
230 ppcr = sa11x0_freq_to_ppcr(target_freq);
231 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
234 case CPUFREQ_RELATION_H:
235 ppcr = sa11x0_freq_to_ppcr(target_freq);
236 if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
237 (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
244 freqs.old = sa11x0_getspeed(0);
245 freqs.new = sa11x0_ppcr_to_freq(ppcr);
248 sdram_calculate_timing(&sd, freqs.new, sdram);
252 * These values are wrong according to the SA1110 documentation
253 * and errata, but they seem to work. Need to get a storage
254 * scope on to the SDRAM signals to work out why.
256 if (policy->max < 147500) {
257 sd.mdrefr |= MDREFR_K1DB2;
258 sd.mdcas[0] = 0xaaaaaa7f;
260 sd.mdrefr &= ~MDREFR_K1DB2;
261 sd.mdcas[0] = 0xaaaaaa9f;
263 sd.mdcas[1] = 0xaaaaaaaa;
264 sd.mdcas[2] = 0xaaaaaaaa;
267 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
270 * The clock could be going away for some time. Set the SDRAMs
271 * to refresh rapidly (every 64 memory clock cycles). To get
272 * through the whole array, we need to wait 262144 mclk cycles.
273 * We wait 20ms to be safe.
275 sdram_set_refresh(2);
276 if (!irqs_disabled()) {
283 * Reprogram the DRAM timings with interrupts disabled, and
284 * ensure that we are doing this within a complete cache line.
285 * This means that we won't access SDRAM for the duration of
288 local_irq_save(flags);
289 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
291 __asm__ __volatile__(" \n\
294 1: str %3, [%1, #0] @ MDCNFG \n\
295 str %4, [%1, #28] @ MDREFR \n\
296 str %5, [%1, #4] @ MDCAS0 \n\
297 str %6, [%1, #8] @ MDCAS1 \n\
298 str %7, [%1, #12] @ MDCAS2 \n\
299 str %8, [%2, #0] @ PPCR \n\
306 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
307 "r" (sd.mdrefr), "r" (sd.mdcas[0]),
308 "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
309 local_irq_restore(flags);
312 * Now, return the SDRAM refresh back to normal.
314 sdram_update_refresh(freqs.new, sdram);
316 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
321 static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
323 if (policy->cpu != 0)
325 policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
326 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
327 policy->cpuinfo.min_freq = 59000;
328 policy->cpuinfo.max_freq = 287000;
329 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
333 static struct cpufreq_driver sa1110_driver = {
334 .flags = CPUFREQ_STICKY,
335 .verify = sa11x0_verify_speed,
336 .target = sa1110_target,
337 .get = sa11x0_getspeed,
338 .init = sa1110_cpu_init,
342 static struct sdram_params *sa1110_find_sdram(const char *name)
344 struct sdram_params *sdram;
346 for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
347 if (strcmp(name, sdram->name) == 0)
353 static char sdram_name[16];
355 static int __init sa1110_clk_init(void)
357 struct sdram_params *sdram;
358 const char *name = sdram_name;
361 if (machine_is_assabet())
362 name = "TC59SM716-CL3";
364 if (machine_is_pt_system3())
367 if (machine_is_h3100())
368 name = "KM416S4030CT";
371 sdram = sa1110_find_sdram(name);
373 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
374 " twr: %d refresh: %d cas_latency: %d\n",
375 sdram->tck, sdram->trcd, sdram->trp,
376 sdram->twr, sdram->refresh, sdram->cas_latency);
378 memcpy(&sdram_params, sdram, sizeof(sdram_params));
380 return cpufreq_register_driver(&sa1110_driver);
386 module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
387 arch_initcall(sa1110_clk_init);