err.no Git - linux-2.6/blob - arch/arm/mach-s3c2412/mach-jive.c

   1 /* linux/arch/arm/mach-s3c2410/mach-jive.c
   2  *
   3  * Copyright 2007 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://armlinux.simtec.co.uk/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/platform_device.h>
  22
  23 #include <linux/spi/spi.h>
  24
  25 #include <linux/mtd/mtd.h>
  26 #include <linux/mtd/partitions.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/mach/irq.h>
  31
  32 #include <asm/plat-s3c/regs-serial.h>
  33 #include <asm/plat-s3c/nand.h>
  34
  35 #include <asm/arch/regs-power.h>
  36 #include <asm/arch/regs-gpio.h>
  37 #include <asm/arch/regs-mem.h>
  38 #include <asm/arch/regs-lcd.h>
  39 #include <asm/arch/spi-gpio.h>
  40 #include <asm/arch/fb.h>
  41
  42 #include <asm/mach-types.h>
  43
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/partitions.h>
  48
  49 #include <asm/plat-s3c24xx/clock.h>
  50 #include <asm/plat-s3c24xx/devs.h>
  51 #include <asm/plat-s3c24xx/cpu.h>
  52 #include <asm/plat-s3c24xx/pm.h>
  53 #include <asm/plat-s3c24xx/udc.h>
  54
  55 static struct map_desc jive_iodesc[] __initdata = {
  56 };
  57
  58 #define UCON S3C2410_UCON_DEFAULT
  59 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
  60 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  61
  62 static struct s3c2410_uartcfg jive_uartcfgs[] = {
  63         [0] = {
  64                 .hwport      = 0,
  65                 .flags       = 0,
  66                 .ucon        = UCON,
  67                 .ulcon       = ULCON,
  68                 .ufcon       = UFCON,
  69         },
  70         [1] = {
  71                 .hwport      = 1,
  72                 .flags       = 0,
  73                 .ucon        = UCON,
  74                 .ulcon       = ULCON,
  75                 .ufcon       = UFCON,
  76         },
  77         [2] = {
  78                 .hwport      = 2,
  79                 .flags       = 0,
  80                 .ucon        = UCON,
  81                 .ulcon       = ULCON,
  82                 .ufcon       = UFCON,
  83         }
  84 };
  85
  86 /* Jive flash assignment
  87  *
  88  * 0x00000000-0x00028000 : uboot
  89  * 0x00028000-0x0002c000 : uboot env
  90  * 0x0002c000-0x00030000 : spare
  91  * 0x00030000-0x00200000 : zimage A
  92  * 0x00200000-0x01600000 : cramfs A
  93  * 0x01600000-0x017d0000 : zimage B
  94  * 0x017d0000-0x02bd0000 : cramfs B
  95  * 0x02bd0000-0x03fd0000 : yaffs
  96  */
  97 static struct mtd_partition jive_imageA_nand_part[] = {
  98
  99 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 100         /* Don't allow access to the bootloader from linux */
 101         {
 102                 .name           = "uboot",
 103                 .offset         = 0,
 104                 .size           = (160 * SZ_1K),
 105                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 106         },
 107
 108         /* spare */
 109         {
 110                 .name           = "spare",
 111                 .offset         = (176 * SZ_1K),
 112                 .size           = (16 * SZ_1K),
 113         },
 114 #endif
 115
 116         /* booted images */
 117         {
 118                 .name           = "kernel (ro)",
 119                 .offset         = (192 * SZ_1K),
 120                 .size           = (SZ_2M) - (192 * SZ_1K),
 121                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 122         }, {
 123                 .name           = "root (ro)",
 124                 .offset         = (SZ_2M),
 125                 .size           = (20 * SZ_1M),
 126                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 127         },
 128
 129         /* yaffs */
 130         {
 131                 .name           = "yaffs",
 132                 .offset         = (44 * SZ_1M),
 133                 .size           = (20 * SZ_1M),
 134         },
 135
 136         /* bootloader environment */
 137         {
 138                 .name           = "env",
 139                 .offset         = (160 * SZ_1K),
 140                 .size           = (16 * SZ_1K),
 141         },
 142
 143         /* upgrade images */
 144         {
 145                 .name           = "zimage",
 146                 .offset         = (22 * SZ_1M),
 147                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 148         }, {
 149                 .name           = "cramfs",
 150                 .offset         = (24 * SZ_1M) - (192*SZ_1K),
 151                 .size           = (20 * SZ_1M),
 152         },
 153 };
 154
 155 static struct mtd_partition jive_imageB_nand_part[] = {
 156
 157 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 158         /* Don't allow access to the bootloader from linux */
 159         {
 160                 .name           = "uboot",
 161                 .offset         = 0,
 162                 .size           = (160 * SZ_1K),
 163                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 164         },
 165
 166         /* spare */
 167         {
 168                 .name           = "spare",
 169                 .offset         = (176 * SZ_1K),
 170                 .size           = (16 * SZ_1K),
 171         },
 172 #endif
 173
 174         /* booted images */
 175         {
 176                 .name           = "kernel (ro)",
 177                 .offset         = (22 * SZ_1M),
 178                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 179                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 180         },
 181         {
 182                 .name           = "root (ro)",
 183                 .offset         = (24 * SZ_1M) - (192 * SZ_1K),
 184                 .size           = (20 * SZ_1M),
 185                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 186         },
 187
 188         /* yaffs */
 189         {
 190                 .name           = "yaffs",
 191                 .offset         = (44 * SZ_1M),
 192                 .size           = (20 * SZ_1M),
 193         },
 194
 195         /* bootloader environment */
 196         {
 197                 .name           = "env",
 198                 .offset         = (160 * SZ_1K),
 199                 .size           = (16 * SZ_1K),
 200         },
 201
 202         /* upgrade images */
 203         {
 204                 .name           = "zimage",
 205                 .offset         = (192 * SZ_1K),
 206                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
 207         }, {
 208                 .name           = "cramfs",
 209                 .offset         = (2 * SZ_1M),
 210                 .size           = (20 * SZ_1M),
 211         },
 212 };
 213
 214 static struct s3c2410_nand_set jive_nand_sets[] = {
 215         [0] = {
 216                 .name           = "flash",
 217                 .nr_chips       = 1,
 218                 .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
 219                 .partitions     = jive_imageA_nand_part,
 220         },
 221 };
 222
 223 static struct s3c2410_platform_nand jive_nand_info = {
 224         /* set taken from osiris nand timings, possibly still conservative */
 225         .tacls          = 30,
 226         .twrph0         = 55,
 227         .twrph1         = 40,
 228         .sets           = jive_nand_sets,
 229         .nr_sets        = ARRAY_SIZE(jive_nand_sets),
 230 };
 231
 232 static int __init jive_mtdset(char *options)
 233 {
 234         struct s3c2410_nand_set *nand = &jive_nand_sets[0];
 235         unsigned long set;
 236
 237         if (options == NULL || options[0] == '\0')
 238                 return 0;
 239
 240         if (strict_strtoul(options, 10, &set)) {
 241                 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
 242                 return 0;
 243         }
 244
 245         switch (set) {
 246         case 1:
 247                 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
 248                 nand->partitions = jive_imageB_nand_part;
 249         case 0:
 250                 /* this is already setup in the nand info */
 251                 break;
 252         default:
 253                 printk(KERN_ERR "Unknown mtd set %ld specified,"
 254                        "using default.", set);
 255         }
 256
 257         return 0;
 258 }
 259
 260 /* parse the mtdset= option given to the kernel command line */
 261 __setup("mtdset=", jive_mtdset);
 262
 263 /* LCD timing and setup */
 264
 265 #define LCD_XRES         (240)
 266 #define LCD_YRES         (320)
 267 #define LCD_LEFT_MARGIN  (12)
 268 #define LCD_RIGHT_MARGIN (12)
 269 #define LCD_LOWER_MARGIN (12)
 270 #define LCD_UPPER_MARGIN (12)
 271 #define LCD_VSYNC        (2)
 272 #define LCD_HSYNC        (2)
 273
 274 #define LCD_REFRESH      (60)
 275
 276 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
 277 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
 278
 279 struct s3c2410fb_display jive_vgg2432a4_display[] = {
 280         [0] = {
 281                 .width          = LCD_XRES,
 282                 .height         = LCD_YRES,
 283                 .xres           = LCD_XRES,
 284                 .yres           = LCD_YRES,
 285                 .left_margin    = LCD_LEFT_MARGIN,
 286                 .right_margin   = LCD_RIGHT_MARGIN,
 287                 .upper_margin   = LCD_UPPER_MARGIN,
 288                 .lower_margin   = LCD_LOWER_MARGIN,
 289                 .hsync_len      = LCD_HSYNC,
 290                 .vsync_len      = LCD_VSYNC,
 291
 292                 .pixclock       = (1000000000000LL /
 293                                    (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
 294
 295                 .bpp            = 16,
 296                 .type           = (S3C2410_LCDCON1_TFT16BPP |
 297                                    S3C2410_LCDCON1_TFT),
 298
 299                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
 300                                    S3C2410_LCDCON5_INVVLINE |
 301                                    S3C2410_LCDCON5_INVVFRAME |
 302                                    S3C2410_LCDCON5_INVVDEN |
 303                                    S3C2410_LCDCON5_PWREN),
 304         },
 305 };
 306
 307 /* todo - put into gpio header */
 308
 309 #define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
 310 #define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
 311
 312 struct s3c2410fb_mach_info jive_lcd_config = {
 313         .displays        = jive_vgg2432a4_display,
 314         .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
 315         .default_display = 0,
 316
 317         /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
 318          * and disable the pull down resistors on pins we are using for LCD
 319          * data. */
 320
 321         .gpcup          = (0xf << 1) | (0x3f << 10),
 322
 323         .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
 324                            S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
 325                            S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
 326                            S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
 327                            S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
 328
 329         .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
 330                            S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
 331                            S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
 332                            S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
 333                            S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
 334
 335         .gpdup          = (0x3f << 2) | (0x3f << 10),
 336
 337         .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
 338                            S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
 339                            S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
 340                            S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
 341                            S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
 342                            S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
 343
 344         .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
 345                            S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
 346                            S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
 347                            S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
 348                            S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
 349                            S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
 350 };
 351
 352 /* LCD SPI support */
 353
 354 static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 355 {
 356         s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
 357 }
 358
 359 static struct s3c2410_spigpio_info jive_lcd_spi = {
 360         .bus_num        = 1,
 361         .pin_clk        = S3C2410_GPG8,
 362         .pin_mosi       = S3C2410_GPB8,
 363         .chip_select    = jive_lcd_spi_chipselect,
 364 };
 365
 366 static struct platform_device jive_device_lcdspi = {
 367         .name           = "s3c24xx-spi-gpio",
 368         .id             = 1,
 369         .num_resources  = 0,
 370         .dev.platform_data = &jive_lcd_spi,
 371 };
 372
 373 /* JIVE SPI devices. */
 374
 375
 376 static struct spi_board_info __initdata jive_spi_devs[] = {
 377         [0] = {
 378                 .modalias       = "VGG2432A4",
 379                 .bus_num        = 1,
 380                 .chip_select    = 0,
 381                 .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
 382                 .max_speed_hz   = 100000,
 383         },
 384 };
 385
 386
 387 static struct platform_device *jive_devices[] __initdata = {
 388         &s3c_device_usb,
 389         &s3c_device_rtc,
 390         &s3c_device_wdt,
 391         &s3c_device_i2c,
 392         &s3c_device_lcd,
 393         &jive_device_lcdspi,
 394         &s3c_device_nand,
 395         &s3c_device_usbgadget,
 396 };
 397
 398 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
 399         .vbus_pin       = S3C2410_GPG1,         /* detect is on GPG1 */
 400 };
 401
 402 /* Jive power management device */
 403
 404 #ifdef CONFIG_PM
 405 static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
 406 {
 407         /* Write the magic value u-boot uses to check for resume into
 408          * the INFORM0 register, and ensure INFORM1 is set to the
 409          * correct address to resume from. */
 410
 411         __raw_writel(0x2BED, S3C2412_INFORM0);
 412         __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
 413
 414         return 0;
 415 }
 416
 417 static int jive_pm_resume(struct sys_device *sd)
 418 {
 419         __raw_writel(0x0, S3C2412_INFORM0);
 420         return 0;
 421 }
 422
 423 #else
 424 #define jive_pm_suspend NULL
 425 #define jive_pm_resume NULL
 426 #endif
 427
 428 static struct sysdev_class jive_pm_sysclass = {
 429         .name           = "jive-pm",
 430         .suspend        = jive_pm_suspend,
 431         .resume         = jive_pm_resume,
 432 };
 433
 434 static struct sys_device jive_pm_sysdev = {
 435         .cls            = &jive_pm_sysclass,
 436 };
 437
 438 static void __init jive_map_io(void)
 439 {
 440         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
 441         s3c24xx_init_clocks(12000000);
 442         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
 443 }
 444
 445 static void __init jive_machine_init(void)
 446 {
 447         /* register system devices for managing low level suspend */
 448
 449         sysdev_class_register(&jive_pm_sysclass);
 450         sysdev_register(&jive_pm_sysdev);
 451
 452         /* write our sleep configurations for the IO. Pull down all unused
 453          * IO, ensure that we have turned off all peripherals we do not
 454          * need, and configure the ones we do need. */
 455
 456         /* Port B sleep */
 457
 458         __raw_writel(S3C2412_SLPCON_IN(0)   |
 459                      S3C2412_SLPCON_PULL(1) |
 460                      S3C2412_SLPCON_HIGH(2) |
 461                      S3C2412_SLPCON_PULL(3) |
 462                      S3C2412_SLPCON_PULL(4) |
 463                      S3C2412_SLPCON_PULL(5) |
 464                      S3C2412_SLPCON_PULL(6) |
 465                      S3C2412_SLPCON_HIGH(7) |
 466                      S3C2412_SLPCON_PULL(8) |
 467                      S3C2412_SLPCON_PULL(9) |
 468                      S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
 469
 470         /* Port C sleep */
 471
 472         __raw_writel(S3C2412_SLPCON_PULL(0) |
 473                      S3C2412_SLPCON_PULL(1) |
 474                      S3C2412_SLPCON_PULL(2) |
 475                      S3C2412_SLPCON_PULL(3) |
 476                      S3C2412_SLPCON_PULL(4) |
 477                      S3C2412_SLPCON_PULL(5) |
 478                      S3C2412_SLPCON_LOW(6)  |
 479                      S3C2412_SLPCON_PULL(6) |
 480                      S3C2412_SLPCON_PULL(7) |
 481                      S3C2412_SLPCON_PULL(8) |
 482                      S3C2412_SLPCON_PULL(9) |
 483                      S3C2412_SLPCON_PULL(10) |
 484                      S3C2412_SLPCON_PULL(11) |
 485                      S3C2412_SLPCON_PULL(12) |
 486                      S3C2412_SLPCON_PULL(13) |
 487                      S3C2412_SLPCON_PULL(14) |
 488                      S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
 489
 490         /* Port D sleep */
 491
 492         __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
 493
 494         /* Port F sleep */
 495
 496         __raw_writel(S3C2412_SLPCON_LOW(0)  |
 497                      S3C2412_SLPCON_LOW(1)  |
 498                      S3C2412_SLPCON_LOW(2)  |
 499                      S3C2412_SLPCON_EINT(3) |
 500                      S3C2412_SLPCON_EINT(4) |
 501                      S3C2412_SLPCON_EINT(5) |
 502                      S3C2412_SLPCON_EINT(6) |
 503                      S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
 504
 505         /* Port G sleep */
 506
 507         __raw_writel(S3C2412_SLPCON_IN(0)    |
 508                      S3C2412_SLPCON_IN(1)    |
 509                      S3C2412_SLPCON_IN(2)    |
 510                      S3C2412_SLPCON_IN(3)    |
 511                      S3C2412_SLPCON_IN(4)    |
 512                      S3C2412_SLPCON_IN(5)    |
 513                      S3C2412_SLPCON_IN(6)    |
 514                      S3C2412_SLPCON_IN(7)    |
 515                      S3C2412_SLPCON_PULL(8)  |
 516                      S3C2412_SLPCON_PULL(9)  |
 517                      S3C2412_SLPCON_IN(10)   |
 518                      S3C2412_SLPCON_PULL(11) |
 519                      S3C2412_SLPCON_PULL(12) |
 520                      S3C2412_SLPCON_PULL(13) |
 521                      S3C2412_SLPCON_IN(14)   |
 522                      S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
 523
 524         /* Port H sleep */
 525
 526         __raw_writel(S3C2412_SLPCON_PULL(0) |
 527                      S3C2412_SLPCON_PULL(1) |
 528                      S3C2412_SLPCON_PULL(2) |
 529                      S3C2412_SLPCON_PULL(3) |
 530                      S3C2412_SLPCON_PULL(4) |
 531                      S3C2412_SLPCON_PULL(5) |
 532                      S3C2412_SLPCON_PULL(6) |
 533                      S3C2412_SLPCON_IN(7)   |
 534                      S3C2412_SLPCON_IN(8)   |
 535                      S3C2412_SLPCON_PULL(9) |
 536                      S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
 537
 538         /* initialise the power management now we've setup everything. */
 539
 540         s3c2410_pm_init();
 541
 542         s3c_device_nand.dev.platform_data = &jive_nand_info;
 543
 544         /* initialise the spi */
 545
 546         s3c2410_gpio_setpin(S3C2410_GPG13, 0);
 547         s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
 548
 549         s3c2410_gpio_setpin(S3C2410_GPB7, 1);
 550         s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
 551
 552         s3c2410_gpio_setpin(S3C2410_GPB6, 0);
 553         s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
 554
 555         s3c2410_gpio_setpin(S3C2410_GPG8, 1);
 556         s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
 557
 558         /* Turn off suspend on both USB ports, and switch the
 559          * selectable USB port to USB device mode. */
 560
 561         s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
 562                               S3C2410_MISCCR_USBSUSPND0 |
 563                               S3C2410_MISCCR_USBSUSPND1, 0x0);
 564
 565         s3c24xx_udc_set_platdata(&jive_udc_cfg);
 566         s3c24xx_fb_set_platdata(&jive_lcd_config);
 567
 568         spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
 569
 570         platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
 571 }
 572
 573 MACHINE_START(JIVE, "JIVE")
 574         /* Maintainer: Ben Dooks <ben@fluff.org> */
 575         .phys_io        = S3C2410_PA_UART,
 576         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 577         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 578
 579         .init_irq       = s3c24xx_init_irq,
 580         .map_io         = jive_map_io,
 581         .init_machine   = jive_machine_init,
 582         .timer          = &s3c24xx_timer,
 583 MACHINE_END