err.no Git - linux-2.6/blob - arch/arm/mach-s3c2410/s3c2412-clock.c

   1 /* linux/arch/arm/mach-s3c2410/s3c2412-clock.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2412,S3C2413 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/list.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/sysdev.h>
  30 #include <linux/clk.h>
  31 #include <linux/mutex.h>
  32 #include <linux/delay.h>
  33
  34 #include <asm/mach/map.h>
  35
  36 #include <asm/hardware.h>
  37 #include <asm/io.h>
  38
  39 #include <asm/arch/regs-serial.h>
  40 #include <asm/arch/regs-clock.h>
  41 #include <asm/arch/regs-gpio.h>
  42
  43 #include "s3c2412.h"
  44 #include "clock.h"
  45 #include "cpu.h"
  46
  47 /* We currently have to assume that the system is running
  48  * from the XTPll input, and that all ***REFCLKs are being
  49  * fed from it, as we cannot read the state of OM[4] from
  50  * software.
  51  *
  52  * It would be possible for each board initialisation to
  53  * set the correct muxing at initialisation
  54 */
  55
  56 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
  57 {
  58         unsigned int clocks = clk->ctrlbit;
  59         unsigned long clkcon;
  60
  61         clkcon = __raw_readl(S3C2410_CLKCON);
  62
  63         if (enable)
  64                 clkcon |= clocks;
  65         else
  66                 clkcon &= ~clocks;
  67
  68         __raw_writel(clkcon, S3C2410_CLKCON);
  69
  70         return 0;
  71 }
  72
  73 static int s3c2412_upll_enable(struct clk *clk, int enable)
  74 {
  75         unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
  76         unsigned long orig = upllcon;
  77
  78         if (!enable)
  79                 upllcon |= S3C2412_PLLCON_OFF;
  80         else
  81                 upllcon &= ~S3C2412_PLLCON_OFF;
  82
  83         __raw_writel(upllcon, S3C2410_UPLLCON);
  84
  85         /* allow ~150uS for the PLL to settle and lock */
  86
  87         if (enable && (orig & S3C2412_PLLCON_OFF))
  88                 udelay(150);
  89
  90         return 0;
  91 }
  92
  93 /* clock selections */
  94
  95 /* CPU EXTCLK input */
  96 static struct clk clk_ext = {
  97         .name           = "extclk",
  98         .id             = -1,
  99 };
 100
 101 static struct clk clk_erefclk = {
 102         .name           = "erefclk",
 103         .id             = -1,
 104 };
 105
 106 static struct clk clk_urefclk = {
 107         .name           = "urefclk",
 108         .id             = -1,
 109 };
 110
 111 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
 112 {
 113         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 114
 115         if (parent == &clk_urefclk)
 116                 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
 117         else if (parent == &clk_upll)
 118                 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
 119         else
 120                 return -EINVAL;
 121
 122         clk->parent = parent;
 123
 124         __raw_writel(clksrc, S3C2412_CLKSRC);
 125         return 0;
 126 }
 127
 128 static struct clk clk_usysclk = {
 129         .name           = "usysclk",
 130         .id             = -1,
 131         .parent         = &clk_xtal,
 132         .set_parent     = s3c2412_setparent_usysclk,
 133 };
 134
 135 static struct clk clk_mrefclk = {
 136         .name           = "mrefclk",
 137         .parent         = &clk_xtal,
 138         .id             = -1,
 139 };
 140
 141 static struct clk clk_mdivclk = {
 142         .name           = "mdivclk",
 143         .parent         = &clk_xtal,
 144         .id             = -1,
 145 };
 146
 147 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
 148 {
 149         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 150
 151         if (parent == &clk_usysclk)
 152                 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
 153         else if (parent == &clk_h)
 154                 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
 155         else
 156                 return -EINVAL;
 157
 158         clk->parent = parent;
 159
 160         __raw_writel(clksrc, S3C2412_CLKSRC);
 161         return 0;
 162 }
 163
 164 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
 165                                               unsigned long rate)
 166 {
 167         unsigned long parent_rate = clk_get_rate(clk->parent);
 168         int div;
 169
 170         if (rate > parent_rate)
 171                 return parent_rate;
 172
 173         div = parent_rate / rate;
 174         if (div > 2)
 175                 div = 2;
 176
 177         return parent_rate / div;
 178 }
 179
 180 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
 181 {
 182         unsigned long parent_rate = clk_get_rate(clk->parent);
 183         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 184
 185         return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
 186 }
 187
 188 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
 189 {
 190         unsigned long parent_rate = clk_get_rate(clk->parent);
 191         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 192
 193         rate = s3c2412_roundrate_usbsrc(clk, rate);
 194
 195         if ((parent_rate / rate) == 2)
 196                 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
 197         else
 198                 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
 199
 200         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 201         return 0;
 202 }
 203
 204 static struct clk clk_usbsrc = {
 205         .name           = "usbsrc",
 206         .id             = -1,
 207         .get_rate       = s3c2412_getrate_usbsrc,
 208         .set_rate       = s3c2412_setrate_usbsrc,
 209         .round_rate     = s3c2412_roundrate_usbsrc,
 210         .set_parent     = s3c2412_setparent_usbsrc,
 211 };
 212
 213 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
 214 {
 215         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 216
 217         if (parent == &clk_mdivclk)
 218                 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
 219         else if (parent == &clk_upll)
 220                 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
 221         else
 222                 return -EINVAL;
 223
 224         clk->parent = parent;
 225
 226         __raw_writel(clksrc, S3C2412_CLKSRC);
 227         return 0;
 228 }
 229
 230 static struct clk clk_msysclk = {
 231         .name           = "msysclk",
 232         .id             = -1,
 233         .set_parent     = s3c2412_setparent_msysclk,
 234 };
 235
 236 /* these next clocks have an divider immediately after them,
 237  * so we can register them with their divider and leave out the
 238  * intermediate clock stage
 239 */
 240 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
 241                                               unsigned long rate)
 242 {
 243         unsigned long parent_rate = clk_get_rate(clk->parent);
 244         int div;
 245
 246         if (rate > parent_rate)
 247                 return parent_rate;
 248
 249         /* note, we remove the +/- 1 calculations as they cancel out */
 250
 251         div = (rate / parent_rate);
 252
 253         if (div < 1)
 254                 div = 1;
 255         else if (div > 16)
 256                 div = 16;
 257
 258         return parent_rate / div;
 259 }
 260
 261 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
 262 {
 263         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 264
 265         if (parent == &clk_erefclk)
 266                 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
 267         else if (parent == &clk_mpll)
 268                 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
 269         else
 270                 return -EINVAL;
 271
 272         clk->parent = parent;
 273
 274         __raw_writel(clksrc, S3C2412_CLKSRC);
 275         return 0;
 276 }
 277
 278 static unsigned long s3c2412_getrate_uart(struct clk *clk)
 279 {
 280         unsigned long parent_rate = clk_get_rate(clk->parent);
 281         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 282
 283         div &= S3C2412_CLKDIVN_UARTDIV_MASK;
 284         div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
 285
 286         return parent_rate / (div + 1);
 287 }
 288
 289 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
 290 {
 291         unsigned long parent_rate = clk_get_rate(clk->parent);
 292         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 293
 294         rate = s3c2412_roundrate_clksrc(clk, rate);
 295
 296         clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
 297         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
 298
 299         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 300         return 0;
 301 }
 302
 303 static struct clk clk_uart = {
 304         .name           = "uartclk",
 305         .id             = -1,
 306         .get_rate       = s3c2412_getrate_uart,
 307         .set_rate       = s3c2412_setrate_uart,
 308         .set_parent     = s3c2412_setparent_uart,
 309         .round_rate     = s3c2412_roundrate_clksrc,
 310 };
 311
 312 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
 313 {
 314         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 315
 316         if (parent == &clk_erefclk)
 317                 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
 318         else if (parent == &clk_mpll)
 319                 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
 320         else
 321                 return -EINVAL;
 322
 323         clk->parent = parent;
 324
 325         __raw_writel(clksrc, S3C2412_CLKSRC);
 326         return 0;
 327 }
 328
 329 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
 330 {
 331         unsigned long parent_rate = clk_get_rate(clk->parent);
 332         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 333
 334         div &= S3C2412_CLKDIVN_I2SDIV_MASK;
 335         div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
 336
 337         return parent_rate / (div + 1);
 338 }
 339
 340 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
 341 {
 342         unsigned long parent_rate = clk_get_rate(clk->parent);
 343         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 344
 345         rate = s3c2412_roundrate_clksrc(clk, rate);
 346
 347         clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
 348         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
 349
 350         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 351         return 0;
 352 }
 353
 354 static struct clk clk_i2s = {
 355         .name           = "i2sclk",
 356         .id             = -1,
 357         .get_rate       = s3c2412_getrate_i2s,
 358         .set_rate       = s3c2412_setrate_i2s,
 359         .set_parent     = s3c2412_setparent_i2s,
 360         .round_rate     = s3c2412_roundrate_clksrc,
 361 };
 362
 363 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
 364 {
 365         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 366
 367         if (parent == &clk_usysclk)
 368                 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
 369         else if (parent == &clk_h)
 370                 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
 371         else
 372                 return -EINVAL;
 373
 374         clk->parent = parent;
 375
 376         __raw_writel(clksrc, S3C2412_CLKSRC);
 377         return 0;
 378 }
 379 static unsigned long s3c2412_getrate_cam(struct clk *clk)
 380 {
 381         unsigned long parent_rate = clk_get_rate(clk->parent);
 382         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 383
 384         div &= S3C2412_CLKDIVN_CAMDIV_MASK;
 385         div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
 386
 387         return parent_rate / (div + 1);
 388 }
 389
 390 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
 391 {
 392         unsigned long parent_rate = clk_get_rate(clk->parent);
 393         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 394
 395         rate = s3c2412_roundrate_clksrc(clk, rate);
 396
 397         clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
 398         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
 399
 400         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 401         return 0;
 402 }
 403
 404 static struct clk clk_cam = {
 405         .name           = "camif-upll", /* same as 2440 name */
 406         .id             = -1,
 407         .get_rate       = s3c2412_getrate_cam,
 408         .set_rate       = s3c2412_setrate_cam,
 409         .set_parent     = s3c2412_setparent_cam,
 410         .round_rate     = s3c2412_roundrate_clksrc,
 411 };
 412
 413 /* standard clock definitions */
 414
 415 static struct clk init_clocks_disable[] = {
 416         {
 417                 .name           = "nand",
 418                 .id             = -1,
 419                 .parent         = &clk_h,
 420                 .enable         = s3c2412_clkcon_enable,
 421                 .ctrlbit        = S3C2412_CLKCON_NAND,
 422         }, {
 423                 .name           = "sdi",
 424                 .id             = -1,
 425                 .parent         = &clk_p,
 426                 .enable         = s3c2412_clkcon_enable,
 427                 .ctrlbit        = S3C2412_CLKCON_SDI,
 428         }, {
 429                 .name           = "adc",
 430                 .id             = -1,
 431                 .parent         = &clk_p,
 432                 .enable         = s3c2412_clkcon_enable,
 433                 .ctrlbit        = S3C2412_CLKCON_ADC,
 434         }, {
 435                 .name           = "i2c",
 436                 .id             = -1,
 437                 .parent         = &clk_p,
 438                 .enable         = s3c2412_clkcon_enable,
 439                 .ctrlbit        = S3C2412_CLKCON_IIC,
 440         }, {
 441                 .name           = "iis",
 442                 .id             = -1,
 443                 .parent         = &clk_p,
 444                 .enable         = s3c2412_clkcon_enable,
 445                 .ctrlbit        = S3C2412_CLKCON_IIS,
 446         }, {
 447                 .name           = "spi",
 448                 .id             = -1,
 449                 .parent         = &clk_p,
 450                 .enable         = s3c2412_clkcon_enable,
 451                 .ctrlbit        = S3C2412_CLKCON_SPI,
 452         }
 453 };
 454
 455 static struct clk init_clocks[] = {
 456         {
 457                 .name           = "dma",
 458                 .id             = 0,
 459                 .parent         = &clk_h,
 460                 .enable         = s3c2412_clkcon_enable,
 461                 .ctrlbit        = S3C2412_CLKCON_DMA0,
 462         }, {
 463                 .name           = "dma",
 464                 .id             = 1,
 465                 .parent         = &clk_h,
 466                 .enable         = s3c2412_clkcon_enable,
 467                 .ctrlbit        = S3C2412_CLKCON_DMA1,
 468         }, {
 469                 .name           = "dma",
 470                 .id             = 2,
 471                 .parent         = &clk_h,
 472                 .enable         = s3c2412_clkcon_enable,
 473                 .ctrlbit        = S3C2412_CLKCON_DMA2,
 474         }, {
 475                 .name           = "dma",
 476                 .id             = 3,
 477                 .parent         = &clk_h,
 478                 .enable         = s3c2412_clkcon_enable,
 479                 .ctrlbit        = S3C2412_CLKCON_DMA3,
 480         }, {
 481                 .name           = "lcd",
 482                 .id             = -1,
 483                 .parent         = &clk_h,
 484                 .enable         = s3c2412_clkcon_enable,
 485                 .ctrlbit        = S3C2412_CLKCON_LCDC,
 486         }, {
 487                 .name           = "gpio",
 488                 .id             = -1,
 489                 .parent         = &clk_p,
 490                 .enable         = s3c2412_clkcon_enable,
 491                 .ctrlbit        = S3C2412_CLKCON_GPIO,
 492         }, {
 493                 .name           = "usb-host",
 494                 .id             = -1,
 495                 .parent         = &clk_h,
 496                 .enable         = s3c2412_clkcon_enable,
 497                 .ctrlbit        = S3C2412_CLKCON_USBH,
 498         }, {
 499                 .name           = "usb-device",
 500                 .id             = -1,
 501                 .parent         = &clk_h,
 502                 .enable         = s3c2412_clkcon_enable,
 503                 .ctrlbit        = S3C2412_CLKCON_USBD,
 504         }, {
 505                 .name           = "timers",
 506                 .id             = -1,
 507                 .parent         = &clk_p,
 508                 .enable         = s3c2412_clkcon_enable,
 509                 .ctrlbit        = S3C2412_CLKCON_PWMT,
 510         }, {
 511                 .name           = "uart",
 512                 .id             = 0,
 513                 .parent         = &clk_p,
 514                 .enable         = s3c2412_clkcon_enable,
 515                 .ctrlbit        = S3C2412_CLKCON_UART0,
 516         }, {
 517                 .name           = "uart",
 518                 .id             = 1,
 519                 .parent         = &clk_p,
 520                 .enable         = s3c2412_clkcon_enable,
 521                 .ctrlbit        = S3C2412_CLKCON_UART1,
 522         }, {
 523                 .name           = "uart",
 524                 .id             = 2,
 525                 .parent         = &clk_p,
 526                 .enable         = s3c2412_clkcon_enable,
 527                 .ctrlbit        = S3C2412_CLKCON_UART2,
 528         }, {
 529                 .name           = "rtc",
 530                 .id             = -1,
 531                 .parent         = &clk_p,
 532                 .enable         = s3c2412_clkcon_enable,
 533                 .ctrlbit        = S3C2412_CLKCON_RTC,
 534         }, {
 535                 .name           = "watchdog",
 536                 .id             = -1,
 537                 .parent         = &clk_p,
 538                 .ctrlbit        = 0,
 539         }, {
 540                 .name           = "usb-bus-gadget",
 541                 .id             = -1,
 542                 .parent         = &clk_usb_bus,
 543                 .enable         = s3c2412_clkcon_enable,
 544                 .ctrlbit        = S3C2412_CLKCON_USB_DEV48,
 545         }, {
 546                 .name           = "usb-bus-host",
 547                 .id             = -1,
 548                 .parent         = &clk_usb_bus,
 549                 .enable         = s3c2412_clkcon_enable,
 550                 .ctrlbit        = S3C2412_CLKCON_USB_HOST48,
 551         }
 552 };
 553
 554 /* clocks to add where we need to check their parentage */
 555
 556 struct clk_init {
 557         struct clk      *clk;
 558         unsigned int     bit;
 559         struct clk      *src_0;
 560         struct clk      *src_1;
 561 };
 562
 563 static struct clk_init clks_src[] __initdata = {
 564         {
 565                 .clk    = &clk_usysclk,
 566                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
 567                 .src_0  = &clk_urefclk,
 568                 .src_1  = &clk_upll,
 569         }, {
 570                 .clk    = &clk_i2s,
 571                 .bit    = S3C2412_CLKSRC_I2SCLK_MPLL,
 572                 .src_0  = &clk_erefclk,
 573                 .src_1  = &clk_mpll,
 574         }, {
 575                 .clk    = &clk_cam,
 576                 .bit    = S3C2412_CLKSRC_CAMCLK_HCLK,
 577                 .src_0  = &clk_usysclk,
 578                 .src_1  = &clk_h,
 579         }, {
 580                 .clk    = &clk_msysclk,
 581                 .bit    = S3C2412_CLKSRC_MSYSCLK_MPLL,
 582                 .src_0  = &clk_mdivclk,
 583                 .src_1  = &clk_mpll,
 584         }, {
 585                 .clk    = &clk_uart,
 586                 .bit    = S3C2412_CLKSRC_UARTCLK_MPLL,
 587                 .src_0  = &clk_erefclk,
 588                 .src_1  = &clk_mpll,
 589         }, {
 590                 .clk    = &clk_usbsrc,
 591                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
 592                 .src_0  = &clk_usysclk,
 593                 .src_1  = &clk_h,
 594         },
 595 };
 596
 597 /* s3c2412_clk_initparents
 598  *
 599  * Initialise the parents for the clocks that we get at start-time
 600 */
 601
 602 static void __init s3c2412_clk_initparents(void)
 603 {
 604         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 605         struct clk_init *cip = clks_src;
 606         struct clk *src;
 607         int ptr;
 608         int ret;
 609
 610         for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
 611                 ret = s3c24xx_register_clock(cip->clk);
 612                 if (ret < 0) {
 613                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 614                                cip->clk->name, ret);
 615                 }
 616
 617                 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
 618
 619                 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
 620                 clk_set_parent(cip->clk, src);
 621         }
 622 }
 623
 624 /* clocks to add straight away */
 625
 626 static struct clk *clks[] __initdata = {
 627         &clk_ext,
 628         &clk_usb_bus,
 629         &clk_erefclk,
 630         &clk_urefclk,
 631         &clk_mrefclk,
 632 };
 633
 634 int __init s3c2412_baseclk_add(void)
 635 {
 636         unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
 637         struct clk *clkp;
 638         int ret;
 639         int ptr;
 640
 641         clk_upll.enable = s3c2412_upll_enable;
 642         clk_usb_bus.parent = &clk_usbsrc;
 643         clk_usb_bus.rate = 0x0;
 644
 645         s3c2412_clk_initparents();
 646
 647         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
 648                 clkp = clks[ptr];
 649
 650                 ret = s3c24xx_register_clock(clkp);
 651                 if (ret < 0) {
 652                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 653                                clkp->name, ret);
 654                 }
 655         }
 656
 657         /* ensure usb bus clock is within correct rate of 48MHz */
 658
 659         if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
 660                 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
 661
 662                 /* for the moment, let's use the UPLL, and see if we can
 663                  * get 48MHz */
 664
 665                 clk_set_parent(&clk_usysclk, &clk_upll);
 666                 clk_set_parent(&clk_usbsrc, &clk_usysclk);
 667                 clk_set_rate(&clk_usbsrc, 48*1000*1000);
 668         }
 669
 670         printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
 671                (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
 672                print_mhz(clk_get_rate(&clk_upll)),
 673                print_mhz(clk_get_rate(&clk_usb_bus)));
 674
 675         /* register clocks from clock array */
 676
 677         clkp = init_clocks;
 678         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
 679                 /* ensure that we note the clock state */
 680
 681                 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
 682
 683                 ret = s3c24xx_register_clock(clkp);
 684                 if (ret < 0) {
 685                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 686                                clkp->name, ret);
 687                 }
 688         }
 689
 690         /* We must be careful disabling the clocks we are not intending to
 691          * be using at boot time, as subsytems such as the LCD which do
 692          * their own DMA requests to the bus can cause the system to lockup
 693          * if they where in the middle of requesting bus access.
 694          *
 695          * Disabling the LCD clock if the LCD is active is very dangerous,
 696          * and therefore the bootloader should be careful to not enable
 697          * the LCD clock if it is not needed.
 698         */
 699
 700         /* install (and disable) the clocks we do not need immediately */
 701
 702         clkp = init_clocks_disable;
 703         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 704
 705                 ret = s3c24xx_register_clock(clkp);
 706                 if (ret < 0) {
 707                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 708                                clkp->name, ret);
 709                 }
 710
 711                 s3c2412_clkcon_enable(clkp, 0);
 712         }
 713
 714         return 0;
 715 }