1 /* linux/arch/arm/mach-s3c2410/pm.c
3 * Copyright (c) 2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Power Manager (Suspend-To-RAM) support
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Parts based on arch/arm/mach-pxa/pm.c
26 * Thanks to Dimitry Andric for debugging
29 #include <linux/init.h>
30 #include <linux/suspend.h>
31 #include <linux/errno.h>
32 #include <linux/time.h>
33 #include <linux/interrupt.h>
34 #include <linux/crc32.h>
35 #include <linux/ioport.h>
36 #include <linux/delay.h>
38 #include <asm/hardware.h>
41 #include <asm/arch/regs-serial.h>
42 #include <asm/arch/regs-clock.h>
43 #include <asm/arch/regs-gpio.h>
44 #include <asm/arch/regs-mem.h>
45 #include <asm/arch/regs-irq.h>
47 #include <asm/mach/time.h>
51 /* for external use */
53 unsigned long s3c_pm_flags;
55 /* cache functions from arch/arm/mm/proc-arm920.S */
57 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
58 extern void arm920_flush_kern_cache_all(void);
60 static void arm920_flush_kern_cache_all(void) { }
63 #define PFX "s3c24xx-pm: "
65 static struct sleep_save core_save[] = {
66 SAVE_ITEM(S3C2410_LOCKTIME),
67 SAVE_ITEM(S3C2410_CLKCON),
69 /* we restore the timings here, with the proviso that the board
70 * brings the system up in an slower, or equal frequency setting
71 * to the original system.
73 * if we cannot guarantee this, then things are going to go very
74 * wrong here, as we modify the refresh and both pll settings.
77 SAVE_ITEM(S3C2410_BWSCON),
78 SAVE_ITEM(S3C2410_BANKCON0),
79 SAVE_ITEM(S3C2410_BANKCON1),
80 SAVE_ITEM(S3C2410_BANKCON2),
81 SAVE_ITEM(S3C2410_BANKCON3),
82 SAVE_ITEM(S3C2410_BANKCON4),
83 SAVE_ITEM(S3C2410_BANKCON5),
85 SAVE_ITEM(S3C2410_CLKDIVN),
86 SAVE_ITEM(S3C2410_MPLLCON),
87 SAVE_ITEM(S3C2410_UPLLCON),
88 SAVE_ITEM(S3C2410_CLKSLOW),
89 SAVE_ITEM(S3C2410_REFRESH),
92 static struct sleep_save gpio_save[] = {
93 SAVE_ITEM(S3C2410_GPACON),
94 SAVE_ITEM(S3C2410_GPADAT),
96 SAVE_ITEM(S3C2410_GPBCON),
97 SAVE_ITEM(S3C2410_GPBDAT),
98 SAVE_ITEM(S3C2410_GPBUP),
100 SAVE_ITEM(S3C2410_GPCCON),
101 SAVE_ITEM(S3C2410_GPCDAT),
102 SAVE_ITEM(S3C2410_GPCUP),
104 SAVE_ITEM(S3C2410_GPDCON),
105 SAVE_ITEM(S3C2410_GPDDAT),
106 SAVE_ITEM(S3C2410_GPDUP),
108 SAVE_ITEM(S3C2410_GPECON),
109 SAVE_ITEM(S3C2410_GPEDAT),
110 SAVE_ITEM(S3C2410_GPEUP),
112 SAVE_ITEM(S3C2410_GPFCON),
113 SAVE_ITEM(S3C2410_GPFDAT),
114 SAVE_ITEM(S3C2410_GPFUP),
116 SAVE_ITEM(S3C2410_GPGCON),
117 SAVE_ITEM(S3C2410_GPGDAT),
118 SAVE_ITEM(S3C2410_GPGUP),
120 SAVE_ITEM(S3C2410_GPHCON),
121 SAVE_ITEM(S3C2410_GPHDAT),
122 SAVE_ITEM(S3C2410_GPHUP),
124 SAVE_ITEM(S3C2410_DCLKCON),
127 #ifdef CONFIG_S3C2410_PM_DEBUG
129 #define SAVE_UART(va) \
130 SAVE_ITEM((va) + S3C2410_ULCON), \
131 SAVE_ITEM((va) + S3C2410_UCON), \
132 SAVE_ITEM((va) + S3C2410_UFCON), \
133 SAVE_ITEM((va) + S3C2410_UMCON), \
134 SAVE_ITEM((va) + S3C2410_UBRDIV)
136 static struct sleep_save uart_save[] = {
137 SAVE_UART(S3C24XX_VA_UART0),
138 SAVE_UART(S3C24XX_VA_UART1),
139 #ifndef CONFIG_CPU_S3C2400
140 SAVE_UART(S3C24XX_VA_UART2),
146 * we send the debug to printascii() to allow it to be seen if the
147 * system never wakes up from the sleep
150 extern void printascii(const char *);
152 static void pm_dbg(const char *fmt, ...)
158 vsprintf(buff, fmt, va);
164 static void s3c2410_pm_debug_init(void)
166 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
168 /* re-start uart clocks */
169 tmp |= S3C2410_CLKCON_UART0;
170 tmp |= S3C2410_CLKCON_UART1;
171 tmp |= S3C2410_CLKCON_UART2;
173 __raw_writel(tmp, S3C2410_CLKCON);
177 #define DBG(fmt...) pm_dbg(fmt)
179 #define DBG(fmt...) printk(KERN_DEBUG fmt)
181 #define s3c2410_pm_debug_init() do { } while(0)
183 static struct sleep_save uart_save[] = {};
186 #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
188 /* suspend checking code...
190 * this next area does a set of crc checks over all the installed
191 * memory, so the system can verify if the resume was ok.
193 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
194 * increasing it will mean that the area corrupted will be less easy to spot,
195 * and reducing the size will cause the CRC save area to grow
198 #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
200 static u32 crc_size; /* size needed for the crc block */
201 static u32 *crcs; /* allocated over suspend/resume */
203 typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
205 /* s3c2410_pm_run_res
207 * go thorugh the given resource list, and look for system ram
210 static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
212 while (ptr != NULL) {
213 if (ptr->child != NULL)
214 s3c2410_pm_run_res(ptr->child, fn, arg);
216 if ((ptr->flags & IORESOURCE_MEM) &&
217 strcmp(ptr->name, "System RAM") == 0) {
218 DBG("Found system RAM at %08lx..%08lx\n",
219 ptr->start, ptr->end);
220 arg = (fn)(ptr, arg);
227 static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
229 s3c2410_pm_run_res(&iomem_resource, fn, arg);
232 static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
234 u32 size = (u32)(res->end - res->start)+1;
236 size += CHECK_CHUNKSIZE-1;
237 size /= CHECK_CHUNKSIZE;
239 DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
241 *val += size * sizeof(u32);
245 /* s3c2410_pm_prepare_check
247 * prepare the necessary information for creating the CRCs. This
248 * must be done before the final save, as it will require memory
249 * allocating, and thus touching bits of the kernel we do not
253 static void s3c2410_pm_check_prepare(void)
257 s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
259 DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
261 crcs = kmalloc(crc_size+4, GFP_KERNEL);
263 printk(KERN_ERR "Cannot allocated CRC save area\n");
266 static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
268 unsigned long addr, left;
270 for (addr = res->start; addr < res->end;
271 addr += CHECK_CHUNKSIZE) {
272 left = res->end - addr;
274 if (left > CHECK_CHUNKSIZE)
275 left = CHECK_CHUNKSIZE;
277 *val = crc32_le(~0, phys_to_virt(addr), left);
284 /* s3c2410_pm_check_store
286 * compute the CRC values for the memory blocks before the final
290 static void s3c2410_pm_check_store(void)
293 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
298 * return TRUE if the area defined by ptr..ptr+size contatins the
302 static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
304 if ((what+whatsz) < ptr)
307 if (what > (ptr+size))
313 static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
315 void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
321 for (addr = res->start; addr < res->end;
322 addr += CHECK_CHUNKSIZE) {
323 left = res->end - addr;
325 if (left > CHECK_CHUNKSIZE)
326 left = CHECK_CHUNKSIZE;
328 ptr = phys_to_virt(addr);
330 if (in_region(ptr, left, crcs, crc_size)) {
331 DBG("skipping %08lx, has crc block in\n", addr);
335 if (in_region(ptr, left, save_at, 32*4 )) {
336 DBG("skipping %08lx, has save block in\n", addr);
340 /* calculate and check the checksum */
342 calc = crc32_le(~0, ptr, left);
344 printk(KERN_ERR PFX "Restore CRC error at "
345 "%08lx (%08x vs %08x)\n", addr, calc, *val);
347 DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
358 /* s3c2410_pm_check_restore
360 * check the CRCs after the restore event and free the memory used
364 static void s3c2410_pm_check_restore(void)
367 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
375 #define s3c2410_pm_check_prepare() do { } while(0)
376 #define s3c2410_pm_check_restore() do { } while(0)
377 #define s3c2410_pm_check_store() do { } while(0)
380 /* helper functions to save and restore register state */
382 void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
384 for (; count > 0; count--, ptr++) {
385 ptr->val = __raw_readl(ptr->reg);
386 DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
390 /* s3c2410_pm_do_restore
392 * restore the system from the given list of saved registers
394 * Note, we do not use DBG() in here, as the system may not have
395 * restore the UARTs state yet
398 void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
400 for (; count > 0; count--, ptr++) {
401 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
402 ptr->reg, ptr->val, __raw_readl(ptr->reg));
404 __raw_writel(ptr->val, ptr->reg);
408 /* s3c2410_pm_do_restore_core
410 * similar to s3c2410_pm_do_restore_core
412 * WARNING: Do not put any debug in here that may effect memory or use
413 * peripherals, as things may be changing!
416 static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
418 for (; count > 0; count--, ptr++) {
419 __raw_writel(ptr->val, ptr->reg);
423 /* s3c2410_pm_show_resume_irqs
425 * print any IRQs asserted at resume time (ie, we woke from)
428 static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
435 for (i = 0; i <= 31; i++) {
436 if ((which) & (1L<<i)) {
437 DBG("IRQ %d asserted at resume\n", start+i);
442 /* s3c2410_pm_check_resume_pin
444 * check to see if the pin is configured correctly for sleep mode, and
445 * make any necessary adjustments if it is not
448 static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
450 unsigned long irqstate;
451 unsigned long pinstate;
452 int irq = s3c2410_gpio_getirq(pin);
455 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
457 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
459 pinstate = s3c2410_gpio_getcfg(pin);
460 pinstate >>= S3C2410_GPIO_OFFSET(pin)*2;
463 if (pinstate == 0x02)
464 DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
466 if (pinstate == 0x02) {
467 DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
468 s3c2410_gpio_cfgpin(pin, 0x00);
473 /* s3c2410_pm_configure_extint
475 * configure all external interrupt pins
478 static void s3c2410_pm_configure_extint(void)
482 /* for each of the external interrupts (EINT0..EINT15) we
483 * need to check wether it is an external interrupt source,
484 * and then configure it as an input if it is not
487 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
488 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
491 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
492 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
496 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
500 * central control for sleep/resume process
503 static int s3c2410_pm_enter(suspend_state_t state)
505 unsigned long regs_save[16];
508 /* ensure the debug is initialised (if enabled) */
510 s3c2410_pm_debug_init();
512 DBG("s3c2410_pm_enter(%d)\n", state);
514 if (state != PM_SUSPEND_MEM) {
515 printk(KERN_ERR PFX "error: only PM_SUSPEND_MEM supported\n");
519 /* check if we have anything to wake-up with... bad things seem
520 * to happen if you suspend with no wakeup (system will often
521 * require a full power-cycle)
524 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
525 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
526 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
527 printk(KERN_ERR PFX "Aborting sleep\n");
531 /* prepare check area if configured */
533 s3c2410_pm_check_prepare();
535 /* store the physical address of the register recovery block */
537 s3c2410_sleep_save_phys = virt_to_phys(regs_save);
539 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
541 /* ensure at least GESTATUS3 has the resume address */
543 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
545 DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
546 DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
548 /* save all necessary core registers not covered by the drivers */
550 s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
551 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
552 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
554 /* set the irq configuration for wake */
556 s3c2410_pm_configure_extint();
558 DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
559 s3c_irqwake_intmask, s3c_irqwake_eintmask);
561 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
562 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
564 /* ack any outstanding external interrupts before we go to sleep */
566 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
568 /* flush cache back to ram */
570 arm920_flush_kern_cache_all();
572 s3c2410_pm_check_store();
574 /* send the cpu to sleep... */
576 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
578 s3c2410_cpu_suspend(regs_save);
580 /* restore the cpu state */
584 /* unset the return-from-sleep flag, to ensure reset */
586 tmp = __raw_readl(S3C2410_GSTATUS2);
587 tmp &= S3C2410_GSTATUS2_OFFRESET;
588 __raw_writel(tmp, S3C2410_GSTATUS2);
590 /* restore the system state */
592 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
593 s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
594 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
596 s3c2410_pm_debug_init();
598 /* check what irq (if any) restored the system */
600 DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
601 __raw_readl(S3C2410_SRCPND),
602 __raw_readl(S3C2410_EINTPEND));
604 s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
605 s3c_irqwake_intmask);
607 s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
608 s3c_irqwake_eintmask);
610 DBG("post sleep, preparing to return\n");
612 s3c2410_pm_check_restore();
614 /* ok, let's return from sleep */
616 DBG("S3C2410 PM Resume (post-restore)\n");
621 * Called after processes are frozen, but before we shut down devices.
623 static int s3c2410_pm_prepare(suspend_state_t state)
629 * Called after devices are re-setup, but before processes are thawed.
631 static int s3c2410_pm_finish(suspend_state_t state)
637 * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
639 static struct pm_ops s3c2410_pm_ops = {
640 .pm_disk_mode = PM_DISK_FIRMWARE,
641 .prepare = s3c2410_pm_prepare,
642 .enter = s3c2410_pm_enter,
643 .finish = s3c2410_pm_finish,
648 * Attach the power management functions. This should be called
649 * from the board specific initialisation if the board supports
653 int __init s3c2410_pm_init(void)
655 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
657 pm_set_ops(&s3c2410_pm_ops);