1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.simtec.co.uk/products/EB2410ITX/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/sysdev.h>
20 #include <linux/serial_core.h>
21 #include <linux/platform_device.h>
22 #include <linux/dm9000.h>
23 #include <linux/ata_platform.h>
25 #include <net/ax88796.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
31 #include <asm/arch/bast-map.h>
32 #include <asm/arch/bast-irq.h>
33 #include <asm/arch/bast-cpld.h>
35 #include <asm/hardware.h>
38 #include <asm/mach-types.h>
40 //#include <asm/debug-ll.h>
41 #include <asm/plat-s3c/regs-serial.h>
42 #include <asm/arch/regs-gpio.h>
43 #include <asm/arch/regs-mem.h>
44 #include <asm/arch/regs-lcd.h>
46 #include <asm/plat-s3c/nand.h>
47 #include <asm/plat-s3c/iic.h>
48 #include <asm/arch/fb.h>
50 #include <linux/mtd/mtd.h>
51 #include <linux/mtd/nand.h>
52 #include <linux/mtd/nand_ecc.h>
53 #include <linux/mtd/partitions.h>
55 #include <linux/serial_8250.h>
57 #include <asm/plat-s3c24xx/clock.h>
58 #include <asm/plat-s3c24xx/devs.h>
59 #include <asm/plat-s3c24xx/cpu.h>
60 #include "usb-simtec.h"
62 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
64 /* macros for virtual address mods for the io space entries */
65 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
66 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
67 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
68 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
70 /* macros to modify the physical addresses for io space */
72 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
73 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
74 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
75 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
77 static struct map_desc bast_iodesc[] __initdata = {
80 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
81 .pfn = PA_CS2(BAST_PA_ISAIO),
85 .virtual = (u32)S3C24XX_VA_ISA_WORD,
86 .pfn = PA_CS3(BAST_PA_ISAIO),
90 /* bast CPLD control registers, and external interrupt controls */
92 .virtual = (u32)BAST_VA_CTRL1,
93 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
97 .virtual = (u32)BAST_VA_CTRL2,
98 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
102 .virtual = (u32)BAST_VA_CTRL3,
103 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
107 .virtual = (u32)BAST_VA_CTRL4,
108 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
114 .virtual = (u32)BAST_VA_PC104_IRQREQ,
115 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
119 .virtual = (u32)BAST_VA_PC104_IRQRAW,
120 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
124 .virtual = (u32)BAST_VA_PC104_IRQMASK,
125 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
130 /* peripheral space... one for each of fast/slow/byte/16bit */
131 /* note, ide is only decoded in word space, even though some registers
135 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
136 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
137 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
140 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
141 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
142 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
145 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
146 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
147 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
150 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
151 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
152 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
155 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
156 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
157 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
159 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
175 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
182 .clocks = bast_serial_clocks,
183 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
191 .clocks = bast_serial_clocks,
192 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
194 /* port 2 is not actually used */
201 .clocks = bast_serial_clocks,
202 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
206 /* NOR Flash on BAST board */
208 static struct resource bast_nor_resource[] = {
210 .start = S3C2410_CS1 + 0x4000000,
211 .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
212 .flags = IORESOURCE_MEM,
216 static struct platform_device bast_device_nor = {
219 .num_resources = ARRAY_SIZE(bast_nor_resource),
220 .resource = bast_nor_resource,
223 /* NAND Flash on BAST board */
226 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
228 /* ensure that an nRESET is not generated on resume. */
229 s3c2410_gpio_setpin(S3C2410_GPA21, 1);
230 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
235 static int bast_pm_resume(struct sys_device *sd)
237 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
242 #define bast_pm_suspend NULL
243 #define bast_pm_resume NULL
246 static struct sysdev_class bast_pm_sysclass = {
248 .suspend = bast_pm_suspend,
249 .resume = bast_pm_resume,
252 static struct sys_device bast_pm_sysdev = {
253 .cls = &bast_pm_sysclass,
256 static int smartmedia_map[] = { 0 };
257 static int chip0_map[] = { 1 };
258 static int chip1_map[] = { 2 };
259 static int chip2_map[] = { 3 };
261 static struct mtd_partition bast_default_nand_part[] = {
263 .name = "Boot Agent",
269 .size = SZ_4M - SZ_16K,
275 .size = MTDPART_SIZ_FULL,
279 /* the bast has 4 selectable slots for nand-flash, the three
280 * on-board chip areas, as well as the external SmartMedia
283 * Note, there is no current hot-plug support for the SmartMedia
287 static struct s3c2410_nand_set bast_nand_sets[] = {
289 .name = "SmartMedia",
291 .nr_map = smartmedia_map,
292 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
293 .partitions = bast_default_nand_part,
299 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
300 .partitions = bast_default_nand_part,
306 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
307 .partitions = bast_default_nand_part,
313 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
314 .partitions = bast_default_nand_part,
318 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
322 slot = set->nr_map[slot] & 3;
324 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
325 slot, set, set->nr_map);
327 tmp = __raw_readb(BAST_VA_CTRL2);
328 tmp &= BAST_CPLD_CTLR2_IDERST;
330 tmp |= BAST_CPLD_CTRL2_WNAND;
332 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
334 __raw_writeb(tmp, BAST_VA_CTRL2);
337 static struct s3c2410_platform_nand bast_nand_info = {
341 .nr_sets = ARRAY_SIZE(bast_nand_sets),
342 .sets = bast_nand_sets,
343 .select_chip = bast_nand_select,
348 static struct resource bast_dm9k_resource[] = {
350 .start = S3C2410_CS5 + BAST_PA_DM9000,
351 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
352 .flags = IORESOURCE_MEM,
355 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
356 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
357 .flags = IORESOURCE_MEM,
362 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
367 /* for the moment we limit ourselves to 16bit IO until some
368 * better IO routines can be written and tested
371 static struct dm9000_plat_data bast_dm9k_platdata = {
372 .flags = DM9000_PLATF_16BITONLY,
375 static struct platform_device bast_device_dm9k = {
378 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
379 .resource = bast_dm9k_resource,
381 .platform_data = &bast_dm9k_platdata,
387 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
388 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
389 #define SERIAL_CLK (1843200)
391 static struct plat_serial8250_port bast_sio_data[] = {
393 .mapbase = SERIAL_BASE + 0x2f8,
394 .irq = IRQ_PCSERIAL1,
395 .flags = SERIAL_FLAGS,
398 .uartclk = SERIAL_CLK,
401 .mapbase = SERIAL_BASE + 0x3f8,
402 .irq = IRQ_PCSERIAL2,
403 .flags = SERIAL_FLAGS,
406 .uartclk = SERIAL_CLK,
411 static struct platform_device bast_sio = {
412 .name = "serial8250",
413 .id = PLAT8250_DEV_PLATFORM,
415 .platform_data = &bast_sio_data,
419 /* we have devices on the bus which cannot work much over the
420 * standard 100KHz i2c bus frequency
423 static struct s3c2410_platform_i2c bast_i2c_info = {
426 .bus_freq = 100*1000,
427 .max_freq = 130*1000,
430 /* Asix AX88796 10/100 ethernet controller */
432 static struct ax_plat_data bast_asix_platdata = {
433 .flags = AXFLG_MAC_FROMDEV,
439 static struct resource bast_asix_resource[] = {
441 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
442 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
443 .flags = IORESOURCE_MEM,
446 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
447 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
448 .flags = IORESOURCE_MEM,
453 .flags = IORESOURCE_IRQ
457 static struct platform_device bast_device_asix = {
460 .num_resources = ARRAY_SIZE(bast_asix_resource),
461 .resource = bast_asix_resource,
463 .platform_data = &bast_asix_platdata
467 /* Asix AX88796 10/100 ethernet controller parallel port */
469 static struct resource bast_asixpp_resource[] = {
471 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
472 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
473 .flags = IORESOURCE_MEM,
477 static struct platform_device bast_device_axpp = {
478 .name = "ax88796-pp",
480 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
481 .resource = bast_asixpp_resource,
484 /* LCD/VGA controller */
486 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
488 .type = S3C2410_LCDCON1_TFT,
503 .lcdcon5 = 0x00014b02,
506 .type = S3C2410_LCDCON1_TFT,
521 .lcdcon5 = 0x00014b02,
524 .type = S3C2410_LCDCON1_TFT,
539 .lcdcon5 = 0x00014b02,
543 /* LCD/VGA controller */
545 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
547 .displays = bast_lcd_info,
548 .num_displays = ARRAY_SIZE(bast_lcd_info),
549 .default_display = 1,
553 /* Standard BAST devices */
555 static struct platform_device *bast_devices[] __initdata = {
569 static struct clk *bast_clocks[] = {
577 static void __init bast_map_io(void)
579 /* initialise the clocks */
581 s3c24xx_dclk0.parent = &clk_upll;
582 s3c24xx_dclk0.rate = 12*1000*1000;
584 s3c24xx_dclk1.parent = &clk_upll;
585 s3c24xx_dclk1.rate = 24*1000*1000;
587 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
588 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
590 s3c24xx_uclk.parent = &s3c24xx_clkout1;
592 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
594 s3c_device_nand.dev.platform_data = &bast_nand_info;
595 s3c_device_i2c.dev.platform_data = &bast_i2c_info;
597 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
598 s3c24xx_init_clocks(0);
599 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
604 static void __init bast_init(void)
606 sysdev_class_register(&bast_pm_sysclass);
607 sysdev_register(&bast_pm_sysdev);
609 s3c24xx_fb_set_platdata(&bast_fb_info);
610 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
613 MACHINE_START(BAST, "Simtec-BAST")
614 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
615 .phys_io = S3C2410_PA_UART,
616 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
617 .boot_params = S3C2410_SDRAM_PA + 0x100,
618 .map_io = bast_map_io,
619 .init_irq = s3c24xx_init_irq,
620 .init_machine = bast_init,
621 .timer = &s3c24xx_timer,