1 /* linux/arch/arm/mach-s3c2410/irq.c
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
46 * 28-Jun-2005 Ben Dooks
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to seperate file
53 #include <linux/init.h>
54 #include <linux/module.h>
55 #include <linux/interrupt.h>
56 #include <linux/ioport.h>
57 #include <linux/ptrace.h>
58 #include <linux/sysdev.h>
60 #include <asm/hardware.h>
64 #include <asm/mach/irq.h>
66 #include <asm/arch/regs-irq.h>
67 #include <asm/arch/regs-gpio.h>
73 /* wakeup irq control */
77 /* state for IRQs over sleep */
79 /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
81 * set bit to 1 in allow bitfield to enable the wakeup settings on it
84 unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
85 unsigned long s3c_irqwake_intmask = 0xffffffffL;
86 unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
87 unsigned long s3c_irqwake_eintmask = 0xffffffffL;
90 s3c_irq_wake(unsigned int irqno, unsigned int state)
92 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
94 if (!(s3c_irqwake_intallow & irqbit))
97 printk(KERN_INFO "wake %s for irq %d\n",
98 state ? "enabled" : "disabled", irqno);
101 s3c_irqwake_intmask |= irqbit;
103 s3c_irqwake_intmask &= ~irqbit;
109 s3c_irqext_wake(unsigned int irqno, unsigned int state)
111 unsigned long bit = 1L << (irqno - EXTINT_OFF);
113 if (!(s3c_irqwake_eintallow & bit))
116 printk(KERN_INFO "wake %s for irq %d\n",
117 state ? "enabled" : "disabled", irqno);
120 s3c_irqwake_eintmask |= bit;
122 s3c_irqwake_eintmask &= ~bit;
128 #define s3c_irqext_wake NULL
129 #define s3c_irq_wake NULL
134 s3c_irq_mask(unsigned int irqno)
140 mask = __raw_readl(S3C2410_INTMSK);
141 mask |= 1UL << irqno;
142 __raw_writel(mask, S3C2410_INTMSK);
146 s3c_irq_ack(unsigned int irqno)
148 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
150 __raw_writel(bitval, S3C2410_SRCPND);
151 __raw_writel(bitval, S3C2410_INTPND);
155 s3c_irq_maskack(unsigned int irqno)
157 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
160 mask = __raw_readl(S3C2410_INTMSK);
161 __raw_writel(mask|bitval, S3C2410_INTMSK);
163 __raw_writel(bitval, S3C2410_SRCPND);
164 __raw_writel(bitval, S3C2410_INTPND);
169 s3c_irq_unmask(unsigned int irqno)
173 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
174 irqdbf2("s3c_irq_unmask %d\n", irqno);
178 mask = __raw_readl(S3C2410_INTMSK);
179 mask &= ~(1UL << irqno);
180 __raw_writel(mask, S3C2410_INTMSK);
183 struct irqchip s3c_irq_level_chip = {
185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask,
187 .unmask = s3c_irq_unmask,
188 .set_wake = s3c_irq_wake
191 static struct irqchip s3c_irq_chip = {
194 .mask = s3c_irq_mask,
195 .unmask = s3c_irq_unmask,
196 .set_wake = s3c_irq_wake
200 s3c_irqext_mask(unsigned int irqno)
206 mask = __raw_readl(S3C24XX_EINTMASK);
207 mask |= ( 1UL << irqno);
208 __raw_writel(mask, S3C24XX_EINTMASK);
210 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
211 /* check to see if all need masking */
213 if ((mask & (0xf << 4)) == (0xf << 4)) {
214 /* all masked, mask the parent */
215 s3c_irq_mask(IRQ_EINT4t7);
218 /* todo: the same check as above for the rest of the irq regs...*/
224 s3c_irqext_ack(unsigned int irqno)
230 bit = 1UL << (irqno - EXTINT_OFF);
233 mask = __raw_readl(S3C24XX_EINTMASK);
235 __raw_writel(bit, S3C24XX_EINTPEND);
237 req = __raw_readl(S3C24XX_EINTPEND);
240 /* not sure if we should be acking the parent irq... */
242 if (irqno <= IRQ_EINT7 ) {
243 if ((req & 0xf0) == 0)
244 s3c_irq_ack(IRQ_EINT4t7);
247 s3c_irq_ack(IRQ_EINT8t23);
252 s3c_irqext_unmask(unsigned int irqno)
258 mask = __raw_readl(S3C24XX_EINTMASK);
259 mask &= ~( 1UL << irqno);
260 __raw_writel(mask, S3C24XX_EINTMASK);
262 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
266 s3c_irqext_type(unsigned int irq, unsigned int type)
268 void __iomem *extint_reg;
269 void __iomem *gpcon_reg;
270 unsigned long gpcon_offset, extint_offset;
271 unsigned long newvalue = 0, value;
273 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
275 gpcon_reg = S3C2410_GPFCON;
276 extint_reg = S3C24XX_EXTINT0;
277 gpcon_offset = (irq - IRQ_EINT0) * 2;
278 extint_offset = (irq - IRQ_EINT0) * 4;
280 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
282 gpcon_reg = S3C2410_GPFCON;
283 extint_reg = S3C24XX_EXTINT0;
284 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
285 extint_offset = (irq - (EXTINT_OFF)) * 4;
287 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
289 gpcon_reg = S3C2410_GPGCON;
290 extint_reg = S3C24XX_EXTINT1;
291 gpcon_offset = (irq - IRQ_EINT8) * 2;
292 extint_offset = (irq - IRQ_EINT8) * 4;
294 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
296 gpcon_reg = S3C2410_GPGCON;
297 extint_reg = S3C24XX_EXTINT2;
298 gpcon_offset = (irq - IRQ_EINT8) * 2;
299 extint_offset = (irq - IRQ_EINT16) * 4;
303 /* Set the GPIO to external interrupt mode */
304 value = __raw_readl(gpcon_reg);
305 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
306 __raw_writel(value, gpcon_reg);
308 /* Set the external interrupt to pointed trigger type */
312 printk(KERN_WARNING "No edge setting!\n");
316 newvalue = S3C2410_EXTINT_RISEEDGE;
320 newvalue = S3C2410_EXTINT_FALLEDGE;
324 newvalue = S3C2410_EXTINT_BOTHEDGE;
328 newvalue = S3C2410_EXTINT_LOWLEV;
332 newvalue = S3C2410_EXTINT_HILEV;
336 printk(KERN_ERR "No such irq type %d", type);
340 value = __raw_readl(extint_reg);
341 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
342 __raw_writel(value, extint_reg);
347 static struct irqchip s3c_irqext_chip = {
349 .mask = s3c_irqext_mask,
350 .unmask = s3c_irqext_unmask,
351 .ack = s3c_irqext_ack,
352 .set_type = s3c_irqext_type,
353 .set_wake = s3c_irqext_wake
356 static struct irqchip s3c_irq_eint0t4 = {
359 .mask = s3c_irq_mask,
360 .unmask = s3c_irq_unmask,
361 .set_wake = s3c_irq_wake,
362 .set_type = s3c_irqext_type,
365 /* mask values for the parent registers for each of the interrupt types */
367 #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
368 #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
369 #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
370 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
376 s3c_irq_uart0_mask(unsigned int irqno)
378 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
382 s3c_irq_uart0_unmask(unsigned int irqno)
384 s3c_irqsub_unmask(irqno, INTMSK_UART0);
388 s3c_irq_uart0_ack(unsigned int irqno)
390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
393 static struct irqchip s3c_irq_uart0 = {
395 .mask = s3c_irq_uart0_mask,
396 .unmask = s3c_irq_uart0_unmask,
397 .ack = s3c_irq_uart0_ack,
403 s3c_irq_uart1_mask(unsigned int irqno)
405 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
409 s3c_irq_uart1_unmask(unsigned int irqno)
411 s3c_irqsub_unmask(irqno, INTMSK_UART1);
415 s3c_irq_uart1_ack(unsigned int irqno)
417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
420 static struct irqchip s3c_irq_uart1 = {
422 .mask = s3c_irq_uart1_mask,
423 .unmask = s3c_irq_uart1_unmask,
424 .ack = s3c_irq_uart1_ack,
430 s3c_irq_uart2_mask(unsigned int irqno)
432 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
436 s3c_irq_uart2_unmask(unsigned int irqno)
438 s3c_irqsub_unmask(irqno, INTMSK_UART2);
442 s3c_irq_uart2_ack(unsigned int irqno)
444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
447 static struct irqchip s3c_irq_uart2 = {
449 .mask = s3c_irq_uart2_mask,
450 .unmask = s3c_irq_uart2_unmask,
451 .ack = s3c_irq_uart2_ack,
454 /* ADC and Touchscreen */
457 s3c_irq_adc_mask(unsigned int irqno)
459 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
463 s3c_irq_adc_unmask(unsigned int irqno)
465 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
469 s3c_irq_adc_ack(unsigned int irqno)
471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
474 static struct irqchip s3c_irq_adc = {
476 .mask = s3c_irq_adc_mask,
477 .unmask = s3c_irq_adc_unmask,
478 .ack = s3c_irq_adc_ack,
481 /* irq demux for adc */
482 static void s3c_irq_demux_adc(unsigned int irq,
483 struct irqdesc *desc)
485 unsigned int subsrc, submsk;
486 unsigned int offset = 9;
487 struct irqdesc *mydesc;
489 /* read the current pending interrupts, and the mask
490 * for what it is available */
492 subsrc = __raw_readl(S3C2410_SUBSRCPND);
493 submsk = __raw_readl(S3C2410_INTSUBMSK);
501 mydesc = irq_desc + IRQ_TC;
502 desc_handle_irq(IRQ_TC, mydesc);
505 mydesc = irq_desc + IRQ_ADC;
506 desc_handle_irq(IRQ_ADC, mydesc);
511 static void s3c_irq_demux_uart(unsigned int start)
513 unsigned int subsrc, submsk;
514 unsigned int offset = start - IRQ_S3CUART_RX0;
515 struct irqdesc *desc;
517 /* read the current pending interrupts, and the mask
518 * for what it is available */
520 subsrc = __raw_readl(S3C2410_SUBSRCPND);
521 submsk = __raw_readl(S3C2410_INTSUBMSK);
523 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
524 start, offset, subsrc, submsk);
531 desc = irq_desc + start;
534 desc_handle_irq(start, desc);
539 desc_handle_irq(start+1, desc);
544 desc_handle_irq(start+2, desc);
548 /* uart demux entry points */
551 s3c_irq_demux_uart0(unsigned int irq,
552 struct irqdesc *desc)
555 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
559 s3c_irq_demux_uart1(unsigned int irq,
560 struct irqdesc *desc)
563 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
567 s3c_irq_demux_uart2(unsigned int irq,
568 struct irqdesc *desc)
571 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
575 s3c_irq_demux_extint8(unsigned int irq,
576 struct irqdesc *desc)
578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
582 eintpnd &= ~0xff; /* ignore lower irqs */
584 /* we may as well handle all the pending IRQs here */
587 irq = __ffs(eintpnd);
588 eintpnd &= ~(1<<irq);
590 irq += (IRQ_EINT4 - 4);
591 desc_handle_irq(irq, irq_desc + irq);
597 s3c_irq_demux_extint4t7(unsigned int irq,
598 struct irqdesc *desc)
600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
604 eintpnd &= 0xff; /* only lower irqs */
606 /* we may as well handle all the pending IRQs here */
609 irq = __ffs(eintpnd);
610 eintpnd &= ~(1<<irq);
612 irq += (IRQ_EINT4 - 4);
614 desc_handle_irq(irq, irq_desc + irq);
620 static struct sleep_save irq_save[] = {
621 SAVE_ITEM(S3C2410_INTMSK),
622 SAVE_ITEM(S3C2410_INTSUBMSK),
625 /* the extint values move between the s3c2410/s3c2440 and the s3c2412
626 * so we use an array to hold them, and to calculate the address of
627 * the register at run-time
630 static unsigned long save_extint[3];
631 static unsigned long save_eintflt[4];
632 static unsigned long save_eintmask;
634 int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
638 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
639 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
641 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
642 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
644 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
645 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
650 int s3c24xx_irq_resume(struct sys_device *dev)
654 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
655 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
657 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
658 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
660 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
661 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
667 #define s3c24xx_irq_suspend NULL
668 #define s3c24xx_irq_resume NULL
673 * Initialise S3C2410 IRQ system
676 void __init s3c24xx_init_irq(void)
683 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
685 /* first, clear all interrupts pending... */
688 for (i = 0; i < 4; i++) {
689 pend = __raw_readl(S3C24XX_EINTPEND);
691 if (pend == 0 || pend == last)
694 __raw_writel(pend, S3C24XX_EINTPEND);
695 printk("irq: clearing pending ext status %08x\n", (int)pend);
700 for (i = 0; i < 4; i++) {
701 pend = __raw_readl(S3C2410_INTPND);
703 if (pend == 0 || pend == last)
706 __raw_writel(pend, S3C2410_SRCPND);
707 __raw_writel(pend, S3C2410_INTPND);
708 printk("irq: clearing pending status %08x\n", (int)pend);
713 for (i = 0; i < 4; i++) {
714 pend = __raw_readl(S3C2410_SUBSRCPND);
716 if (pend == 0 || pend == last)
719 printk("irq: clearing subpending status %08x\n", (int)pend);
720 __raw_writel(pend, S3C2410_SUBSRCPND);
724 /* register the main interrupts */
726 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
728 for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
729 /* set all the s3c2410 internal irqs */
732 /* deal with the special IRQs (cascaded) */
740 set_irq_chip(irqno, &s3c_irq_level_chip);
741 set_irq_handler(irqno, do_level_IRQ);
750 //irqdbf("registering irq %d (s3c irq)\n", irqno);
751 set_irq_chip(irqno, &s3c_irq_chip);
752 set_irq_handler(irqno, do_edge_IRQ);
753 set_irq_flags(irqno, IRQF_VALID);
757 /* setup the cascade irq handlers */
759 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
760 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
762 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
763 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
764 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
765 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
767 /* external interrupts */
769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
770 irqdbf("registering irq %d (ext int)\n", irqno);
771 set_irq_chip(irqno, &s3c_irq_eint0t4);
772 set_irq_handler(irqno, do_edge_IRQ);
773 set_irq_flags(irqno, IRQF_VALID);
776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
777 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
778 set_irq_chip(irqno, &s3c_irqext_chip);
779 set_irq_handler(irqno, do_edge_IRQ);
780 set_irq_flags(irqno, IRQF_VALID);
783 /* register the uart interrupts */
785 irqdbf("s3c2410: registering external interrupts\n");
787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
789 set_irq_chip(irqno, &s3c_irq_uart0);
790 set_irq_handler(irqno, do_level_IRQ);
791 set_irq_flags(irqno, IRQF_VALID);
794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
796 set_irq_chip(irqno, &s3c_irq_uart1);
797 set_irq_handler(irqno, do_level_IRQ);
798 set_irq_flags(irqno, IRQF_VALID);
801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
803 set_irq_chip(irqno, &s3c_irq_uart2);
804 set_irq_handler(irqno, do_level_IRQ);
805 set_irq_flags(irqno, IRQF_VALID);
808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
809 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
810 set_irq_chip(irqno, &s3c_irq_adc);
811 set_irq_handler(irqno, do_edge_IRQ);
812 set_irq_flags(irqno, IRQF_VALID);
815 irqdbf("s3c2410: registered interrupt handlers\n");