1 /* linux/arch/arm/mach-s3c2410/cpu.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/platform_device.h>
31 #include <asm/hardware.h>
34 #include <asm/delay.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
39 #include <asm/arch/regs-gpio.h>
40 #include <asm/arch/regs-serial.h>
55 void (*map_io)(struct map_desc *mach_desc, int size);
56 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
57 void (*init_clocks)(int xtal);
62 /* table of supported CPUs */
64 static const char name_s3c2400[] = "S3C2400";
65 static const char name_s3c2410[] = "S3C2410";
66 static const char name_s3c2412[] = "S3C2412";
67 static const char name_s3c2440[] = "S3C2440";
68 static const char name_s3c2442[] = "S3C2442";
69 static const char name_s3c2410a[] = "S3C2410A";
70 static const char name_s3c2440a[] = "S3C2440A";
72 static struct cpu_table cpu_ids[] __initdata = {
76 .map_io = s3c2410_map_io,
77 .init_clocks = s3c2410_init_clocks,
78 .init_uarts = s3c2410_init_uarts,
85 .map_io = s3c2410_map_io,
86 .init_clocks = s3c2410_init_clocks,
87 .init_uarts = s3c2410_init_uarts,
94 .map_io = s3c244x_map_io,
95 .init_clocks = s3c244x_init_clocks,
96 .init_uarts = s3c244x_init_uarts,
101 .idcode = 0x32440001,
102 .idmask = 0xffffffff,
103 .map_io = s3c244x_map_io,
104 .init_clocks = s3c244x_init_clocks,
105 .init_uarts = s3c244x_init_uarts,
106 .init = s3c2440_init,
107 .name = name_s3c2440a
110 .idcode = 0x32440aaa,
111 .idmask = 0xffffffff,
112 .map_io = s3c244x_map_io,
113 .init_clocks = s3c244x_init_clocks,
114 .init_uarts = s3c244x_init_uarts,
115 .init = s3c2442_init,
119 .idcode = 0x32412001,
120 .idmask = 0xffffffff,
121 .map_io = s3c2412_map_io,
122 .init_clocks = s3c2412_init_clocks,
123 .init_uarts = s3c2412_init_uarts,
124 .init = s3c2412_init,
125 .name = name_s3c2412,
127 { /* a newer version of the s3c2412 */
128 .idcode = 0x32412003,
129 .idmask = 0xffffffff,
130 .map_io = s3c2412_map_io,
131 .init_clocks = s3c2412_init_clocks,
132 .init_uarts = s3c2412_init_uarts,
133 .init = s3c2412_init,
134 .name = name_s3c2412,
137 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
138 .idmask = 0xffffffff,
139 .map_io = s3c2400_map_io,
140 .init_clocks = s3c2400_init_clocks,
141 .init_uarts = s3c2400_init_uarts,
142 .init = s3c2400_init,
147 /* minimal IO mapping */
149 static struct map_desc s3c_iodesc[] __initdata = {
157 static struct cpu_table *
158 s3c_lookup_cpu(unsigned long idcode)
160 struct cpu_table *tab;
164 for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
165 if ((idcode & tab->idmask) == tab->idcode)
172 /* board information */
174 static struct s3c24xx_board *board;
176 void s3c24xx_set_board(struct s3c24xx_board *b)
182 if (b->clocks_count != 0) {
183 struct clk **ptr = b->clocks;
185 for (i = b->clocks_count; i > 0; i--, ptr++)
186 s3c24xx_register_clock(*ptr);
190 /* cpu information */
192 static struct cpu_table *cpu;
194 static unsigned long s3c24xx_read_idcode_v5(void)
196 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
197 return __raw_readl(S3C2412_GSTATUS1);
199 return 1UL; /* don't look like an 2400 */
203 static unsigned long s3c24xx_read_idcode_v4(void)
205 #ifndef CONFIG_CPU_S3C2400
206 return __raw_readl(S3C2410_GSTATUS1);
212 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
214 unsigned long idcode = 0x0;
216 /* initialise the io descriptors we need for initialisation */
217 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
219 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
220 idcode = s3c24xx_read_idcode_v5();
222 idcode = s3c24xx_read_idcode_v4();
225 cpu = s3c_lookup_cpu(idcode);
228 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
229 panic("Unknown S3C24XX CPU");
232 printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
234 if (cpu->map_io == NULL || cpu->init == NULL) {
235 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
236 panic("Unsupported S3C24XX CPU");
239 (cpu->map_io)(mach_desc, size);
242 /* s3c24xx_init_clocks
244 * Initialise the clock subsystem and associated information from the
245 * given master crystal value.
247 * xtal = 0 -> use default PLL crystal value (normally 12MHz)
248 * != 0 -> PLL crystal value in Hz
251 void __init s3c24xx_init_clocks(int xtal)
257 panic("s3c24xx_init_clocks: no cpu setup?\n");
259 if (cpu->init_clocks == NULL)
260 panic("s3c24xx_init_clocks: cpu has no clock init\n");
262 (cpu->init_clocks)(xtal);
265 /* uart management */
267 static int nr_uarts __initdata = 0;
269 static struct s3c2410_uartcfg uart_cfgs[3];
271 /* s3c24xx_init_uartdevs
273 * copy the specified platform data and configuration into our central
274 * set of devices, before the data is thrown away after the init process.
276 * This also fills in the array passed to the serial driver for the
277 * early initialisation of the console.
280 void __init s3c24xx_init_uartdevs(char *name,
281 struct s3c24xx_uart_resources *res,
282 struct s3c2410_uartcfg *cfg, int no)
284 struct platform_device *platdev;
285 struct s3c2410_uartcfg *cfgptr = uart_cfgs;
286 struct s3c24xx_uart_resources *resp;
289 memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
291 for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
292 platdev = s3c24xx_uart_src[cfgptr->hwport];
294 resp = res + cfgptr->hwport;
296 s3c24xx_uart_devs[uart] = platdev;
298 platdev->name = name;
299 platdev->resource = resp->resources;
300 platdev->num_resources = resp->nr_resources;
302 platdev->dev.platform_data = cfgptr;
308 void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
313 if (cpu->init_uarts == NULL) {
314 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
316 (cpu->init_uarts)(cfg, no);
319 static int __init s3c_arch_init(void)
323 // do the correct init for cpu
326 panic("s3c_arch_init: NULL cpu\n");
332 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
337 struct platform_device **ptr = board->devices;
340 for (i = 0; i < board->devices_count; i++, ptr++) {
341 ret = platform_device_register(*ptr);
344 printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr);
348 /* mask any error, we may not need all these board
356 arch_initcall(s3c_arch_init);