2 * arch/arm/mach-pxa/time.c
4 * PXA clocksource, clockevents, and OST interrupt handlers.
5 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
7 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
8 * by MontaVista Software, Inc. (Nico, your code rocks!)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/clockchips.h>
19 #include <linux/sched.h>
21 #include <asm/div64.h>
22 #include <asm/cnt32_to_63.h>
23 #include <asm/mach/irq.h>
24 #include <asm/mach/time.h>
25 #include <asm/arch/pxa-regs.h>
28 * This is PXA's sched_clock implementation. This has a resolution
29 * of at least 308 ns and a maximum value of 208 days.
31 * The return value is guaranteed to be monotonic in that range as
32 * long as there is always less than 582 seconds between successive
33 * calls to sched_clock() which should always be the case in practice.
36 #define OSCR2NS_SCALE_FACTOR 10
38 static unsigned long oscr2ns_scale;
40 static void __init set_oscr2ns_scale(unsigned long oscr_rate)
42 unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
46 * We want an even value to automatically clear the top bit
47 * returned by cnt32_to_63() without an additional run time
48 * instruction. So if the LSB is 1 then round it up.
50 if (oscr2ns_scale & 1)
54 unsigned long long sched_clock(void)
56 unsigned long long v = cnt32_to_63(OSCR);
57 return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
62 pxa_ost0_interrupt(int irq, void *dev_id)
65 struct clock_event_device *c = dev_id;
67 if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
68 /* Disarm the compare/match, signal the event. */
71 } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
72 /* Call the event handler as many times as necessary
73 * to recover missed events, if any (if we update
74 * OSMR0 and OSCR0 is still ahead of us, we've missed
75 * the event). As we're dealing with that, re-arm the
76 * compare/match for the next event.
80 * There's a latency between the instruction that
81 * writes to OSMR0 and the actual commit to the
82 * physical hardware, because the CPU doesn't (have
83 * to) run at bus speed, there's a write buffer
84 * between the CPU and the bus, etc. etc. So if the
85 * target OSCR0 is "very close", to the OSMR0 load
86 * value, the update to OSMR0 might not get to the
87 * hardware in time and we'll miss that interrupt.
89 * To be safe, if the new OSMR0 is "very close" to the
90 * target OSCR0 value, we call the event_handler as
91 * though the event actually happened. According to
92 * Nico's comment in the previous version of this
93 * code, experience has shown that 6 OSCR ticks is
94 * "very close" but he went with 8. We will use 16,
95 * based on the results of testing on PXA270.
97 * To be doubly sure, we also tell clkevt via
98 * clockevents_register_device() not to ask for
99 * anything that might put us "very close".
101 #define MIN_OSCR_DELTA 16
104 next_match = (OSMR0 += LATCH);
106 } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
107 && (c->mode == CLOCK_EVT_MODE_PERIODIC));
114 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
116 unsigned long irqflags;
118 raw_local_irq_save(irqflags);
119 OSMR0 = OSCR + delta;
122 raw_local_irq_restore(irqflags);
127 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
129 unsigned long irqflags;
132 case CLOCK_EVT_MODE_PERIODIC:
133 raw_local_irq_save(irqflags);
134 OSMR0 = OSCR + LATCH;
137 raw_local_irq_restore(irqflags);
140 case CLOCK_EVT_MODE_ONESHOT:
141 raw_local_irq_save(irqflags);
143 raw_local_irq_restore(irqflags);
146 case CLOCK_EVT_MODE_UNUSED:
147 case CLOCK_EVT_MODE_SHUTDOWN:
148 /* initializing, released, or preparing for suspend */
149 raw_local_irq_save(irqflags);
151 raw_local_irq_restore(irqflags);
156 static struct clock_event_device ckevt_pxa_osmr0 = {
158 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
161 .cpumask = CPU_MASK_CPU0,
162 .set_next_event = pxa_osmr0_set_next_event,
163 .set_mode = pxa_osmr0_set_mode,
166 static cycle_t pxa_read_oscr(void)
171 static struct clocksource cksrc_pxa_oscr0 = {
174 .read = pxa_read_oscr,
175 .mask = CLOCKSOURCE_MASK(32),
177 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
180 static struct irqaction pxa_ost0_irq = {
182 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
183 .handler = pxa_ost0_interrupt,
184 .dev_id = &ckevt_pxa_osmr0,
187 static void __init pxa_timer_init(void)
190 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
192 set_oscr2ns_scale(CLOCK_TICK_RATE);
194 ckevt_pxa_osmr0.mult =
195 div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
196 ckevt_pxa_osmr0.max_delta_ns =
197 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
198 ckevt_pxa_osmr0.min_delta_ns =
199 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
201 cksrc_pxa_oscr0.mult =
202 clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
204 setup_irq(IRQ_OST0, &pxa_ost0_irq);
206 clocksource_register(&cksrc_pxa_oscr0);
207 clockevents_register_device(&ckevt_pxa_osmr0);
211 static unsigned long osmr[4], oier;
213 static void pxa_timer_suspend(void)
222 static void pxa_timer_resume(void)
231 * OSCR0 is the system timer, which has to increase
232 * monotonically until it rolls over in hardware. The value
233 * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
234 * which is a handy value to restore to OSCR0.
236 OSCR = OSMR0 - LATCH;
239 #define pxa_timer_suspend NULL
240 #define pxa_timer_resume NULL
243 struct sys_timer pxa_timer = {
244 .init = pxa_timer_init,
245 .suspend = pxa_timer_suspend,
246 .resume = pxa_timer_resume,