2 * Low-level PXA250/210 sleep/wakeUp support
5 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
7 * Adapted for PXA by Nicolas Pitre:
8 * Copyright (c) 2002 Monta Vista Software, Inc.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License.
14 #include <linux/config.h>
15 #include <linux/linkage.h>
16 #include <asm/assembler.h>
17 #include <asm/hardware.h>
19 #include <asm/arch/pxa-regs.h>
26 * Forces CPU into sleep state
29 ENTRY(pxa_cpu_suspend)
32 stmfd sp!, {r2 - r12, lr} @ save registers on stack
34 @ get coprocessor registers
35 mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode
36 mrc p15, 0, r4, c15, c1, 0 @ CP access reg
37 mrc p15, 0, r5, c13, c0, 0 @ PID
38 mrc p15, 0, r6, c3, c0, 0 @ domain ID
39 mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
40 mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
41 mrc p15, 0, r9, c1, c0, 0 @ control reg
43 bic r3, r3, #2 @ clear frequency change bit
45 @ store them plus current virtual stack ptr on stack
49 @ preserve phys address of stack
52 ldr r1, =sleep_save_sp
56 bl xscale_flush_kern_cache_all
58 @ Put the processor to sleep
59 @ (also workaround for sighting 28071)
61 @ prepare value for sleep mode
62 mov r1, #3 @ sleep mode
64 @ prepare to put SDRAM into self-refresh manually
67 orr r5, r5, #MDREFR_SLFRSH
69 @ prepare pointer to physical address 0 (virtual mapping in generic.c)
70 mov r2, #UNCACHED_PHYS_0
72 @ Intel PXA255 Specification Update notes problems
73 @ about suspending with PXBus operating above 133MHz
74 @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
76 @ We keep the change-down close to the actual suspend on SDRAM
77 @ as possible to eliminate messing about with the refresh clock
78 @ as the system will restore with the original speed settings
80 @ Ben Dooks, 13-Sep-2004
83 ldr r8, [r6] @ keep original value for resume
85 @ ensure x1 for run and turbo mode with memory clock
86 bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK
87 orr r7, r7, #(1<<5) | (2<<7)
89 @ check that the memory frequency is within limits
90 and r14, r7, #CCCR_L_MASK
92 bicne r7, r7, #CCCR_L_MASK
93 orrne r7, r7, #1 @@ 99.53MHz
95 @ get ready for the change
97 @ note, turbo is not preserved over sleep so there is no
98 @ point in preserving it here. we save it on the stack with the
99 @ other CP registers instead.
101 mcr p14, 0, r0, c6, c0, 0
102 orr r0, r0, #2 @ initiate change bit
104 @ align execution to a cache line
111 @ All needed values are now in registers.
112 @ These last instructions should be in cache
114 @ initiate the frequency change...
116 mcr p14, 0, r0, c6, c0, 0
118 @ restore the original cpu speed value for resume
121 @ put SDRAM into self-refresh
124 @ force address lines low by reading at physical address 0
128 mcr p14, 0, r1, c7, c0, 0
130 20: b 20b @ loop waiting for sleep
135 * entry point from bootloader into kernel during resume
137 * Note: Yes, part of the following code is located into the .data section.
138 * This is to allow sleep_save_sp to be accessed with a relative load
139 * while we can't rely on any MMU translation. We could have put
140 * sleep_save_sp in the .text section as well, but some setups might
141 * insist on it to be truly read-only.
146 ENTRY(pxa_cpu_resume)
147 mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC @ set SVC, irqs off
150 ldr r0, sleep_save_sp @ stack phys addr
151 ldr r2, =resume_after_mmu @ its absolute virtual address
152 ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr
155 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
156 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
158 #ifdef CONFIG_XSCALE_CACHE_ERRATA
159 bic r9, r9, #0x0004 @ see cpu_xscale_proc_init
162 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
163 mcr p15, 0, r4, c15, c1, 0 @ CP access reg
164 mcr p15, 0, r5, c13, c0, 0 @ PID
165 mcr p15, 0, r6, c3, c0, 0 @ domain ID
166 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
167 mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
168 b resume_turn_on_mmu @ cache align execution
172 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc.
174 @ Let us ensure we jump to resume_after_mmu only when the mcr above
175 @ actually took effect. They call it the "cpwait" operation.
176 mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
177 sub pc, r2, r1, lsr #32 @ jump to virtual addr
183 .word 0 @ preserve stack phys ptr here
187 #ifdef CONFIG_XSCALE_CACHE_ERRATA
188 bl cpu_xscale_proc_init
192 ldmfd sp!, {r4 - r12, pc} @ return to caller